共查询到20条相似文献,搜索用时 15 毫秒
1.
As technology scales toward deep submicron, the integration of complete system-on-chip (SoC) designs consisting of large number of Intellectual Property (IP) blocks (cores) on the same silicon die is becoming technically feasible. Until recently, the design-space exploration for SoCs has been mainly focused on the computational aspects of the problem. However, as the number of IP blocks on a single chip and their performance continue to increase, a shift from computation-based to communication-based designs becomes mandatory. As a result, the communication architecture plays a major role in the area, performance and energy consumption of the overall systems [Pasricha S, Dutt N. On-chip communication architectures: system on chip interconnect. Amsterdam: Elsevier Inc.; 2008, Kim J, Verbauwhede I, Chang MCF. Design of an interconnect architecture and signaling technology for parallelism in communication. IEEE Trans VLSI Syst 2007;15(8):881-94].This article presents a structure of a wrapper as a component of Code Division Multiple Access, CDMA, based shared bus architecture in a SoC. Two types of wrappers can be identified, master and slave. A master wrapper is located between the arbiter and CDMA coded physical interconnect, while a slave connects the CDMA coded bus with memory/peripheral module. In the proposal, only bus lines that carry address and data signals are CDMA coded. We implemented a pair of master-slave wrapper described in VHDL and confirmed its functionality using testbenches. Also we synthesized wrappers using a Xilinx Spartan and Virtex devices to determine resource requirements in respect to a number of equivalent gates, communication bandwidth, latency and power consumption. Specifically we involved a Design_Quality, DQ, metric for wrapper performance evaluation. A pair of master-slave wrapper seems to occupy appropriate space, in average 2000 equivalent gates, considering CPU cost of about 30,000 gates, what is less than 8% of hardware overhead per CPU. We also present experimental results which show that benefits of involving CDMA coding relates both to decreasing a number of bus lines and accomplishing simultaneous multiple master-slave connections at relatively low-power consumption and high communication bandwidth. Convenient range indices RW and RR to determine data transfer rate for Write and Read operations in multiprocessor bus systems that use TDMA and CDMA data transfer techniques. The obtained results show that increased data transfer latencies involved by CDMA data transfer are compensated by simultaneous master-slave transfers. 相似文献
2.
3.
A bus architecture that provides high performance while scaling across a range of chip sizes is described. The system on a chip design in which it has been implemented includes both a dedicated processor with a set of embedded system peripherals and system support logic that may be reconfigured by a user in the field. Multiple masters and slaves are provided for in the architecture and included in the dedicated portion of this chip. Designers configure additional bus slave peripherals and support functions in the programmable logic. Dedicated structures extend the bus throughout the user-configurable system logic. The bus is pipelined, uses OR gates, and has separate read and write data. The bus pipeline registers are distributed to provide predictable performance and a synchronous interface to the designer. Bus protocol decoders are also distributed throughout the logic. These protocol decoders handle the complexities of pipelining for the designer. Virtual bus sockets provide all of the physical signals necessary to interface registers to the bus for single-cycle read and write transactions. The physical characteristics and design methods involved in the design of this system on a chip as well as those of the application environment all influenced the design tradeoffs in this architecture 相似文献
4.
Vikram Iyengar Krishnendu Chakrabarty Erik Jan Marinissen 《Journal of Electronic Testing》2002,18(2):213-230
Test access mechanisms (TAMs) and test wrappers are integral parts of a system-on-chip (SOC) test architecture. Prior research has concentrated on only one aspect of the TAM/wrapper design problem at a time, i.e., either optimizing the TAMs for a set of pre-designed wrappers, or optimizing the wrapper for a given TAM width. In this paper, we address a more general problem, that of carrying out TAM design and wrapper optimization in conjunction. We present an efficient algorithm to construct wrappers that reduce the testing time for cores. Our wrapper design algorithm improves on earlier approaches by also reducing the TAM width required to achieve these lower testing times. We present new mathematical models for TAM optimization that use the core testing time values calculated by our wrapper design algorithm. We further present a new enumerative method for TAM optimization that reduces execution time significantly when the number of TAMs being designed is small. Experimental results are presented for an academic SOC as well as an industrial SOC. 相似文献
5.
6.
System-on-chip (SOC) design based on intellectual property (IP) cores has become a growing trend in integrated circuit (IC) design. Testing of such cores is a challenging problem, especially when these cores are deeply embedded in the system chip. The wrapper of the P1500 standard can facilitate the testing of such cores; however, a full-size wrapper is expensive because the hardware overhead is large. If the requirement for testing I/O pins of IP cores is considered and reduced to a minimum during the core design, SOC designers will need to put much less effort into testing the cores. In this paper, a built-in self-test (BIST) technique, which is applicable to both analogue and mixed-signal integrated circuits and is based on the weighted sum of selected node voltages, is proposed. Besides high fault coverage, the proposed BIST technique needs only one extra testing output pin, and only a single dc stimulus is needed to feed at the primary input of the circuit under test (CUT). Hence, the proposed BIST technique is especially suitable for testing IP cores. 相似文献
7.
Embedded cores in a core-based system-on-chip (SOC) are not easily accessible via chip I/O pins. Test-access mechanisms (TAMs) and test wrappers (e.g., the IEEE Standard 1500 wrapper) have been proposed for the testing of embedded cores in a core-based SOC in a modular fashion. We show that such a modular testing approach can also be used for emerging three-dimensional integrated circuits based on through-silicon vias (TSVs). Core-based SOCs based on 3D IC technology are being advocated as a means to continue technology scaling and overcome interconnect-related bottlenecks. We present an optimization technique for minimizing the post-bond test time for 3D core-based SOCs under constraints on the number of TSVs, the TAM bitwidth, and thermal limits. The proposed optimization method is based on a combination of integer linear programming, LP-relaxation, and randomized rounding. It considers the Test Bus and TestRail architectures, and incorporates wire-length constraints in test-access optimization. Simulation results are presented for the ITC 02 SOC Test Benchmarks and the test times are compared to that obtained when methods developed earlier for two-dimensional ICs are applied to 3D ICs. The test time dependence on various 3D parameters (e.g. 3D placement, the number of layers, thermal constraints, and the number of TSVs) is also studied. 相似文献
8.
Shyue-Kung Lu Chih-Hsien Hsu 《Reliability, IEEE Transactions on》2006,55(2):293-306
As the complexity and size of the embedded memories keep increasing, improving the yield of embedded memories is the key step toward improving the overall chip yield of a SOC design. The most well known way to improve the memory yield is by using redundant elements to replace the faulty cells. However, the repair efficiency mainly depends on the type, and the amount of redundancy; and on the redundancy analysis algorithms. Therefore, new types of redundancy based on divided bit-line (DBL), and divided word-line (DWL) techniques are proposed in this work. A memory column (row), including the redundant column (row), is partitioned into column blocks (row blocks), respectively. A row/column block is used as the basic replacement element instead of a row/column for the traditional approaches. Based on the new types of redundancy, three types of fault-tolerant memory (FTM) systems are also proposed. If a redundant row/column block is used as the basic replacement element, then the row block-based FTM (RBFTM)/column block-based (CBFTM) system is used. If both the DWL, and DBL techniques are implemented onto a memory chip, then the hybrid FTM (HFTM) system is achieved. The storage and remapping of faulty addresses can be implemented with a CAM (content addressable memory) block. To achieving better repair efficiency, a novel hybrid block-repair (HBR) algorithm is also proposed. This algorithm is suitable for hardware implementation with negligible overhead. For the HFTM system, the hardware overheads are less than 0.65%, and 0.7% for 64-Kbit SRAM, and 8-Mbit DRAM, respectively. Moreover, the repair rate can be improved significantly. Experimental results show that our approaches can improve the memory fabrication yield significantly. The characteristics of low power and fast access time of DBL and DWL techniques are also preserved. 相似文献
9.
A modify wrapper/test access mechanism(TAM) structure is described to explore the maximal potential capacity of TAM, named “IP cores resource multiplexing(IPRM)”, reducing test application time for DVFS-based multicore System-on-Chips(MSoCs). The IPRM core wrappers, different from standard wrappers, enable to isolated core wrapper resource again to store test data for embedded cores under test. An integer linear programming (ILP) formulation with IPRM wrapper is proposed to improve multi-site test. Experimental results of the ITC’02 SoC Benchmark show that IPRM core wrapper reduces the burdens on ATE effectively, and can reduce the test application time by 10–50%. 相似文献
10.
11.
首先根据生化微传感SOC的应用场合和微传感器的特点,选定CR SARADC作为片内嵌入类型;基于SOC的标准CMOS工艺实现和低功耗的设计目标,分别进行了电容阵列、比较器、开关阵列和SAR控制逻辑等组成单元全定制原理图、版图设计,实现了片内嵌入10位ADC的整体芯片.流片实测结果DNL、INL最大值分别为+/1.0LSB、+/-1.5LSB,功耗仅为4.62mW,满足生化微传感SOC数据转换的片内嵌入要求. 相似文献
12.
13.
Sandeep Koranne 《Journal of Electronic Testing》2002,18(4-5):415-434
In this paper a mathematical formulation and an efficient solution, of the embedded core-based system-on-chip (SOC) test scheduling problem (ECTSP) is presented. The ECTSP can be stated as follows; given a chip with N
C cores each having a test T
i; where T
i takes time
to execute on a test access mechanism (TAM) of width w
j, and a constraint W on the number of top-level test pins; calculate the TAM assignment vector and the schedule for each test T
i, such that the completion time of the full chip test is minimized. All existing approaches have solved the ECTSP by solving the TAM partition and scheduling problem sequentially. In this paper we present an unified approach to solve the ECTSP. We present the first report of a design of reconfigurable core wrapper which allows for a dynamic change in the width of the test access mechanism (TAM) executing a core test. An automatic procedure for the creation of DfT hardware required for reconfiguration using a graph theoretic representation of core wrappers is also presented. For the case of reconfigurable wrappers, efficient algorithms to compute the schedule are presented based upon some recent results in the field of malleable task scheduling. Cases in which the degree of reconfigurability are constrained are considered; the case when only a single core can have reconfigurable wrapper, a schedule with zero TAM idle time can be found in time O(N
C(N
C + W)lgW), and the case when only 2 different wrapper configurations are allowed can be solved in time O(N
C
3). Comparison with existing results on benchmark SOCs show that our algorithms outperform state-of-art ILP formulations not only in schedule makespan, but also significantly reduce computation time. 相似文献
14.
文章介绍了一个面向SOC设计的可变规模的LeD驱动IP核,该IP包括四个独立的LeD驱动单元(DU)。不仅可以通过配置该IP使四个独立的Du分别驱动不同规模的LCD,而且能够实现四个Du级联来面对更复杂的应用场合。此外,设计了一个与wishbone总线相兼容的接口模块wrapper,并将该IP结合wrapper模块嵌入到0R1200平台来进行系统级的仿真验证。仿真结果表明该IP达到了设计要求,且通过修改wrapper模块可使该IP核适用于不同的SOC设计平台。 相似文献
15.
16.
17.
《Very Large Scale Integration (VLSI) Systems, IEEE Transactions on》2009,17(8):1152-1156
18.
Sehgal A. Ozev S. Chakrabarty K. 《Very Large Scale Integration (VLSI) Systems, IEEE Transactions on》2006,14(3):292-304
Many system-on-chips (SOCs) today contain both digital- and analog-embedded cores. Even though the test cost for such mixed-signal SOCs is significantly higher than that for digital SOCs, most prior research in this area has focused exclusively on digital cores. We propose a low-cost test development methodology for mixed-signal SOCs that allows the analog and digital cores to be tested in a unified manner, thereby minimizing the overall test cost. The analog cores in the SOC are wrapped such that they can be accessed using a digital test access mechanism (TAM). We evaluate the impact of the use of analog test wrappers on area overhead and test time. To reduce area overhead, we present an analog test wrapper optimization technique, which is then combined with TAM optimization in a cost-oriented heuristic approach for test scheduling. We also demonstrate the feasibility of using analog wrappers by presenting transistor-level simulations for an analog wrapper and a representative core. We present experimental results for three SOCs from the ITC '02 test benchmarks that have been augmented with three analog cores: an I-Q transmit path pair and an audio CODEC path used in cellular phone applications. 相似文献
19.
详细阐述了一种用于嵌入式系统中的USB总线接口电路,该电路是基于USB专用芯片CH375实现的,并给出了系统硬件实现和应用程序。实验结果表明,该电路具有成本低、可靠性高等特点,可方便地集成到各种嵌入式系统中。 相似文献
20.
System-on-chip test scheduling with reconfigurable core wrappers 总被引:1,自引:0,他引:1
Larsson E. Fujiwara H. 《Very Large Scale Integration (VLSI) Systems, IEEE Transactions on》2006,14(3):305-309
The problem with increasing test application time for testing core-based system-on-chip (SOC) designs is addressed with test architecture design and test scheduling. The scan-chains at each core are configured into a set of wrapper-chains, which by a core wrapper are connected to the test access mechanism (TAM), and the tests are scheduled in such a way that the test time is minimized. In this paper, we make use of reconfigurable core wrappers that, in contrast to standard wrappers, can dynamically change (reconfigure) the number of wrapper-chains during test application. We show that by using reconfigurable wrappers the test scheduling problem is equivalent to independent job scheduling on identical machines, and we make use of an existing preemptive scheduling algorithm that produces an optimal solution in linear time (O(n); n is the number of tests). We also show that the problem can be solved without preemption, and we extend the algorithm to handle: 1) test conflicts due to interconnection tests and 2) cases when the test time of a core limits an optimal usage of the TAM. The overhead in logic is given by the number of configurations, and we show that the upper-bound is three configurations per core. We compare the proposed approach with the existing technique and show, in comparison, that our technique is 2% less from lower bound. 相似文献