全局快门像素技术和CMoS图像传感器形成强大的技术组合

传统上,全局快门像素技术主要用于CCD图像传感器。由于CMOS图像传感器的不断普及,且由于机器视觉、电影制作、工业、汽车和扫描应用要求必须以高图像品质捕捉快速移动的物体,图像传感器供应商Aptina公司已经致力于克服在CMOS图像传感器上使用全局快门像素技术的相关传统障碍。     

高分辨率双快门模式CMOS图像传感器控制电路的设计与仿真

主要介绍了一种可用于空间信息获取的高分辨率双快门模式CMOS图像传感器,分析比较了该CMOS图像传感器卷帘式和同步式两种快门模式的工作原理和特点,设计了两种快门模式的时序控制电路并进行了仿真和验证,结果表明了控制电路设计的正确性,并可适用于空间微纳型卫星的成像系统。     

ViTA 1300：通用CMOS图像传感器

赛普拉斯推出一款面向机器视觉市场的高灵敏度高速CMOS图像传感器。该款全新的130万像素VITA1300传感器结合了管线式和触发式全局快门,具有150帧,秒（fps）的无图像畸变高帧频,而且读出速度很快。     

一种新型CMOS图像传感器的设计

为了提高CMOS图像传感器的图像质量,通过对图像主要的噪声源以及图像失真的分析,提出一种新型的CMOS有源像素图像传感器.该CMOS图像传感器使用4T有源像素,大大提高了图像传感器的灵敏度.通过在传感器中集成图像预处理功能,对改善图像的质量起到了很好的效果.     

低照度CMOS图像传感器技术

与其他固体微光器件相比,低照度CMOS图像传感器具有成本、功耗及体积优势,是固体微光器件发展的重要方向。但目前低照度CMOS图像传感器的微光性能还不能满足夜视应用要求。本文介绍了低照度CMOS图像传感器及提高其灵敏度的几种技术途径,采用低照度技术后CMOS图像传感器性能已接近实用要求。随着CMOS工艺技术的不断发展及低照度CMOS图像传感器研究的不断深入,在不远的将来,低照度CMOS图像传感器将成为固体微光器件的重要一员。     

CMOS图像传感器及其发展趋势

本文简要介绍了CMOS图像传感器的发展历程及工作原理.对CCD图像传感器与CMOS图像传感器的优缺点进行了比较,指出了CMOS图像传感器的技术优势,并讨论了CMOS图像传感器的发展趋势.     

CMOS图像传感器及其研究

介绍了CMOS图像传感器的工作原理,比较了CCD图像传感器与CMOS图像传感器的优缺点,指出了CMOS图像传感器的技术问题和解决途径,综述了CMOS图像传感器的现状和发展趋势.     

消费电子

赛普拉斯流水线式全域曝光快门CMOS图像传感器 赛普拉斯推出一款用于高端机器视觉市场的高敏感度、高速CMOS图像传感器,用于检验机、生物检测（如下一代掌纹读取仪）以及智能交通系统等。250万像素VITA25K传感器拥有单器件最大数据吞吐能力．并带有流水线和触发式全域决门。     

CMOS图像传感器的研究新进展

随着超大规模集成技术的发展,CMOS图像传感器显示出了强劲的发展趋势.简要介绍了CMOS图像传感器的发展历程,在分析CCD和CMOS图像传感器工作原理的基础上,对比了CMOS图像传感器与CCD的特点.重点描述了国外CMOS图像传感器的最新商业化产品状况,同时给出了一些产品的性能参数,最后展望了CMOS图像传感器的未来发展趋势.     

CMOS图像传感器的研究进展

20世纪90年代以来,随着超大规模集成(VLSI)技术的发展,CMOS图像传感器显示出强劲的发展势头.简要介绍了CMOS图像传感器的结构及工作原理,详细比较了CMOS图像传感器与CCD的性能特点,讨论了CMOS图像传感器的关键技术问题.并给出了相应的解决途径,综述了GMOS图像传感器的国内外研究现状,最后对CMOS图像传感器的发展趋势进行了展望.     

A High-Speed, High-Sensitivity Digital CMOS Image Sensor With a Global Shutter and 12-bit Column-Parallel Cyclic A/D Converters

This paper presents a high-speed, high-sensitivity 512times512 CMOS image sensor with column parallel cyclic 12-bit ADCs and a global electronic shutter. Each pixel has a charge amplifier for high charge-to-voltage conversion gain despite of using a large-size photodiode, and two sample-and-hold stages for the global shutter and fixed pattern noise (FPN) canceling. High-speed column-parallel cyclic ADC arrays with 12-bit resolution having a small layout size of 0.09 mm ² are integrated at both sides of image array. A technique for accelerating the conversion speed using variable clocking and sampling capacitance is developed. A digital gain control function using 14-bit temporal digital code is also set in the column parallel ADC. The fabricated chip in 0.25-mum CMOS image sensor technology achieves the full frame rate in excess of 3500 frames/s. The in-pixel charge amplifier achieves the optical sensitivity of 19.9 V/lxmiddots. The signal full scale at the pixel output is 1.8 V at 3.3-V supply and the noise level is measured to be 1.8mV_rms, and the resulting signal dynamic range is 60 dB     

An Improved Global Shutter Pixel with Extended Output Range and Linearity of Compensation for CMOS Image Sensor

An improved global shutter pixel structure with extended output range and linearity of compensation is proposed for CMOS image sensor. The potential switching of the sample and hold capacitor bottom plate outside the array is used to solve the problem of the serious swing limitation, which will attenuate the dynamic range of the image sensor. The non-linear problem caused by the substrate bias effect in the output process of the pixel source follower is solved by using the mirror FD point negative feedback self-establishment technology outside the array. The approach proposed in this paper has been verified in a global shutter CMOS image sensor with a scale of 1024×1024 pixels. The test results show that the output range is expanded from 0.95V to 2V, and the error introduced by the nonlinearity is sharply reduced from 280mV to 0.3mV. Most importantly, the output range expansion circuit does not increase the additional pixel area and the power consumption. The power consumption of linearity correction circuit is only 23.1μW, accounting for less than 0.01％ of the whole chip power consumption.     

CMOS图像传感器IBIS5-B-1300的驱动时序设计

介绍Cypress公司的图像传感器IBIS5-B-1300,分析其特性和工作原理,并对其两种快门方式进行了比较。在此基础上设计它所需要的时序控制电路。选用Xilinx公司的Spartan3系列FPGA芯片XC3S50作为硬件设计平台,对采用不同配置和快门的时序控制电路进行了仿真。实验结果表明,设计的驱动电路能够满足成像器的工作需求。     

CMOS图像传感器用像素级双采样存储技术

多次曝光技术是扩展CM O S APS图像传感器动态范围较为有效的方法,但多于两次的曝光,信号处理复杂,使传感器的帧频受到限制,而像素级双采样存储技术将两次曝光采样及图像组合处理在像素内实现,在获得高动态范围的同时,可有效提高图像实时处理的速度,并且可以工作于高速同步曝光模式。     

脉冲激光辐照CMOS相机的图像间断现象及机理

为了研究脉冲激光辐照CMOS相机时拍摄图像产生间断现象的原因,利用1 064 nm脉冲激光对卷帘快门式CMOS相机进行了辐照实验。在获得的图像中观测到了间断现象,表现为垂直方向上的亮区和暗区,计算表明各帧图像中暗区的行数为固定值。根据CMOS图像传感器积分方式和扫描机制,分析了图像间断现象的形成机理为卷帘快门式CMOS存储的不同时性。理论计算结果与实验结果一致,并理论分析了完全无暗区图像存在的原因。提出了基于多帧间断图像采用拼接手段获得完整连续图像的方法,得到的图像与直接拍摄图像基本一致。     

Global Shutter CMOS Image Sensor With Wide Dynamic Range

A novel concept for global shutter CMOS image sensors with wide dynamic range (WDR) implementation is presented. The proposed imager is based on the multisampling WDR approach and it allows an efficient global shutter pixel implementation achieving small pixel size and high fill factor. The proposed imager provides wide DR by applying adaptive exposure time to each pixel, according to the local illumination intensity level. Two pixel configurations, employing different kinds of a 1-bit in-pixel memory were implemented. An imager, including two different pixels was designed and simulated in 0.18-mum CMOS technology. System architecture and operation are discussed and simulation results are presented.     

A 256×256 pixel smart CMOS image sensor for line-based stereovision applications

This paper presents a 256×256 pixel smart CMOS image sensor for line based vision applications. By combining the edge-based analog processing technique with an active pixel array, a dense and fast on-chip analog image processing has been achieved. The on-chip processing unit includes (1) an analog histogram equalizer, (2) a programmable recursive Gaussian filter, (3) a spatio-temporal differentiator, and (4) a local extrema extractor. An electronic shutter is applied to the active pixel sensor array in order to adapt the exposure time as a function of global illumination. The on-chip histogram equalizer extends the image into a constant and optimal range for all the following processing operators and gives a stable and predictable precision of the analog processing. A prototype chip has been designed and fabricated in a standard 0.8-μm CMOS process with double poly and double metal, giving a pixel pitch of 20 μm and die size of 7×7 mm². A line processing time is compatible with TV line scan period. The worst case power consumption measures 40 mA at 5 V     

CMOS image sensor with NMOS-only global shutter and enhanced responsivity

Most CMOS image sensors today use the rolling shutter approach to control the integration time. This pixel architecture is advantageous where minimal pixel size is required to increase resolution or reduce over all chip size. For imaging of a fast moving object or when used with pulsed illumination, the rolling shutter approach is not suitable since it leads to severe distortion. Therefore, these applications require image sensors with a global shutter pixel architecture, which incorporates a sample-and-hold element in each pixel. Due to the optical exposure of the in-pixel storage element, shutter leakage is critical. First approaches which use separate wells in the pixel to isolate the storage node from the photodiode showed good shutter efficiency, but are bulky and led to large pixels with poor fill factor and bad responsivity. This paper presents an NMOS-only pixel with a global shutter and subthreshold operation of the NMOS sample-and-hold transistor to increase optical responsivity by a factor of five to 9 /spl upsi/V/photon, including fill factor.     

基于LUPA4000图像传感器扩展动态范围方法研究

基于CMOS图像传感器LUPA4000,对双斜率光积分进行研究。选用Altera公司的EP3C25Q240C8N作为硬件设计载体,使用VHDL语言对LUPA4000像素内部驱动信号进行描述,并采用QutartusⅡ软件对所做的设计进行功能仿真,最后采用基于LUPA4000的相机系统,实现了同步快门模式下的双斜率光积分操作。实验结果表明,双斜率光积分有效扩展了普通线性转移成像器的光学动态范围,提升了成像质量。