低温半导体器件模拟的误差限方法

本文从数值方法和求解变量的物理意义两主面出发，提出了适用于低温半导体器件计算机模拟的误差限方法，并且将该方法插入ＭＩＮＩＭＯＳ４．０进行了数值实验．结果表明，设置误差限方法能保证低温半导体器件模拟的数值敛性，并且有较快的收敛速度．     

低温半导体器件模拟中若干问题与对策

低温半导体器件以其优异的性能,可以满足军用和民用等领域中常规器件无法满足的特殊要求.低温微电子学日益成为微电子技术的重要的发展方向,而低温器件计算机模拟则是低温器件分析与设计的重要手段.本文着重讨论了常温下半导体器件的计算机模拟方法在低温下的蜕变及相应的对策,分析了导致常温下方法失效的主要物理参数的低温模型,并提出了低温器件模拟加速收敛的几种数值技术.     

新型纳米尺寸MOSFET器件的模拟和设计

在半导体器件的研制过程中,用计算机数值模拟取代测量方法来优化设计器件的性能参数,则器件的调试周期将显著缩短,费用将大幅度降低。本文简述了新型纳米尺寸MOSFET器件模拟的主要物理模型和数值方法,阐述MOSFET相关器件模拟的国内外研究动态,判断其发展趋势和研究方向。     

低温半导体器件模拟软件包

本文在通用半导体器件模拟软件ＰＩＳＣＥＳ（版本为９００９Ｉ，ＳｕｎＯＳ４．１（Ｚｈｉｐｉｎｇ））的基础上，修改了模型方程，加进了低温参数模型，成功地开发和编制出了适于低温半导体器件模拟软件ＳＥ－ＰＩＳＣＥＳ，模拟了７７Ｋ下二极管的稳态特性、瞬态特性和交流小信号分析，并将模拟结果和３００Ｋ下的作了对比分析．     

亚微米半导体器件模拟方法的探索

本文综述了近十年来半导体器件模拟的发展概况，阐述了漂移扩散模型（ＤＤＭ）、流体动力学模型（ＨＤＭ）、玻耳兹曼模型（ＢＴＭ）、全量子模型（ＱＴＭ）的各自适用范围，概括了玻耳兹曼的一些新解法，ＨＤＭ，ＢＴＭ适合于亚微米半导体器件的模拟。     

磁敏二极管的数值模拟

本文首次实现了具有高复合表面的磁敏半导体器件的数值模拟;探讨了适合于数值模拟的磁敏半导体器件的边界条件及基本方程的定标方法。所得结果与实验数据基本相符,可以说明器件的内部机理,对磁敏器件的优化设计有指导意义。     

双极型压控晶体管直流特性的数值模拟

本文采用数值计算和解析分析相结合的方法,建立了新型功率半导体器件－－有型压控晶体管（ＢＪＭＯＳＦＥＴ）电流－电压特性的数值分析模型;运用Ｍａｔｈｅｍａｔｉｃｓ数学分析软件,模拟得出ＢＪＭＯＳＦＥＴ电压转移特性曲线和电压输出特性曲线;得出的结果说明在相同的器件结构尺寸和工作情况下,与功率ＭＯＳ晶体管相比,导通电压略有增加,但电流容量增加较大。     

一维S－G格式的三维应用

本文提出了一种将一维Ｓ－Ｇ格式应用于三维电流连续性方程的方法。该方法具有经典的多维Ｓ－Ｇ方法的优点，却有效地减小了数值误差，可用于半导体器件模拟。     

一维S－G格式的三维应用

本文提出了一种将一维Ｓ－Ｇ格式应用于三维电流连续性方程的方法。该方法具有经典的多维Ｓ－Ｇ方法的优点，却有效地减小了数值误差，可用于半导体器件模拟。     

半导体器件/电路混合模拟及其在HPM效应中的应用

建立了自行研制的通用二维半导体器件数值模拟软件GSRES与电子电路仿真软件SPICE的接口;实现了半导体器件/电路混合模拟功能,从而将电子系统的高功率微波效应模拟容纳到电路模拟的框架下;给出对CMOS反相器及典型数字电路的混合模拟算例.计算结果验证了该方法的可行性及有效性.     

Two-dimensional analysis of a BiNMOS transistor operating at 77 Kusing a modified PISCES program

The authors present a detailed two-dimensional numerical simulation study on the steady-state and turn-on transient behavior of a BiNMOS device operating at 77 K using PISCES-2B with modified low-temperature models. It is shown that the switching speed of the BiNMOS device, which is designed for operation at room temperature, is degraded for low-temperature operation. The BiNMOS device structure and the low-temperature device models for the two-dimensional (2D) device simulator are described, following by the steady-state and the transient analysis of the BiNMOS device. The turn-on transient performance of the BiNMOS device shows that, at 77 K, the switching time, which is determined by the load-related delay and the intrinsic delay of the bipolar device, increases about 45% from its 300 K value for an output load of 0.1 pF/μm     

Back-gate bias effect on the subthreshold behavior and theswitching performance in an ultrathin SOI CMOS inverter operating at 77and 300 K

The effect of back-gate bias on the subthreshold behavior and the switching performance in an ultrathin SOI CMOS inverter operating at 300 and 77 K is investigated using a low-temperature device simulator. The simulation results show that the nonzero back-gate bias induces hole pile-up at the back interface, which causes opposite effects on the NMOS and PMOS subthreshold characteristics at 300 and 77 K. Throughout the transient process, at 300 K, for V_B=-5 V operation, hole pile-up at the back interface always exists in the NMOS device. Compared to the zero back-gate bias case, at V_B=-5 V, the risetime of the SOI CMOS inverter is over 5% shorter at 77 and 300 K and the falltime is 5% longer. Prepinch-off velocity saturation in the NMOS device dominates the pull-down transient as a result of the smaller electron critical electric field     

77 K versus 300 K operation: the quasi-saturation behavior of aDMOS device and its fully analytical model

A simulation study on the 77-K versus 300-K operation in terms of the quasi-saturation behavior of a DMOS device using low-temperature PISCES is discussed. From the analysis, a closed-form analytical quasi-saturation model for DMOS devices has been derived. Based on the analysis, for a lightly doped substrate (1×10¹⁵ cm^-3), at 77 K, the drain current at quasi-saturation is higher than that at 300 K. For a heavily doped-substrate (1×10¹⁶ cm^-3), at 77 K, the drain current at quasi-saturation is lower. The difference in drain current at quasi-saturation between 77 K and 300 K for different substrate doping densities is attributed to the incomplete ionization and saturated velocity effects     

Comparison of NMOS and PMOS hot carrier effects from 300 to 77 K

Since hot carrier effects can pose a potential limit to device scaling, hot-carrier-induced device degradation has been one of the major concerns in modern device technology. Currently, there is a great interest in pursuing low-temperature operation of MOS devices since it offers many advantages compared to room temperature operation. Also, low-temperature operation is often required for space applications. However, low-temperature operation exacerbates hot carrier reliability of MOS devices. Even though hot carrier effects are significantly worse at low temperature, most of the studies on hot-carrier-induced device degradation were done at room temperature and little has been done at low temperature. In this work, hot-carrier-induced device degradation is characterized from 77 K to room temperature for both NMOS and PMOS devices with the emphasis on low-temperature behavior of hot carrier degradation. For NMOS devices, the worst case bias condition for hot carrier effects is found to be a function of temperature. It is also determined that one of the primary reasons for the great reduction on hot carrier device lifetime at low temperature is that a given amount of damage simply induces a greater reduction on device performance at low temperature. For PMOS devices, the initial damage appears similar for both room temperature and 77 K; however, subsequent annealing indicates that the damage mechanism at 77 K differs markedly from that at 300 K. Hot carrier stressing on PMOS devices at low temperature appears to induce hole generation and substantial interface state creation upon annealing unlike 300 K stressed devices. This finding may have serious reliability implications for PMOS devices operated at cryogenic temperatures     

A two-dimensional simulation of a cooled, submicrometer indium arsenide Schottky-gate FET

A two-dimensional simulation of an InAs, Schottky-gate FET operated at 77 K is reported. A device of 0.25-µm source-drain spacing is assumed. The full field-dependent mobility is treated. The results suggest that such a device would have performance characteristics comparable even to Josephson junctions for high-speed low-power logic applications.     

DIBL in short-channel NMOS devices at 77 K

Detailed experimental and two-dimensional numerical simulation results on drain-induced barrier lowering (DIBL) versus channel length at 300 and 77 K in short-channel NMOS devices are presented. It is found that by decreasing the temperature from 300 to 77 K. DIBL in NMOS devices with effective channel lengths (L) from 0.5 to 2.0 μm is improved for the range of L<0.6 μm and L>1.2 μm, but is worse for L between 0.6 and 1.2 μm. The new version of the two-dimensional device numerical simulation program MINIMOS 4.0, which includes device modeling at cryogenic temperatures, was used to investigate this unique characteristic. The measured DIBL characteristics can be explained physically as the transition from surface DIBL through the subsurface DIBL to the bulk DIBL or punchthrough effect at 300 K, but almost a surface DIBL for the whole range of channel length variation at 77 K. Design considerations for the channel doping profile for low-temperature operation based on keeping the same DIBL and V_TH as required for room-temperature operation are briefly discussed     

High-mobility strained-Si PMOSFET's

Operation and fabrication of a new high channel mobility strained-Si PMOSFET are presented. The growth of high-quality strained Si layer on completely relaxed, step-graded, SiGe buffer layer is demonstrated by gas source MBE. The strained-Si layer is characterized by double crystal X-ray diffraction, photoluminescence, and transmission electron microscopy. The operation of a PMOSFET is shown by device simulation and experiment. The high-mobility strained-Si PMOSFET is fabricated on strained-Si, which is grown epitaxially on a completely relaxed step-graded Si_0.82Ge_0.18 buffer layer on Si(100) substrate. At high vertical fields (high |V_g|), the channel mobility of the strained-Si device is found to be 40% and 200% higher at 300 K and 77 K, respectively, compared to those of the bulk Si device. In the case of the strained-Si device, degradation of channel mobility due to Si/SiO₂ interface scattering is found to be more pronounced compared to that of the bulk Si device. Carrier confinement at the type-II strained-Si/SiGe-buffer interface is clearly demonstrated from device transconductance and C-V measurements at 300 K and 77 K     

Measurement of J/V characteristics of a GaAs submicron n+-n?-n+ diode

The J/V characteristics of a GaAs 0.24 ?m channel length n+-n?-n+ diode have been measured at 8 K, 77 K and 300 K. Good agreement is observed with the J/V predictions recently reported by Awano et al. using a Monte-Carlo simulation of a similar device. This verifies the accuracy of their model, and substantiates their findings that electron transport in a 0.25 ?m channel is near-ballistic at 77 K, with a peak ensemble-average electron velocity approaching 108 cm s?1 for an ensemble-average energy just under 0.36 eV. An effective time-average velocity of about half this value can be expected for the total channel transit.     

Design optimization of high-performance low-temperature 0.18 μmMOSFETs with low-impurity-density channels at supply voltage below 1 V

A 0.18 μm nMOS structure with a vertically nonuniform low-impurity-density channel (LIDC) at 77 K has been studied at supply voltage below 1 volt. An abrupt Gaussian profile is used in the channel. The investigation is based on two-dimensional (2-D) energy transport simulation with appropriate models to account for quantum and low-temperature freeze-out effects. The study focuses on achieving high driving capability and low off-current at low supply voltage and on minimizing short-channel effects. Some guidelines are proposed for improving device performance and suppressing short-channel effects of the LIDC MOS devices. It is shown that at 77 K the optimized nonuniform LIDC 0.18 μm nMOS structure with an abrupt impurity channel profile at supply voltage as low as 0.9 V is able to provide a saturation drain current comparable to that of a room-temperature LIDC 0.1 μm nMOS device at 1.5 V. Furthermore, the 77 K LIDC 0.18 μm nMOS consumes considerably lower dynamic and standby power than the room-temperature 0.1 μm nMOS. These results suggest that the LIDC MOS structure with an abrupt channel profile is very suitable for low-power and high-speed ULSI applications at low temperature     

Hot-electron-induced interface state generation in n-channel MOSFET's at 77 K

Hot-electron-induced degradation in n-channel Si MOSFET's as a result of stress voltages applied at 77 K was studied. The devices were stressed at 77 K for 48 h with a drain voltage of 5 V and a gate voltage corresponding to that at which maximum substrate current was measured. Comparison of pre-stress and post-stress electrical characteristics for forward and for inverse mode operation at room temperature and at 77 K indicate that the observed degradation was due to the generation of hot-electron-induced acceptor interface states at the drain end of the device approximately 0.09 eV below the Si conduction band edge. No trapped charge resulting from hot-electron injection into the gate oxide was observed. The charge associated with the filled interface states had no observable effect on effective channel electron mobility at room temperature, and reduced that at 77 K by no more than 25 percent of the pre-stress value. Operation of CMOS inverters in either logic state (OFF, ON) resulted in no degradation of either device. Operation in a switching mode at 77 K did result in degradation of the n-channel device but not the p-channel FET. The observed degradation is thought to be correlated with the substrate current generated during the switching transient.