Loop细分小波框架对图形传输与去噪的应用

基于细分小波的多分辨率分析是近年来三维图形处理的重要方法,该方法在图形的压缩,去噪,渐近显示和传输,多分辨率绘制和编辑等领域已有很多研究与应用。最近Maria Charina等人提出了一种新的基于细分小波紧框架的多分辨率分析理论,使得细分小波框架在三维图形处理领域的应用成为值得研究的新课题。在深入学习和研究这种全新的多分辨率分析理论的基础上,详细推导了Loop细分小波紧框架的分解和重构公式,应用这些公式实现了多分辨率曲面的构造并将其应用到三维网格图形的渐进传输和去噪中。通过与M.Bertram的双正交Loop细分小波算法的对比,表明基于Loop细分小波紧框架的多分辨率分析算法具有较好的渐进传输和去噪效果。由于通常的输入网格不具有细分连通性,而基于细分曲面的多分辨率分析算法要求它所处理的网格具有这种连通性,所以还特别提出了一种构造既能逼近输入网格又具有细分连通性的网格的简捷算法。     

基于区域分解的并行动态LOD构建算法

面向大规模可视数据的高速绘制问题,提出了一种基于区域分解的并行动态LOD（level-of-detail,层次细节模型）构建算法。算法首先改进了传统的渐进网格方法,实现了基于二次误差测度网格简化算法的渐进网格方法;接着提出了一种基于模型包围盒的区域分解算法,实现了原始模型的自适应区域分解;在每个子区域上,并行地执行渐进网格方法,实现了模型的并行动态LOD构建。实验结果表明,该算法可生成高质量的LOD模型,具备理想的加速比和可扩放性;与串行算法相比,该算法有效地提高了算法的执行效率。     

采用新代价模型的HMA网格资源调度

网格系统为管理和调度跨越不同区域的资源提供了一种虚拟框架。该文提出了一个基于HMA的网格资源调度系统以实现资源发现和调度;给出了一个新型的代价模型,它比传统的代价模型更多地考虑了资源发现代价和资源决策代价。随后,将新型代价模型集成到基于HMA的网格资源调度系统中。对比实验显示,新型代价模型下的最优解优于传统代价模型下的最优解。     

渐进网格简化模型的改进算法

渐进网格模型可以用于层次细节的实现、三维网格的简化及重建等.改进并实现了一种渐进网格生成算法,针对渐进网格在简化和重建过程中各边权值计算中出现的误差,给出一种改进的权值公式,以便更精确地确定各边的优先级.同时针对简化过程中,各个块之间会出现裂缝,提出裂缝消除的方法.实验结果表明,该方法可以有效的简化模型,以满足用户的需求并提高效率.     

面向移动计算终端的渐进几何简化方法

在移动计算终端上进行移动三维图形计算是一个重要的课题.针对移动计算终端屏幕小、计算能力低、无线网络带宽受限等特点,研究如何进行移动三维图形的渐进显示具有十分重要的意义.提出了利用Kobbelt四边形细分算法的逆过程迭代地进行简化的方法,通过迭代地把模型分割为奇点和作为简化模型的偶点,实现了对四边形网格几何模型的渐进式简化;提出了渐进显示的模式,通过把每一层的奇点作为可添加的细节信息,可以支持在终端上渐进显示不同细节模型并实现原模型的无损还原.完整的简化方法简单快速,可以高效地实现移动三维图形的渐进简化显示.最后在型号为Mio 336的PDA上的实验结果表明,研究成果在移动计算终端上进行实时交互等方面具有很好的应用前景.     

一种内存网格的数据预取算法

内存网格(RAM(random access memory) grid)是一种面向广域网上内存资源共享的新型网格系统.它的主要目标是在物理内存不足的情况下,提高内存密集型应用或IO密集型应用的系统性能.内存网格的应用效果取决于网络通信开销.在减少或隐藏网络通信开销的情况下,其性能可以进一步提高.通过对内存网格的分析,设计了一种基于"推"数据的内存网格预取机制.借助数据挖掘领域中序列模式挖掘的方法,提出了相应的预取算法.通过基于真实运行状态的模拟,对预取算法进行了评估和验证.     

位移蝶形细分面片的渐进传输

随着三维激光扫描和建模技术的不断进步，三维网格模型的数据量越来越大．与此同时，无处不在的智能计算要求数据必须能够在网络上进行快速的传输，现有的三维网格渐进传输技术无论是基于任意拓扑结构网格的渐进网格技术，还是基于参数化细分面片的渐进传输技术，都存在着传输数据量大、渐进显示效果差的问题，针对这些缺点，提出了首先利用位移蝶形细分面片重建原来的网格模型，然后对于重建后的位移蝶形细分面片设计了一种新的数据简化方法，进而构造了一种渐进传输算法，该算法在减少传输数据总量的同时，提高了渐进传输的视觉效果。     

基于边优化的三角网格简化算法

在渐进网格算法的基础上,提出一种新的基于边优化的三角网格简化算法。在该方法重建出的多分辨率模型表面上,模型的细节层次呈连续分布,并且能跟随视点位置的变化发生动态变化。实验结果表明,该算法运算速度快,显示效果较好,能有效支持细节层次模型的表示。     

面向内存数据网格的分布式事务保障机制

在线事务处理（online transaction processing,OLTP）应用面临并发量和数据量持续增长的问题,并且高并发读写操作使得后台数据库成为瓶颈。内存数据网格（in-memory data grid,IMDG）是基于内存的新型分布式数据访问平台,是解决系统数据库写操作瓶颈的有效技术途径之一。然而内存数据网格中数据访问操作涉及的数据分布是不可预知的,需要提供分布式事务保障。针对内存数据网格的系统特点,提出了一种分布式事务保障机制,设计实现了事务处理模型、请求处理和数据定位方法以及事务保障协议,并规范化地定义了客户端与服务器端以及服务器端之间的操作接口。在事务处理基准测试TPC-W上的实验结果表明,新机制可以提高在线事务应用的处理速度,并具备良好的扩展性。     

关于三维网格压缩和渐进传输问题的几点探讨

通过对渐进网格（PM）和压缩渐进网格（CPM）技术的探讨,提出了在采用线性插值的方法分批传输压缩数据的同时,动态细化3D模型的几何网格。相应地,对CPM算法进行了简化,以减少解压时的开销,在CPM的基础上使渐进细化网格有更好的显示效果。     

Tuning collective communication for Partitioned Global Address Space programming models

Partitioned Global Address Space (PGAS) languages offer programmers the convenience of a shared memory programming style combined with locality control necessary to run on large-scale distributed memory systems. Even within a PGAS language programmers often need to perform global communication operations such as broadcasts or reductions, which are best performed as collective operations in which a group of threads work together to perform the operation. In this paper we consider the problem of implementing collective communication within PGAS languages and explore some of the design trade-offs in both the interface and implementation. In particular, PGAS collectives have semantic issues that are different than in send-receive style message passing programs, and different implementation approaches that take advantage of the one-sided communication style in these languages. We present an implementation framework for PGAS collectives as part of the GASNet communication layer, which supports shared memory, distributed memory and hybrids. The framework supports a broad set of algorithms for each collective, over which the implementation may be automatically tuned. Finally, we demonstrate the benefit of optimized GASNet collectives using application benchmarks written in UPC, and demonstrate that the GASNet collectives can deliver scalable performance on a variety of state-of-the-art parallel machines including a Cray XT4, an IBM BlueGene/P, and a Sun Constellation system with InfiniBand interconnect.     

P-3PC: a point-to-point communication model for automatic andoptimal decomposition of regular domain problems

One of the most fundamental problems automatic parallelization tools are confronted with is to find an optimal domain decomposition for a given application. For regular domain problems (such as simple matrix manipulations), this task may seem trivial. However, communication costs in message-passing programs often depend significantly on the memory layout of data blocks to be transmitted. As a consequence, straightforward domain decompositions may be non-optimal. In this paper, we introduce a new point-to-point communication model, called P-3PC (Parameterized model based on the Three Paths of Communication), that is specifically designed to overcome this problem. In comparison with related models (e.g. LogGP), P-3PC is similar in complexity, but more accurate in many situations. Although the model is aimed at MPI's standard point-to-point operations, it is applicable to similar message-passing definitions as well. The effectiveness of the model is tested in a framework for automatic parallelization of low-level image processing applications. Experiments are performed on two Beowulf-type systems, each having a different interconnection network and a different MPI implementation. The results show that, where other models frequently fail, P-3PC correctly predicts the communication costs related to any type of domain decomposition     

Information-flow models for shared memory with an application to the PowerPC architecture

This paper introduces a generic framework for defining instructions, programs, and the semantics of their instantiation by operations in a multiprocessor environment. The framework captures information flow between operations in a multiprocessor program by means of a reads-from mapping from read operations to write operations. Two fundamental relations are defined on the operations: a program order between operations which instantiate the program of some processor and view orders which are specific to each shared memory model. An operation cannot read from the "hidden" pastor from the future; the future and the past causality can be examined either relative to the program order or relative to the view orders. A shared memory model specifies, for a given program, the permissible transformation of resource states. The memory model should reflect the programmer's view by citing the guaranteed behavior of the multiprocessor in the interface visible to the programmer. The model should retrain from dictating the design practices that should be followed by the implementation. Our framework allows an architect to reveal the programming view induced by a shared-memory architecture; it serves programmers exploring the limits of the programming interface and guides architecture-level verification. The framework is applicable for complex, commercial architectures as it can capture subtle programming-interface details, exposing the underlying aggressive microarchitecture mechanisms. As an illustration, we define the shared memory model supported by the PowerPC architecture, within our framework.     

EPE‐Mobile—A framework for early performance estimation of mobile applications

Considering the constrained resources of mobile devices, a thorough performance evaluation of a mobile application is crucial. However, performance evaluation in the mobile domain is still a manual and time‐consuming task. The diversity of mobile devices only increases the complexity of this task. We propose EPE‐Mobile, a framework to automate early performance estimation in mobile applications. It is composed of a configurable library of basic operations and an engine that automatically creates a synthetic program based on the specification of a new app. The synthetic program that EPE‐Mobile generates provides feedback for mobile developers at the first design stages and before the actual implementation of a new application. The fast evaluation can also guide developers in optimizing their applications or in choosing devices with the best trade‐off between cost and performance to run a given application. Finally, developers can reuse the data collection infrastructure of the framework to collect performance data during all development stages. We validate the proposed framework using 4 applications from the Android Play Store. Based on their specifications, 4 synthetic programs were generated and executed on different devices. We compared the results to those obtained from the execution of the actual applications in the same devices. Experimental results show that it is possible to create synthetic applications with similar behavior to that of real applications and, thus, classify devices based on the actual application needs. The framework uses aspect‐oriented programming to collect the metrics of interest. This approach provides increased modularity and separation of concerns, thus facilitating the improvement of the framework itself, by adding other metrics or basic operations.     

The FPGA implementation of a one-bit-per-pixel image registration algorithm

The calculation of the motion observed between two images of the same scene is required for many applications such as video compression, panoramic stitching and optic flow algorithms for vehicle navigation. The particular application that we focus on in this paper is the need for small light-weight vehicles, such as unmanned ground or air vehicles, to sense their own motion for use in autonomous navigation algorithms. As the processing is ideally performed on-board these vehicles, there are severe restrictions on the processing environment available to perform the optic flow calculations. This has led to the development of FPGA solutions to calculate optic flow. However the most recent approaches still have extensive on-board memory requirements and make use of complex processing operations such as multiplication and matrix inversion. We present an FPGA implementation of a low complexity version of the Lucas–Kanade registration algorithm. This algorithm operates on one-bit images instead of the standard eight-bit approach and consequently can utilize simple logic operations such as exclusive-or rather than multiplications and also makes very efficient use of the available internal memory and resources.     

一种精简的二维DWT结构设计

设计了一种低功耗的二维离散小波变换(DWT)结构，用于无线传感器网络中的图像压缩。该结构实现了精简复杂性的(5,3)整数离散小波变换，采用流水线和延迟线技术，在获得高运算吞吐率的同时，使数据尽可能被处理单元高效利用，以减少对片内存储器和片外存储器的访问次数。多级二维DWT采用展开方法实现，这种方法可尽早开始下一级变换，不需要大的片内存储器和片内存取操作。模拟试验和FPGA实现验证了系统在满足需要性能的前提下具有低复杂性、低功耗、片内存储器小等优点。     

企业智能化Web商务数据挖掘引擎算法设计与实现

针对现有的数据挖掘引擎难以满足企业不断增长的需求的问题,在传统搜索引擎的基础上提出了一种企业专用的智能化Web商务数据挖掘引擎.从总体上给出了模型框架,得出企业智能化Web商务数据挖掘引擎是一个基于多模型的系统的结论.接着分别详细研究了该引擎的:Web内容挖掘、Web信息获取、客户行为挖掘3个核心模块.并给出了3个模块的详细算法设计和实现过程     

基于Struts-Hibernate架构的权限管理系统的设计与实现

介绍了Struts-Hibernate整合架构,剖析了Struts-Hibernate整合原理和关键技术,针对当前权限管理在维护性、灵活性和完整性等方面的不足,设计并实现了一个基于Struts-Hibernate架构的面向RBAC的权限管理系统（PMS）,实现了用户、角色、权限、资源和操作等管理功能,降低了系统的耦合度,提高了系统的可移植性、可扩展性和安全性,在可扩展的企业级应用开发中有很好的前景。实验结果表明,PMS降低了授权管理的复杂性,减少了管理开销,提高了系统的灵活性和安全性。     

一种主动存储计算机模型

提出了一种新型的主动存储计算机模型，其特征是存储器单元不仅可以有传统的读写操作，还可以有执行操作，这个模型扩展了传统的随机访问计算机（RAM）模型，可以用来研究一些新型计算模式的体系结构机制和算法设计与分析，如SoC、可重构计算、并行计算、网格计算、万维网服务等，对于网格计算，这个模型可用于研究网格协议与执行机制、网格算法的正确性和复杂度以及网格客户端与服务器端的有效交互。