Board level solder joint reliability modeling and testing of TFBGA packages for telecommunication applications

For thin-profile fine-pitch BGA (TFBGA) packages, board level solder joint reliability during the thermal cycling test is a critical issue. In this paper, both global and local parametric 3D FEA fatigue models are established for TFBGA on board with considerations of detailed pad design, realistic shape of solder joint, and nonlinear material properties. They have the capability to predict the fatigue life of solder joint during the thermal cycling test within ±13% error. The fatigue model applied is based on a modified Darveaux’s approach with nonlinear viscoplastic analysis of solder joints. A solder joint damage model is used to establish a connection between the strain energy density (SED) per cycle obtained from the FEA model and the actual characteristic life during the thermal cycling test. For the test vehicles studied, the maximum SED is observed at the top corner of outermost diagonal solder ball. The modeling predicted fatigue life is first correlated to the thermal cycling test results using modified correlation constants, curve-fitted from in-house BGA thermal cycling test data. Subsequently, design analysis is performed to study the effects of 14 key package dimensions, material properties, and thermal cycling test condition. In general, smaller die size, higher solder ball standoff, smaller maximum solder ball diameter, bigger solder mask opening, thinner board, higher mold compound CTE, smaller thermal cycling temperature range, and depopulated array type of ball layout pattern contribute to longer fatigue life.     

Thermal cycling analysis of flip-chip solder joint reliability

The reliability concern in flip-chip-on-board (FCOB) technology is the high thermal mismatch deformation between the silicon die and the printed circuit board that results in large solder joint stresses and strains causing fatigue failure. Accelerated thermal cycling (ATC) test is one of the reliability tests performed to evaluate the fatigue strength of the solder interconnects. Finite element analysis (FEA) was employed to simulate thermal cycling loading for solder joint reliability in electronic assemblies. This study investigates different methods of implementing thermal cycling analysis, namely using the "dwell creep" and "full creep" methods based on a phenomenological approach to modeling time independent plastic and time dependent creep deformations. There are significant differences between the "dwell creep" and "full creep" analysis results for the flip chip solder joint strain responses and the predicted fatigue life. Comparison was made with a rate dependent viscoplastic analysis approach. Investigations on thermal cycling analysis of the temperature range, (ΔT) effects on the predicted fatigue lives of solder joints are reported     

Comprehensive board-level solder joint reliability modeling and testing of QFN and PowerQFN packages

For quad flat non-lead (QFN) packages, board-level solder joint reliability during thermal cycling test is a critical issue. In this paper, a parametric 3D FEA sliced model is established for QFN on board with considerations of detailed pad design, realistic shape of solder joint and solder fillet, and non-linear material properties. It has the capability to predict the fatigue life of solder joint during thermal cycling test within ±34% error. The fatigue model applied is based on a modified Darveaux’s approach with non-linear viscoplastic analysis of solder joints. A solder joint damage model is used to establish a connection between the strain energy density (SED) per cycle obtained from the FEA model and the actual characteristic life during thermal cycling test. For the test vehicles studied, the maximum SED is observed mostly at the top corner of peripheral solder joint. The modeling predicted fatigue life is first correlated to thermal cycling test results using modified correlation constants, curve-fitted from in-house QFN thermal cycling test data. Subsequently, design analysis is performed to study the effects of 17 key package dimensions, material properties, and thermal cycling test condition. Generally, smaller package size, smaller die size, bigger pad size, thinner PCB, higher mold compound CTE, higher solder standoff, and extra soldering at the center pad help to enhance the fatigue life. Comparisons are made with thermal cycling test results to confirm the relative trends of certain effects. Another enhanced QFN design with better solder joint reliability, PowerQFN, is also studied and compared with QFN of the same package size.     

Reliability challenges of automotive power electronics

A high reliability of power electronic modules is an essential requirement for hybrid traction applications. This includes a high capability to withstand the stress of repeated active and passive thermal cycles in order to meet the lifetime requirements. Active power cycling requirements are not especially severe for hybrid traction applications compared to many industrial applications. The lifetime for passive thermal cycles by a change of ambient conditions in contrast is defined by the materials and the architecture of a power module. The classical module design with Cu base plates is limited in lifetime particularly with respect to passive temperature cycles due to CTE mismatch. The advanced pressure contact design eliminates the base plate together with the base plate solder and the terminal solder interconnections and thus enhances the thermal cycling capability. As a synergy effect, this design establishes a very balanced static and transient current distribution for paralleled chips. Finally, the last remaining solder interface – the chip solder layer – can be replaced by an Ag diffusion sinter technology. The presented cycling test results will confirm, that the first 100% solder-free module shows an improved performance in passive and active cycling tests.     

Board level solder joint reliability analysis of stacked die mixed flip-chip and wirebond BGA

Stacked die BGA has recently gained popularity in telecommunication applications. However, its board level solder joint reliability during the thermal cycling test is not as well-studied as common single die BGA. In this paper, solder joint fatigue of lead-free stacked die BGA with mixed flip-chip (FC) and wirebond (WB) interconnect is analyzed in detail. 3D fatigue model is established for stacked die BGA with considerations of detailed pad design, realistic shape of solder ball, and non-linear material properties. The fatigue model applied is based on a modified Darveaux’s approach with non-linear viscoplastic analysis of solder joints. Based on the FC–WB stack die configuration, the critical solder ball is observed located between the top and bottom dice corner, and failure interface is along the top solder/pad interface. The modeling predicted fatigue life is first correlated to the thermal cycling test results using modified correlation constants, curve-fitted from in-house lead-free TFBGA46 (thin-profile fine-pitch BGA) thermal cycling test data. Subsequently, design analyzes are performed to study the effects of 20 key design variations in package dimensions, material properties, and thermal cycling test conditions. In general, thinner PCB and mold compound, thicker substrate, larger top or bottom dice sizes, thicker top die, higher solder ball standoff, larger solder mask opening, smaller PCB pad size, smaller thermal cycling temperature range, longer ramp time, and shorter dwell time contribute to longer fatigue life. SnAgCu is a common lead-free solder, and it has much better board level reliability performance than eutectic solder based on modeling results, especially low stress packages.     

Evolution of microstructure and failure mechanism of lead-free solder interconnections in power cycling and thermal shock tests

Failure mechanisms of lead-free solder interconnections in power cycling and thermal shock tests have been investigated in this work. Even though there are some characteristic differences between the two tests, the failures in both cases were induced by recrystallization-assisted crack nucleation and propagation. The three major differences between the tests were: (i) minimum temperature during power cycling was considerably higher in comparison to thermal shock, (ii) the current flow in the power cycling test resulted in electromigration, and (iii) in the power cycling test heat originates locally from components themselves. These differences were also reflected in the test results in the following way: firstly, in the power cycling test the recrystallization occurred earlier than in the thermal shock test, mainly owing to the higher average temperature and secondly, the enhanced growth of intermetallic compound layer at the anode side due to the electromigration was observed during power cycling.     

Board level solder joint reliability analysis and optimization of pyramidal stacked die BGA packages

Due to requirements of cost-saving and miniaturization, stacked die BGA has recently gained popularity in many applications. However, its board level solder joint reliability during the thermal cycling test is not as well-studied as common single die BGA. In this paper, solder joint fatigue of wirebond stacked die BGA is analyzed in detail. 3D fatigue model is established for stacked die BGA with considerations of detailed pad design, realistic shape of solder ball, and non-linear material properties. The fatigue model applied is based on a modified Darveaux's approach with non-linear viscoplastic analysis of solder joints. The critical solder ball is observed located between the top and bottom dice corner, and failure interface is along the top solder/pad interface. The modeling predicted fatigue life is first correlated to the thermal cycling test results using modified correlation constants, curve-fitted from in-house TFBGA (thin-profile fine-pitch BGA) thermal cycling test data. Subsequently, design analyses are performed to study the effects of 16 key design variations in package dimensions, material properties, and thermal cycling test conditions. In general, smaller top and bottom dice sizes, thicker top or bottom die, thinner PCB, thicker substrate, higher solder ball standoff, larger solder mask opening size, smaller maximum ball diameter, smaller PCB pad size, smaller thermal cycling temperature range, longer ramp time, and shorter dwell time contribute to longer fatigue life. The effect of number of layers of stacked-die is also investigated. Finally, design optimization is performed based on selected critical design variables.     

A new experimental method to evaluate creep fatigue life of flip-chip solder joints with underfill

A new accelerated stress test method was developed to evaluate creep life of flip-chip solder joints with underfill. With this method, a cyclic creep test can be done simply by applying a displacement to the FR-4 printed circuit board (PCB) board in the axial direction. The creep fatigue test was performed under displacement control with real-time electrical continuity monitoring. Test results show that the displacement arising from the force is equivalent to the thermal stress during thermal expansion. It was found that the magnitude of displacement was proportional to the inelastic strain sustained by the solder joints. This indicates that the creep fatigue life obtained will not only reflect the quality of the solder joints, but can also be used to characterize the reliability of the flip-chip assembly. Finite element modeling was also performed to confirm the agreement of deformation of the solder joints under mechanical and thermal loading. Results suggest that deformation and strain of the flip-chip assembly are consistent or comparable between the mechanical and thermal cycling. The failure analysis indicates that fatigue cracks often initiate from the top edge of a corner solder joint in the creep fatigue test, which is similar to what would happen in thermal cycling test. Lastly, the effect of underfill on the creep fatigue test is discussed. It is postulated that the test method is applicable to other flip-chip assemblies, such as conductive adhesive interconnections.     

Thermal transient characteristics of die attach in high power LED PKG

The reliability of packaged electronics strongly depends on the die attach quality because any void or a small delamination may cause instant temperature increase in the die, leading sooner or later to failure in the operation. Die attach materials have a key role in the thermal management of high power LED packages by providing the low thermal resistance between the heat generating LED chips and the heat dissipating heat slug. In this paper, thermal transient characteristics of die attach in high power LED PKG have been studied based on the thermal transient analysis using the evaluation of the structure function of the heat flow path. With high power LED packages fabricated by die attach materials such as Ag paste, solder paste and Au/Sn eutectic bonding, we have demonstrated for characteristics such as cross-section analysis, shear test and visual inspection after shear test of die attach and how to detect die attach failures and to measure thermal resistance values of die attach in high power LED PKG. From the differential structure function of the thermal transient characteristics, we could know the result that die attach quality of Au/Sn eutectic bonding with the thermal resistance of about 3.5 K/W was much better than this of Ag paste and solder paste with the thermal resistance of about 11.5–14.2 K/W and 4.4–4.6 K/W, respectively. From this results, it is possible to fabricate high power LED with a small thermal resistance and a good die attach quality by applying Au/Sn eutectic bonding die attach with a high reliability and a good repeatability.     

Estimation of the degradation rate of multi-crystalline silicon photovoltaic module under thermal cycling stress

The overall power of an outdoor-exposed photovoltaic (PV) module decreases as a result of thermal cycling (TC) stress, due to the formation of cracks between the solder and metal. In this study, the thermal fatigue life of solder (62Sn36Pb2Ag) interconnection between copper and silver metallization in PV module was studied. This paper describes in detail the degradation rate (R_D) prediction model of solder interconnection for crystalline PV module. The R_D prediction model is developed which based on published constitutive equations for solder and TC test results on actual PV module. The finite element method was employed to study the creep strain energy density of solder interconnections in TC conditions. Three types of accelerated tests were conducted to determine the prediction model parameters. R_D in benchmark condition is predicted and compared with those of TC conditions.     

Reliability of CSP Interconnections Under Mechanical Shock Loading Conditions

Failure modes and mechanisms under mechanical shock loading were studied by employing the statistical and fractographic research methods, and the finite element (FE) analysis. The SnAgCu-bumped components were reflow-soldered with the SnAgCu solder paste on Ni(P)|Au-coated and organic solderability preservative-coated multilayer printed wiring boards with and without micro-via structure in the soldering pads. The component boards were designed, fabricated, assembled, and drop tested according to the JESD22-B111 standard for portable electronic products. The test data were analyzed by utilizing the Weibull statistics, and the characteristic lifetimes (eta) and shape parameters (beta) were calculated. Statistically significant differences in the reliability were found between the different coating materials and pad structures. The results on the failed assemblies showed good correlation between the failure modes and the FE calculations. Under high deformation rates the solder material undergoes strong strain-rate hardening, which increases the stresses in the interconnections as compared to those in the thermal cycling tests. Therefore, the failure mechanisms under high deformation rates differed essentially from those observed in thermal cycling tests     

The Reliability of Microalloyed Sn-Ag-Cu Solder Interconnections Under Cyclic Thermal and Mechanical Shock Loading

In this study, the performance of three microalloyed Sn-Ag-Cu solder interconnection compositions (Sn-3.1Ag-0.52Cu, Sn-3.0Ag-0.52Cu-0.24Bi, and Sn-1.1Ag-0.52Cu-0.1Ni) was compared under mechanical shock loading (JESD22-B111 standard) and cyclic thermal loading (40 ± 125°C, 42 min cycle) conditions. In the drop tests, the component boards with the low-silver nickel-containing composition (Sn-Ag-Cu-Ni) showed the highest average number of drops-to-failure, while those with the bismuth-containing alloy (Sn-Ag-Cu-Bi) showed the lowest. Results of the thermal cycling tests showed that boards with Sn-Ag-Cu-Bi interconnections performed the best, while those with Sn-Ag-Cu-Ni performed the worst. Sn-Ag-Cu was placed in the middle in both tests. In this paper, we demonstrate that solder strength is an essential reliability factor and that higher strength can be beneficial for thermal cycling reliability but detrimental to drop reliability. We discuss these findings from the perspective of the microstructures and mechanical properties of the three solder interconnection compositions and, based on a comprehensive literature review, investigate how the differences in the solder compositions influence the mechanical properties of the interconnections and discuss how the differences are reflected in the failure mechanisms under both loading conditions.     

Evaluation of the impact of the physical dimensions and material of the semiconductor chip on the reliability of Sn3.5Ag solder interconnect in power electronic module: A finite element analysis perspective

This paper primarily focuses on an evaluation study for the temperature cycling capability of tin silver solder interconnect in power electronic applications by the impact of die dimensions and die material properties. The study was investigated on finite element analysis perspective on chip/solder/substrate structure. A commercially available chip was chosen in the finite element analysis (FEA) as the nominal base die. Two thermal cycle profiles were utilised. The effect of die area, die thickness and material properties (Si and SiC) on the thermal cycling capability of the solder layer was investigated from FEA perspective. From the FEA, it was concluded that decrease in die thickness resulting in increment of thermal cycling capability of solder layer for both material (Si and SiC). Increase in die area increases the thermal cycling capability of solder. For higher ΔT thermal cycle, solder under SiC die perform better than solder under Si die in terms of thermal cycling capability. When the die thickness become smaller than a threshold value of the thermal cycle regime, solder under Si die have better thermal cycling capability than solder under SiC die. Additionally a parametric study was undertaken for a SiC chip/substrate structure under high ∆ T temperature cycling profile for solder layer geometric parameter (wetting angle, titling angle and thickness). From the parametric study which utilised design of experiments (DoE), a wavelet radial basis surrogate model was generated. A sensitivity analysis was performed on surrogate model in order to identify the most influencing parameter. From the sensitivity analysis, it was concluded that wetting angle and solder layer thickness of solder layer have significant impact on the thermal cycling capability of the solder layer.     

Application of coupled electro-thermal and physics-of-failure-based analysis to the design of accelerated life tests for power modules

In the reliability theme a central activity is to investigate, characterize and understand the contributory wear-out and overstress mechanisms to meet through-life reliability targets. For power modules, it is critical to understand the response of typical wear-out mechanisms, for example wire-bond lifting and solder degradation, to in-service environmental and load-induced thermal cycling. This paper presents the use of a reduced-order thermal model coupled with physics-of-failure-based life models to quantify the wear-out rates and life consumption for the dominant failure mechanisms under prospective in-service and qualification test conditions. When applied in the design of accelerated life and qualification tests it can be used to design tests that separate the failure mechanisms (e.g. wire-bond and substrate-solder) and provide predictions of conditions that yield a minimum elapsed test time. The combined approach provides a useful tool for reliability assessment and estimation of remaining useful life which can be used at the design stage or in-service. An example case study shows that it is possible to determine the actual power cycling frequency for which failure occurs in the shortest elapsed time. The results demonstrate that bond-wire degradation is the dominant failure mechanism for all power cycling conditions whereas substrate-solder failure dominates for externally applied (ambient or passive) thermal cycling.     

Effect of Size of Lid-Substrate Adhesive on Reliability of Solder Balls in Thermally Enhanced Flip Chip PBGA Packages

Six design cases of lid-substrate adhesive with various combinations of widths and heights were analyzed to investigate how the size of the adhesive affects the reliability of the solder balls of thermally enhanced flip chip plastic ball grid array (FC-PBGA) packages in thermal cycling tests. Analysis results were compared with data on the reliability of conventional FC-PBGA packages. Thermal-mechanical behavior was simulated by the finite element (FE) method and the eutectic solder was assumed to exhibit elastic-viscoplastic behavior. The temperature-dependent nonlinear stress/strain relationship of the adhesive was experimentally determined and used in the FE analysis. Darveaux's model was employed to obtain the predicted fatigue life of the solder ball. Simulation results reveal that the fatigue life of the solder balls in thermally enhanced FC-PBGA packages is much shorter than that in conventional FC-PBGA packages, and the life of solder balls increases with both the width and the height of the adhesive. However, the effect of the width of the adhesive on the reliability of the solder ball is stronger than that of the height. Moreover, increasing either the width or the height reduces the plastic strain in the adhesive at critical locations, indicating that the reliability of the adhesive can be improved by its size. The predicted results of the life of solder balls for some selected studied packages are also compared with experimental data from thermal cycling tests in the paper     

Reliability evaluations for board-level chip-scale packages under coupled power and thermal cycling test conditions

To evaluate conjointly the effects of ambient temperature fluctuation and operation bias on the reliability of board-level electronic packages, a coupled power and thermal cycling test has been proposed. In this study, the sequential thermal–mechanical coupling analysis, which solves in turn the transient temperature field and subsequent thermomechanical deformations, is performed to investigate thermal characteristics along with fatigue reliability of board-level thin-profile fine-pitch ball grid array chip-scale packages under coupled power and thermal cycling test conditions. Effects of different power cycling durations are studied. A pure thermal cycling condition is also examined and compared. Numerical results indicate that, for the coupled power and thermal cycling test, a shorter power cycling duration in general leads to a shorter fatigue life. However, the temperature compensation effect elongates the fatigue life under certain power cycling durations.     

Chip-scale packaging of power devices and its application inintegrated power electronics modules

A power electronics packaging technology utilizing chip-scale packaged (CSP) power devices to build three-dimensional (3-D) integrated power electronics modules (IPEMs) is presented in this paper. The chip-scale packaging structure, termed die dimensional ball grid array (D²BGA), eliminates wire bonds by using stacked solder joints to interconnect power chips. D²BGA package consists of a power chip, inner solder caps, high-lead solder balls, and molding resin. It has the same lateral dimensions as the starting power chip, which makes high-density packaging and module miniaturization possible. This package enables the power chip to combine excellent thermal transfer, high current handling capability, improved electrical characteristics, and ultralow profile packaging. Electrical tests show that the V_CE(sat) and on-resistance of the D²BGA high speed insulated-gate-bipolar transistors (IGBTs) are improved by 20% and 30% respectively by eliminating the device wirebonds and other external interconnections, such as the leadframe. In this paper, we present the design, reliability, and processing issues of D²BGA package, and the implementation of these chip-scale packaged power devices in building 30 kW half-bridge power converter modules. The electrical and reliability test results of the packaged devices and the power modules are reported     

A Study on the Thermal Fatigue Behavior of Solder Joints Under Power Cycling Conditions

Failure mechanisms exposed by environmental accelerating testing methods such as thermal cycling or thermal shock test, may differ from those at service operating conditions. While the device is heated up or cooled down evenly on its external surface during environmental testing, real operating powered devices experience temperature gradients caused by internal local heating, components' different heat dissipation capability, and ambient temperature variation, etc. In this study, a power cycling technique is introduced to better approximate the field operating conditions so as to activate the field failure modes. Power cycling thermal fatigue test is performed with different ball grid array solder joints, that is, lead contained [Sn/37 Pb (SP)] and lead free [Sn/4.0Ag/0.5 Cu (SAC)], and the result is compared. In order to account for the thermal fatigue life behavior discrepancy for different solder joint composition, real time Moire interferometry is applied to measure the global/local thermo-mechanical behavior during power cycling excursion. Effective damage parameter, the total average shear strain, is extracted from the experiment and applied to account for the difference in fatigue life result of two different solders. In addition, amount of experimentally measured total average shear strain is mutually verified with finite element method analysis. It is clear that total average shear strain of a solder joint can be an effective damage parameter to predict thermo-mechanical fatigue life. A physical mechanism in terms of thermal material property of solder joints' is proposed to offer some thoughts to abnormal shear strain behavior that leads to discrepancies in fatigue life of two solders. An importance of power cycling testing method is emphasized for certain package designs.     

Finite element based fatigue life estimation of the solder joints with effect of intermetallic compound growth

This paper develops an analysis procedure to study the effects of intermetallic compound (IMC) growth on the fatigue life of 63Sn-37Pb (lead-rich)/96.5Sn-3.5Ag (lead-free) solder balls for flip-chip plastic ball grid array packages under thermal cycling test conditions. In this analysis procedure, the thickness of the IMC increased with the number of thermal cycles, and was determined using the growth rate equation. A series of non-linear finite element analyses was conducted to simulate the stress/strain history at the critical locations of the solder balls with various IMC thicknesses in thermal cycling tests. The simulated stress/strain results were then employed in a fatigue life prediction model to determine the relationship between the predicted fatigue life of the solder ball and the IMC thickness. Based on the concept of continuous damage accumulation and incorporated with the linear damage rule, this study defines the damage of each thermal cycle as the reciprocal of the predicted fatigue life of the solder joints with the corresponding IMC thickness. The final fatigue failure of the solder ball was determined as the number of cycles corresponding to the cumulative damage equal to unity. Results show that the solder joint fatigue life decreased as the IMC thickness increased. Moreover, the predicted thermal fatigue life of lead-rich solders based on the effects of IMC growth is apparently smaller than that without considering the IMC growth in the reliability analysis. Results also show that the influence of the IMC thickness on the fatigue life prediction of the lead-free solder joint can be ignored.     

Reliability of lead-free interconnections under consecutive thermal and mechanical loadings

To simulate more realistically the effects of strains and stresses on the reliability of portable electronic products, lead-free test assemblies were thermally cycled (−45°C/+125°C, 15-min. dwell time, 750 cycles) or isothermally annealed (125°C, 500 h) before the standard drop test. The average number of drops to failure increased when the thermal cycling was performed before the drop test (1,500 G deceleration, 0.5 ms half-sine pulse). However, the difference was not statistically significant due to the large dispersion in the number of drops to failure of the assemblies drop tested after the thermal cycling. On the other hand, the average number of drops to failure decreased significantly when the isothermal annealing was carried out before the drop test. The failure analysis revealed four different failure modes: (1) cracking of the reaction layers on either side of the interconnections, (2) cracking of the bulk solder, (3) mixed mode of component-side intermetallic and bulk solder cracking, and (4) voidassisted cracking of the component-side Cu₃Sn layer. The assemblies that were not thermally cycled or annealed exhibited only type (1) failure mode. The interconnections that were thermally cycled before the drop test failed by mode (2) or mode (3). The drop test reliability of the thermally cycled interconnections was found to depend on the extent of recrystallization generated during the thermal cycling. This also explains the observed wide dispersion in the number of drops to failure. On the other hand, the test boards that were isothermally annealed before the drop testing failed by mode (4).