Reliability of submicron InGaAs/InP DHBT under thermal and electrical stresses

We report on the reliability of InGaAs/InP DHBT technology which has applications in very high-speed ICs (over 100 Gbits/s). This work presents the results of accelerated aging tests under thermal and electrical stresses performed on HBT up to 2000 h. Stress conditions consist in applying collector–emitter bias V_CE from 1.3 to 2.7 V and collector current densities J_C of 400 and 610 kA/cm². The corresponding junction temperatures T_J extends from 83 to 137 °C. The base current ideality factor η_B increase and the current gain β decrease have revealed a degradation of the base–emitter junction. The normalized current gain β_norm drop has occurred earlier for higher V_CE and/or higher T_J. A 20% decrease of β_norm chosen as the failure criterion leads to an activation energy of 1.1 eV.     

Common-base multi-finger submicron InGaAs/InP double heterojunction bipolar transistor with fmax of 305 GHz

A layout of a common-base four-finger InGaAs/InP double heterostructure bipolar transistor (DHBT) has been designed and the corresponding DHBT has been fabricated successfully by using planarization technology. The area of each emitter finger was 1 × 15 μm². The breakdown voltage was more than 7 V, the current could be more than 100 mA. The maximum output power can be more than 80 mW derived from the DC characteristics. The maximum oscillation frequency was as high as 305 GHz at I_C = 50 mA and V_CB = 1.5 V. The DHBT is thus promising for the medium power amplifier and voltage controlled oscillator (VCO) applications at W band and higher frequencies.     

Effects of arsenic mole fraction x on the gain characteristics of type-II InP/GaAsxSb1−x DHBTs

The static gain characteristics of N–p–N InP/GaAs_xSb_1?x/InP double heterojunction bipolar transistors (DHBTs) were studied as a function of the base arsenic (As) mole fraction x. Compared to the devices with a lattice-matched base (x = 0.51), a current gain improvement largely arising from a base current reduction is observed in DHBTs with higher As base mole fractions (and consequently a reduced type-II conduction band discontinuity ΔE_C at the emitter-base heterojunction). Both the surface periphery and the intrinsic recombination currents decrease markedly as the base arsenic concentration increases. The present work therefore unambiguously demonstrates that the emitter type-II conduction band discontinuity between the InP emitter and the GaAs_xSb_1?x base enhances the undesirable emitter size effects (ESEs) and increases intrinsic recombination currents directly under the emitter contact.     

High fmax InP double heterojunction bipolar transistorswith chirped InGaAs/InP superlattice base-collector junction grown byCBE

We report the performance of InP Double Heterojunction Bipolar Transistors (DHBT's) with a chirped InGaAs/InP superlattice B-C junction grown by CBE. The B-C junction of the DHBT was graded with a 10-period InGaAs/InP chirped superlattice (CSL) between the InGaAs base and the lightly doped InP collector. A highly doped thin layer was also included at the end of the CSL to offset the quasi-electric field arising from the grade and suppress further the carrier blocking effect across the B-C heterojunction. The InP/InGaAs CSL DHBT demonstrated a high BV_CEO of 18.3 V with a typical current gain of 55 with minimal carrier blocking up to high current densities. Maximum cutoff frequencies of f_max=146 GHz and f_r=71 GHz were obtained from the fabricated 2×10 μm²-emitter DHBT     

MBE生长的InP DHBT的性能

报道了一种自对准InP/InGaAs 双异质结双极晶体管的器件性能.成功制作了U型发射极尺寸为2μm×12μm的器件,其峰值共射直流增益超过300,残余电压约为0.16V,膝点电压仅为0.6V,而击穿电压约为6V.器件的截至频率达到80GHz,最大震荡频率为40GHz.这些特性使此类器件更适合于低压、低功耗及高频方面的应用.     

Preliminary results of storage accelerated aging test on InP/InGaAs DHBT

We report on the reliability of InP HBT technology which has applications in very high-speed ICs. This work presents the storage accelerated aging tests results performed on InP/InGaAs HBT at stress temperatures of 180, 210 and 240 °C up to 3000 h. We have performed aging tests for two generations of InP HBT which differ from the collector doping level and from material used for planarization. From the Gummel plots, we note that the major degradation mechanism is located at the base–emitter junction periphery. Investigations on the physical origin of the observed failure mechanism has been performed using TCAD simulations.     

带有复合掺杂层集电区的InP/InGaAs/InP DHBT直流特性分析

设计了一种新结构InP/InGaAs/InP双异质结双极晶体管(DHBT),在集电区与基区之间插入n -InP层,以降低集电结的导带势垒尖峰,克服电流阻挡效应.采用基于热场发射和连续性方程的发射透射模型,计算了n -InP插入层掺杂浓度和厚度对InP/InGaAs/InP DHBT集电结导带有效势垒高度和I-V特性的影响.结果表明,当n -InP插入层掺杂浓度为3×1019cm-3、厚度为3nm时,可以获得较好的器件特性.采用气态源分子束外延(GSMBE)技术成功地生长出InP/InGaAs/InP DHBT结构材料.器件研制结果表明,所设计的DHBT材料结构能有效降低集电结的导带势垒尖峰,显著改善器件的输出特性.     

ECR plasma etch fabrication of C-doped base InGaAs/InP DHBT structures: A comparison of CH4/H2/Ar vs BCl3/N2 plasma etch chemistries

We compare ECR plasma etch fabrication of self-aligned thin emitter carbondoped base InGaAs/InP DHBT structures using either CH₄/H₂/Ar or BCl₃/N₂ etch chemistries. Detrimental hydrogen passivation of the carbon doping in the base region of our structure during CH₄/H₂/Ar dry etching of the emitter region is observed. Initial conductivity is not recovered with annealing up to a temperature of 500°C. This passivation is not due to damage from the dry etching or from the MOMBE growth process, since DHBT structures which are ECR plasma etched in BCl₃/N₂ have the same electrical characteristics as wet etched controls. It is due to hydrogen implantation from the plasma exposure. This is supported with secondary ion mass spectroscopy profiles of structures which are etched in CH₄/D₂/Ar showing an accumulation of deuterium in the C-doped base region.     

Pseudomorphic AlInP/InP heterojunction bipolar transistors

Novel InP-based heterojunction bipolar transistors (HBTs) using an AlInP pseudomorphic emitter, together with an InP base and collector, have been fabricated. By using InP as both base and collector, the advantage of high electron velocity and high breakdown field of InP collectors are obtained without the problem associated with the energy barrier between the more standard InGaAs/InP base and collector heterojunction. Epitaxial layers were grown by gas-source molecular beam epitaxy (GSMBE). The 200 Å pseudomorphic emitter had an aluminium fraction of 15%, sufficiently suppressing hole injection from the base. The DC gain for 40×40 μm² devices reached 18. The breakdown voltage BV_CEO of 10 V is an improvement over devices with InGaAs base and collector layers     

Comparative investigation of InP/InGaAs heterostructure-emitter tunneling and superlattice bipolar transistors

In this article, the characteristics of InP/InGaAs heterostructure-emitter bipolar transistors with 30 n-InP layer tunneling layers and a five-period InP/InGaAs superlattice are demonstrated and comparatively investigated by experimentally results and analysis. In the three devices, a 200 Å n-In_0.53Ga_0.47As layer together with an n-InP tunneling emitter layer (or n-InP/n-InGaAs superlattice) forms heterostructure emitter to decrease collector-emitter offset voltage. The results exhibits that the largest collector current and current gain are obtained for the tunneling transistor with a 30 Å n-InP tunneling emitter layer. On the other hand, some of holes injecting from base to emitter will be blocked at n-InP/n-InGaAs heterojunction due to the relatively small hole transmission coefficient in superlattice device, which will result in a considerable base recombination current in the n-InGaAs layer. Therefore, the collector current and current gain of the superlattice device are the smallest values among of the devices.     

15-nm base type-II InP/GaAsSb/InP DHBTs with F/sub T/=384 GHz and a 6-V BV/sub CEO/

Type-II InP/GaAsSb/InP double heterojunction bipolar transistors (DHBTs) with a 15-nm base were fabricated by contact lithography: 0.73/spl times/11 /spl mu/m/sup 2/ emitter devices feature f/sub T/=384GHz (f/sub MAX/=262GHz) and BV/sub CEO/=6V. This is the highest f/sub T/ ever reported for InP/GaAsSb DHBTs, and an "all-technology" record f/sub T//spl times/BV/sub CEO/ product of 2304 GHz/spl middot/V. This result is credited to the favorable scaling of InP/GaAsSb/InP DHBT breakdown voltages (BV/sub CEO/) in thin collector structures.     

High-speed, high-current-gain p-n-p InP/InGaAs heterojunctionbipolar transistors

p-n-p InP/InGaAs heterojunction bipolar transistors (HBTs) are reported for the first time. The transistors, grown by metal organic molecular beam epitaxy (MOMBE), exhibited maximum DC current gain values up to 420 for a base doping level of 4×10¹⁸ cm^-3 . Small-signal measurements on self-aligned transistors with 3-μm×8-μm emitter area indicated the unity gain cutoff frequency value of 10.5 GHz and the inferred maximum frequency of oscillation of 25 GHz. The results clearly demonstrate the feasibility of complementary integrated circuits in the InP material system     

High breakdown voltage InGaAs/InP double heterojunction bipolar transistors with fmax=256 GHz and BVCEO= 8.3 V

正An InGaAs/InP DHBT with an InGaAsP composite collector is designed and fabricated using triple mesa structural and planarization technology.All processes are on 3-inch wafers.The DHBT with an emitter area of 1 x 15μm~2 exhibits a current cutoff frequency f_t = 170 GHz and a maximum oscillation frequency f_(max) = 256 GHz.The breakdown voltage is 8.3 V,which is to our knowledge the highest BV_(CEO) ever reported for InGaAs/InP DHBTs in China with comparable high frequency performances.The high speed InGaAs/InP DHBTs with high breakdown voltage are promising for voltage-controlled oscillator and mixer applications at W band or even higher frequencies.     

Bipolar transistor with quantum well base

We report in this study the modeling of a heterostructure bipolar transistor (HBT) where the base is designed as a quantum well. The transistor structure consists of a base layer of GaAs that is heavily p-type doped. The 0.024 μm base is sandwiched between wide band gap In_xGa_1?xP which composes the n-type emitter and collector layers immediately adjacent to the base. The thickness of the base was chosen so that it is comparable to the wavelength of the electrons passing though it. There are two heavily doped cap layers of InGaAs at the emitter contact. The remainder of the emitter and collector regions are composed of GaAs. The purpose of this design is to filter the energies and velocities of electrons as they pass through the base region that forms a quantum barrier to electrons and a quantum well to holes. This should result in a significant decrease of noise in comparison to that observed in non-quantum base HBTs. As expected, the thin quantum well improves the collection of injected carriers, which in turn boosts the DC gain (β) to 750 and increases the power of the novel transistor by a factor of six, in comparison to a commercially available HBT with a similar non-quantum well structure. At high frequencies, the gain of the device is increased by about 5 dB over the non-quantum base HBT that this device is based upon. Additionally, the cutoff frequency is improved from 20 to 50 GHz. Modeling of the novel transistor was done using Silvaco ATLAS?. This study will continue with the fabrication of experimental wafers.     

Optimization of the base electrode for InGaAs/InP DHBT structures with a buried emitter-base junction

We have optimized the base electrode for InGaAs/InP based double heterojunction bipolar transistors with a buried emitter-base junction. For the buried emitter-base structure, the base metal is diffused through a thin graded quaternary region, which is doped lightly n-type, to make ohmic contact to the p⁺InGaAs base region. The metal diffusion depth must be controlled, or contact will also be made to the collector region. Several metal schemes were evaluated. An alloy of Pd/Pt/Au was the best choice for the base metal, since it had the lowest contact resistance and a sufficient diffusion depth after annealing. The Pd diffusion depth was easily controlled by limiting the thickness to 50?, and using ample Pt, at least 350?, as a barrier metal to the top layer of Au. Devices with a 500? base region show no degradation in dc characteristics after operation at an emitter current density of 90 kA/cm² and a collector bias, V_CE, of 2V at room temperature for over 500 h. Typical common emitter current gain was 120. An f_t of 95 GHz and f_max, of 131 GHz were achieved for 2×4 μm² emitter size devices.     

GaInP/GaAs double heterojunction bipolar transistor with highfT, fmax, and breakdown voltage

We report on the dc and microwave performance of an MOCVD-grown carbon-doped GaInP/GaAs double heterojunction bipolar transistor (DHBT) with a thin highly doped n-type GaInP layer in the collector. The DHBT showed improved current-voltage characteristics at low collector-emitter bias compared with those of a DHBT without the heavily doped GaInP layer, while maintaining a high breakdown voltage (BV_CEO~20 V). Small area, self-aligned emitter transistors with two 2×5 μm² emitter fingers were fabricated and exhibited f_T and f_max of 53 GHz and 75 GHz, respectively. These results indicate the promise of carbon-doped base GaInP/GaAs DHBT's for high-power microwave applications     

High-gain, high-speed InP/InGaAs double-heterojunction bipolartransistors with a step-graded base-collector heterojunction

We show that by using InP for the emitter and collector layers, and a thin high-doped base layer, it is possible to achieve both a high DC current gain and a high maximum frequency of oscillation. We have fabricated InP/InGaAs double heterojunction bipolar transistors (DHBT's) with cutoff frequencies f_T and f_max of 92 and 95 GHz, respectively, with a DC current gain of over 100. The maximum cutoff frequencies were 107 and 104 GHz     

Graded base type-II InP/GaAsSb DHBT with f/sub T/=475 GHz

The first demonstration of a type-II InP/GaAsSb double heterojunction bipolar transistor (DHBT) with a compositionally graded InGaAsSb to GaAsSb base layer is presented. A device with a 0.4/spl times/6 /spl mu/m/sup 2/ emitter dimensions achieves peak f/sub T/ of 475 GHz (f/sub MAX/=265 GHz) with current density at peak f/sub T/ exceeding 12 mA//spl mu/m/sup 2/. The structure consists of a 25-nm InGaAsSb/GaAsSb graded base layer and 65-nm InP collector grown by MBE with breakdown voltage /spl sim/4 V which demonstrates the vertical scaling versus breakdown advantage over type-I DHBTs.     

Simulated analysis for InGaP/GaAs heterostructure-emitter bipolar transistor with InGaAs/GaAs superlattice-base structure

A novel InGaP/GaAs heterostructure-emitter bipolar transistor (HEBT) with InGaAs/GaAs superlattice-base structure is proposed and demonstrated by two-dimensional analysis. As compared with the traditional HEBT, the studied superlattice-base device exhibits a higher collector current, a higher current gain of 246, and a lower base–emitter (B–E) turn-on voltage of 0.966 V at a current level of 1 μA, attributed to the increased charge storage of minority carriers in the InGaAs/GaAs superlattice-base region by tunneling behavior. The low turn-on voltage can reduce the operating voltage and collector–emitter offset voltage for low power consumption in circuit applications.     

High-speed InP/lnGaAs heterojunction bipolar transistor utilizing nonalloyed contacts on n+-InP contacting layers

We have demonstrated a high-speed InP/lnGaAs heterojunction bipolar transistor with nonalloyed TiPtAu contacts on n⁺-InP emitter and collector contacting layers. The use of SiBr₄ as a silicon doping source enabled the formation of low resistance (p_c <2 × 10⁻⁶Ω. cm²), nonalloyed TiPtAu contacts to the heavily doped (n = 2 × 10¹⁹ cm⁻³) InP contacting layers. A device with a 3 × 10 Μm² emitter contact exhibited excellent dc characteristics and had ƒ_T = ƒ_max = 107 GHz. Emitter and collector resistances are compared to a device with InGaAs contacting layers.