低压5V pMOS器件在不同栅偏置应力下的热载流子注入退化机理研究

研究了低压pMOS器件热载流子注入HCI（hot-carrier injection）退化机理,分析了不同的栅压应力下漏极饱和电流（Idsat）退化出现不同退化趋势的原因。结合实测数据并以实际样品为模型进行了器件仿真,研究表明,快界面态会影响pMOS器件迁移率,导致Idsat的降低;而电子注入会降低pMOS器件阈值电压（Vth）,导致Idsat的上升。当栅压为-7.5V时,界面态的产生是导致退化的主要因素,在栅压为-2.4V的应力条件下,电子注入在热载流子退化中占主导作用。     

pMOS器件的热载流子注入和负偏压温度耦合效应

研究了在热载流子注入HCI(hot-carrier injection)和负偏温NBT(negative bias temperature)两种偏置条件下pMOS器件的可靠性.测量了pMOS器件应力前后的电流电压特性和典型的器件参数漂移,并与单独HCI和NBT应力下的特性进行了对比.在这两种应力偏置条件下,pMOS器件退化特性的测量结果显示高温NBT应力使得热载流子退化效应增强.由于栅氧化层中的固定正电荷引起正反馈的热载流子退化增强了漏端电场,使得器件特性严重退化.给出了NBT效应不断增强的HCI耦合效应的详细解释.     

pMOS器件的热载流子注入和负偏压温度耦合效应

研究了在热载流子注入HCI(hotcarrier injection)和负偏温NBT(negative bias temperature)两种偏置条件下pMOS器件的可靠性．测量了pMOS器件应力前后的电流电压特性和典型的器件参数漂移，并与单独HCI和NBT应力下的特性进行了对比．在这两种应力偏置条件下，pMOS器件退化特性的测量结果显示高温NBT应力使得热载流子退化效应增强．由于栅氧化层中的固定正电荷引起正反馈的热载流子退化增强了漏端电场，使得器件特性严重退化．给出了NBT效应不断增强的HCI耦合效应的详细解释．     

沟道热载流子导致的 PDSOI NMOSFET's击穿特性

对热载流子导致的 SIMOX衬底上的部分耗尽 SOI NMOSFET's的栅氧化层击穿进行了系统研究 .对三种典型的热载流子应力条件造成的器件退化进行实验 .根据实验结果 ,研究了沟道热载流子对于 SOI NMOSFET's前沟特性的影响 .提出了预见器件寿命的幂函数关系 ,该关系式可以进行外推 .实验结果表明 ,NMOSFET's的退化是由热空穴从漏端注入氧化层 ,且在靠近漏端被俘获造成的 ,尽管电子的俘获可以加速 NMOSFET's的击穿 .一个 Si原子附近的两个 Si— O键同时断裂 ,导致栅氧化层的破坏性击穿 .提出了沟道热载流子导致氧化层击穿的新物理机制     

HALO结构pMOSFETs在V_g=V_d/2应力模式下应力相关的热载流子退化

研究了超薄栅(2 .5 nm )短沟HAL O- p MOSFETs在Vg=Vd/ 2应力模式下不同应力电压时热载流子退化特性.随着应力电压的变化,器件的退化特性也发生了改变.在加速应力下寿命外推方法会导致过高地估计器件寿命.在高场应力下器件退化是由空穴注入或者电子与空穴复合引起的,随着应力电压的下降器件退化主要是由电子注入引起的.最后,给出了两种退化机制的临界电压并在实验中得到验证     

DEMOS在热载流子应力下的混合失效模式

研究了18V漏极延伸金属氧化物半导体场效应晶体管(DEMOS)在高栅极电压下的热载流子注入效应。实验观察到两种失效模式,分别是热空穴的注入效应和高栅压导致的阈值电压增大,发现其对器件损伤分别局限在漏极区域和沟道区域,对器件的性能影响正好相反,前者减少了漏极串联电阻,而后者增大了沟道电阻。描述了这两个失效模式的物理过程,分析并讨论了器件参数的退化曲线。讨论了如何提高DEMOS在高栅压下的抗热载流子的能力,指出了漏极上方的氧化层的质量和栅极氧化层中自由电荷数量,对于提高器件的可靠性至关重要。     

沟道热载流子导致的PDSOI NMOSFET's击穿特性

对热载流子导致的SIMOX衬底上的部分耗尽SOI NMOSFET's 的栅氧化层击穿进行了系统研究．对三种典型的热载流子应力条件造成的器件退化进行实验．根据实验结果,研究了沟道热载流子对于SOI NMOSFET's前沟特性的影响．提出了预见器件寿命的幂函数关系,该关系式可以进行外推．实验结果表明,NMOSFET's 的退化是由热空穴从漏端注入氧化层,且在靠近漏端被俘获造成的,尽管电子的俘获可以加速NMOSFET's的击穿．一个Si原子附近的两个Si—O键同时断裂,导致栅氧化层的破坏性击穿．提出了沟道热载流子导致氧化层击穿的新物理机制．     

一种用于分离pMOS器件热载流子应力下氧化层陷阱电荷和界面陷阱电荷对阈值电压退化作用的方法

在电荷泵技术的基础上,提出了一种新的方法用于分离和确定氧化层陷阱电荷和界面陷阱电荷对pMOS器件热载流子应力下的阈值电压退化的作用,并且这种方法得到了实验的验证.结果表明对于pMOS器件退化存在三种机制:电子陷阱俘获、空穴陷阱俘获和界面陷阱产生.需要注意的是界面陷阱产生仍然是pMOS器件热载流子退化的主要机制,不过氧化层陷阱电荷的作用也不可忽视.     

应力下LDD nMOSFET栅控产生电流退化特性研究

研究了LDD nMOSFET栅控产生电流在电子和空穴交替应力下的退化特性。电子应力后栅控产生电流减小,相继的空穴注人中和之前的陷落电子而使得产生电流曲线基本恢复到初始状态。进一步发现产生电流峰值在空穴应力对电子应力引发的退化的恢复程度与阈值电压和最大饱和漏电流不同。电子应力中陷落电子位于栅漏交叠区附近的沟道侧I区和LDD侧的II区中氧化层中。GIDL应力中,空穴注入进II区中和了陷落电子,使得产生电流的退化基本得到恢复,但这些空穴并未有效中和I区中的陷落电子,因此阈值电压和最大饱和漏电流退化恢复的程度较小,分别为20%和7%。     

HALO结构pMOSFETs在Vg=Vd/2应力模式下应力相关的热载流子退化

研究了超薄栅(2.5nm)短沟HALO-pMOSFETs在Vg=Vd/2应力模式下不同应力电压时热载流子退化特性.随着应力电压的变化,器件的退化特性也发生了改变.在加速应力下寿命外推方法会导致过高地估计器件寿命.在高场应力下器件退化是由空穴注入或者电子与空穴复合引起的,随着应力电压的下降器件退化主要是由电子注入引起的.最后,给出了两种退化机制的临界电压并在实验中得到验证.     

The degradation mechanisms in high voltage pLEDMOS transistor with thick gate oxide

The hot-carrier degradation behavior in a high voltage p-type lateral extended drain MOS (pLEDMOS) with thick gate oxide is studied in detail for different stress voltages. The different degradation mechanisms are demonstrated: the interface trap formation in the channel region and injection and trapping of hot electrons in the accumulation and field oxide overlapped drift regions of the pLEDMOS, depending strongly on the applied gate and drain voltage. It will be shown that the injection mechanism gives rise to rather moderate changes of the specific on-resistance (Ron) but tiny changes of the saturation drain current (Idsat) and the threshold voltage (Vth). CP experiments and detailed TCAD simulations are used to support the experimental findings. In this way, the abnormal degradation of the electrical parameters of the pLEDMOS is explained. A novel structure is proposed that the field oxide of the pLEDMOS transistor is used as its gate oxide in order to minish the hot-carrier degradation.     

关态应力下P-MOSFETs的退化

研究了沟长从0.525μm到1.025μm 9nm厚的P-MOSFETs在关态应力(Vgs＝0,Vds＜0)下的热载流子效应．讨论了开态和关态应力．结果发现由于在漏端附近存在电荷注入,关态漏电流在较高的应力后会减小．但是低场应力后关态漏电流会增加,这是由于新生界面态的作用．结果还发现开态饱和电流和阈值电压在关态应力后变化很明显,这是由于栅漏交叠处的电荷注入和应力产生的界面态的影响．Idsat的退化可以用函数栅电流（Iｇ）乘以注入的栅氧化层电荷数（Qinj）的幂函数表达．最后给出了基于Idsat退化的寿命预测模型．     

超薄栅氧化物pMOSFET器件在软击穿后的特性

研究了在软击穿后MOS晶体管特性的退化.在晶体管上加均匀的电压应力直到软击穿发生的过程中监控晶体管的参数.在软击穿后,输出特性和转移特性只有小的改变.在软击穿发生时,漏端的电流和域值电压的退化是连续变化的.但是,在软击穿时栅漏电流突然有大量的增加.对软击穿后的栅漏电流增量的分析表明,软击穿后的电流机制是FN隧穿,这是软击穿引起的氧化物的势垒高度降低造成的.     

超薄栅氧化物pMOSFET器件在软击穿后的特性

研究了在软击穿后MOS晶体管特性的退化.在晶体管上加均匀的电压应力直到软击穿发生的过程中监控晶体管的参数.在软击穿后,输出特性和转移特性只有小的改变.在软击穿发生时,漏端的电流和域值电压的退化是连续变化的.但是,在软击穿时栅漏电流突然有大量的增加.对软击穿后的栅漏电流增量的分析表明,软击穿后的电流机制是FN隧穿,这是软击穿引起的氧化物的势垒高度降低造成的.     

一种新的SPICE BSIM3v3 HCI可靠性模型的建立及参数优化

研究中提出了用于描述HCI(热载流子注入)效应的MOSFET可靠性模型及其建模方法,在原BSIM3模型源代码中针对7个主要参数,增加了其时间调制因子,优化并拟合其与HCI加压时间(Stress time)的关系式,以宽长比为10μm/0.5μm5 V的MOSFET为研究对象,在开放的SPICE和BSIM3源代码对模型库文件进行修改,实现了该可靠性模型。实验表明,该模型的测量曲线与参数提取后的I-V仿真曲线十分吻合,因而适用于预测标准工艺MOS器件在一定工作电压及时间下性能参数的变化,进而评估标准工艺器件的寿命。     

Oxide-trap-induced instability of GIDL of thermally nitrided-oxideN-MOSFET's under stress

Some holes created from band-to-band (B-B) tunneling in the deep-depletion region of the drain can be injected into the gate oxide and reduce the vertical field there. As a result, gate-induced drain leakage (GIDL) current decreases. This kind of hot-hole injection depends on the voltage difference between the drain and gate, due to nitridation-induced lowering of the barrier height for hole injection at the SiO₂-Si interface. The subsequent hot-electron injection can neutralize these trapped holes, and make the GIDL current recover, and even increase beyond its original value. Since the trapped charges also affect the lateral field, the observed change in the ratio of substrate to source currents further confirms the proposed mechanism for the GIDL degradation and recovery behavior     

A new insight into the degradation behavior of the LDD N-MOSFETduring dynamic hot-carrier stressing

A new degradation behavior of LDD N-MOSFETs during dynamic hot-carrier stress is presented. Increased degradation occurs during the gate pulse transition, and involves hot-hole injection that initially begins in the oxide-spacer region, and later propagates to the channel region. Experimental results clearly show that increased degradation of the linear drain current and transconductance is mainly due to hole-induced interface traps in the oxide-spacer region. Electron trapping at hole-induced oxide defects, on the other hand, is mainly responsible for the enhanced threshold voltage shift in the late stage, when hole injection coincides with electron injection in the channel region     

Device reliability study of AlGaN/GaN high electron mobility transistors under high gate and channel electric fields via low frequency noise spectroscopy

A set of different short term stress conditions are applied to AlGaN/GaN high electron mobility transistors and changes in the electronic behaviour of the gate stack and channel region are investigated by simultaneous gate and drain current low frequency noise measurements. Permanent degradation of gate current noise is observed during high gate reverse bias stress which is linked to defect creation in the gate edges. In the channel region a permanent degradation of drain noise is observed after a relatively high drain voltage stress in the ON-state. This is attributed to an increase in the trap density at the AlGaN/GaN interface under the gated part of the channel. It was found that self-heating alone does not cause any permanent degradation to the channel or gate stack. OFF-state stress also does not affect the gate stack or the channel.     

Gate current in OFF-state MOSFET

The source of the gate current in MOSFETs due to an applied drain voltage with the gate grounded is studied. It is found that for 100-Å or thinner oxide, the gate current is due to Fowler-Nordheim (F-N) tunneling electrons from the gate. With increasing oxide thickness, hot-hole injection becomes the dominant contribution to the gate current. This gate current can cause I_D walkout, which is a decrease in the gate-induced drain leakage current, and hole trapping, which becomes important for device degradation study. It can also be used to advantage in EPROM (erasable programmable read-only memory) erasure