谐振隧穿晶体管数字单片集成电路

阐述了谐振隧穿器件构成的与非门、单/双稳逻辑转换电路、或非门、流水线逻辑门、D触发器、静态存储器、多值逻辑和静态分频器等数字单片集成电路,它们具有高频高速、低功耗、多值逻辑、节点少、节省器件、简化电路等显著优势,将是数字集成电路后续小型化最有希望的代表。指出材料生长和芯片工艺制作等问题是其实现工业化生产的瓶颈。综述了国内外在该领域的研究现状和发展趋势,特别是美国已经有高水平的谐振隧穿晶体管数字单片电路问世,我国正在开展少量的研究工作。     

Diode-HBT-logic circuits monolithically integrable with ECl/CMLcircuits

A novel logic approach, diode-HBT logic (DHL), that is implemented with GaAlAs/GaAs HBTs and Schottky diodes to provide high-density and low-power digital circuit operation is described. This logic family was realized with the same technology used to produce emitter-coupled-logic/current-mode-logic (ECL/CML) circuits. The logic operation was demonstrated with a 19-stage ring oscillator and a frequency divider. A gate delay of 160 ps was measured with 1.1 mW of power per gate. The divider worked properly up to 6 GHz. Layouts of a DHL flip-flop and divider showed that circuit area and transistor count can be reduced by about a factor of 3, relative to ECL/CML circuits. The new logic approach allows monolithic integration of high-speed ECL/CML circuits with high-density DHL circuits with high-density DHL circuits     

A 4K CMOS gate array with automatically generated test circuits

A 2-/spl mu/m CMOS 4K-gate array using a newly devised scan bus method has been developed. This method is applied to the array by using a double-latch structure, parallel scanning, and normal-test common pin techniques. The gate array can be tested for 95-100% of all DC faults using computer-generated test circuits and test data, without placing restrictions on the logic design. Due to an access-to-output flip-flop structure and a gate-isolated three-input type basic cell, including embedded transistors, the area increase and operating speed degradation due to test circuits are considerably reduced. Furthermore, besides the flip-flop blocks, a built-in RAM macroblock is available. Degradation of operating speed is evaluated as 10%. The scan operation is done at a clock cycle of 120 ns, and the access time of the RAM macroblock is 34 ns. The gate array includes 4032 three-input gates on a 7.2/spl times/7.02-mm chip.     

基于时序优先的电路容错混合加固方案

为了有效降低容忍软错误设计的硬件和时序开销,该文提出一种时序优先的电路容错混合加固方案。该方案使用两阶段加固策略,综合运用触发器替换和复制门法。第1阶段,基于时序优先的原则,在电路时序松弛的路径上使用高可靠性时空冗余触发器来加固电路;第2阶段,在时序紧张的路径使用复制门法进行加固。和传统方案相比,该方案既有效屏蔽单粒子瞬态(SET)和单粒子翻转(SEU),又减少了面积开销。ISCAS89电路在45 nm工艺下的实验表明,平均面积开销为36.84%,电路平均软错误率降低99%以上。     

Full functionality of LSI gate arrays fabricated on 3-in-diameter,MOCVD-grown GaAs-on-silicon substrates

Fully functional, 504-gate arrays have been fabricated on an MOCVD (metalorganic chemical-vapor deposition)-grown, 3-in-diameter, GaAs-on-silicon substrate. Each ECL (emitter-coupled-logic)-compatible gate array consists of an eight-bit adder, a D flip-flop, a 214 divider (with a divide-by-four tap), and a 263-stage inverter string. These circuits represent 90% gate utilization, or approximately 6600 transistors. The wafer-level yield of fully functional gate arrays is 10.7%. This demonstrates total functionality and yield for a digital circuit with LSI-level complexity using MOCVD-grown GaAs-on-silicon material and shows that this material, even with defect densities greater than 108 cm^-2, is viable for high-density LSI circuits     

A monolithic multigigabit/second DCFL GaAs decision circuit

A GaAs integrated circuit has been designed and fabricated to regenerate digital data at gigabit per second rates. The circuit architecture is direct-coupled FET logic (DCFL), and the fabrication is by self-aligned etched gate on CVD epitaxial material. The circuit includes a moderate-gain input amplifier with threshold adjustment, a clocked D flip-flop for data sampling and storage, and an output buffer for driving low impedance transmission lines. Dynamic performance measurements include correct regeneration of pseudorandom data at 2.0 Gbit/s, the maximum allowed by available instrumentation, and 1010... data at 2.4 Gbit/s. Rise/fall times below 150 ps into 50 Ω were observed. A minimum gate delay of 17.8 ps and a maximum toggle frequency of 3.8 GHz were measured with associated ring oscillator and binary frequency divider circuits, respectively.     

Reliable CAD Analyses of CMOS Radio Frequency and Microwave Circuits Using Smoothed Gate Capacitance Models

The problems with convergence caused by both voltage- and charge-controlled models of MOSFET gate capacitances are often a limiting factor of the computer aided design tools. In the paper, an idea of the exponential smoothing of model discontinuities is proposed. The method is demonstrated on smoothing the gate capacitance discontinuity at zero drain-source voltage. An advanced integration algorithm convenient for the computer aided design of radio frequency and microwave CMOS circuits suppressing possible physically incorrect results of the traditional methods is also described. The updated model and algorithm are checked by analyzing a sophisticated CMOS flip-flop circuit.     

Basic circuits for multi-valued sequential logic

Multi-valued logic circuits were presented as an alternative to well known binary logic. It has the potential of reducing the number of active elements and interconnection lines. More data may be transferred trough a single wire using logic signals having more than two levels. However, in spite of their potential advantages, developments in multi-valued systems are not satisfactory. In particular, it is very difficult to find circuits to implement the multilevel sequential circuits. The flip-flop is the basic building block of sequential circuits and may be used to design sequential circuits such as counter/dividers and other sequential circuits. In this regard, a new multilevel flip-flop, called the AB flip-flop, was developed and published by the authors recently (Sarica and Morgul, Electron Lett 47(5):297–298, 2011). In this paper we present a new latch and restoration circuit which improves the performance of the previously designed flip-flop circuit. It is also shown that any sequential circuit may be implemented by using this flip-flop.     

Monolithically integrated enhancement/depletion-mode AIGaN/GaN HEMT D flip-flop using fluorine plasma treatment

Depletion-mode and enhancement-mode AlGaN/GaN HEMTs using fluorine plasma treatment were integrated on one wafer. Direct-coupled FET logic circuits, such as an E/D HEMT inverter, NAND gate and D flip-flop, were fabricated on an AlGaN/GaN heterostructure. The D flip-flop and NAND gate are demonstrated in a GaN system for the first time. The dual-gate AlGaN/GaN E-HEMT substitutes two single-gate E-HEMTs for simplifying the NAND gate and shrinking the area, integrating with a conventional AlGaN/GaN D-HEMT and demonstrating a NAND gate. E/D-mode D flip-flop was fabricated by integrating the inverters and the NAND gate on the AlGaN/GaN heterostructure. At a supply voltage of 2 V, the E/D inverter shows an output logic swing of 1.7 V, a logic-low noise margin of 0.49 V and a logic-high noise margin of 0.83 V. The NAND gate and D flip-flop showed correct logic function demonstrating promising potential for GaN-based digital ICs.     

Monolithically integrated enhancement/depletion-mode AlGaN/GaN HEMT D flip-flop using fluorine plasma treatment

Depletion-mode and enhancement-mode AlGaN/GaN HEMTs using fluorine plasma treatment were integrated on one wafer.Direct-coupled FET logic circuits,such as an E/D HEMT inverter,NAND gate and D flip-flop,were fabricated on an AlGaN/GaN heterostructure.The D flip-flop and NAND gate are demonstrated in a GaN system for the first time.The dual-gate AlGaN/GaN E-HEMT substitutes two single-gate E-HEMTs for simplifying the NAND gate and shrinking the area,integrating with a conventional AlGaN/GaN D-HEMT and demonstrating a NAND gate.E/D-mode D flip-flop was fabricated by integrating the inverters and the NAND gate on the AlGaN/GaN heterostructure.At a supply voltage of 2 V,the E/D inverter shows an output logic swing of 1.7 V,a logic-low noise margin of 0.49 V and a logic-high noise margin of 0.83 V.The NAND gate and D flip-flop showed correct logic function demonstrating promising potential for GaN-based digital ICs.     

F等离子体处理增强型及耗尽型AlGaN/GaN HEMT集成的D触发器

耗尽型和F等离子体处理增强型高电子迁移率晶体管（HEMT）被集成在同一圆片上。增强型/耗尽型 HEMT反向器、与非门以及D触发器等直接耦合场效应晶体管逻辑电路被制作在AlGaN/GaN异质结上。D触发器在GaN体系中首次被实现。在电源电压为2伏的条件下,增强型/耗尽型反向器显示输出逻辑摆幅为1.7伏,逻辑低噪声容限为0.49伏,逻辑高噪声容限为0.83伏。与非门和D触发器的功能正确,证实了GaN基数字电路的发展潜力。     

触发器可靠度计算的F-PTM方法

传统的概率转移矩阵（PTM）方法是一种用于估计软错误对组合电路可靠度影响的有效方法,但传统PTM方法只适用于组合逻辑电路的可靠度评估.触发器是时序逻辑电路的重要组成部分,其可靠度评估对时序电路的可靠度分析研究至关重要.为此,本文提出了基于PTM的触发器可靠度计算的F-PTM方法及电路PTM的判定定理.F-PTM方法首先建立触发器电路的特征方程,再用电路PTM的判定定理生成触发器的PTM,最后,根据输入信号的概率分布函数计算出电路的可靠度.与传统PTM方法相比较,F-PTM方法既能计算组合电路的PTM,又能计算触发器电路的PTM,其通用性强.对典型的触发器电路和74X系列电路中的触发器电路的实验结果表明,F-PTM方法合理可行.与多阶段方法和Monte Carlo方法的实验结果相比较,F-PTM方法得到的结果更精确.     

High-speed integrated circuits using i-AlGaAs/n-GaAs doped-channel hetero-MISFET's (DMT's)

High-speed ring oscillators and divide-by-two circuits have been fabricated by using i-AlGaAs/n-GaAs doped-channel hetero-MISFET's (DMT's) and saturated resistors in direct-coupled FET logic (DCFL) circuit architecture for the first time. The maximum operating frequency is 3.72 GHz for dual-clocked master-slave flip-flop frequency dividers based on eight NOR gates, which consist of 0.8-µm gate enhancement-mode DMT's with 370-mS/mm maximum transconductance. A 25-stage ring oscillator shows 24-     

高温CMOS数字集成电路直流传输特性的分析

分析了高温CMOS倒相器和门电路的直流传输特性,建立了相应的解析模型。根据分析,高温MOSFET阈值电压和载流子迁移率的降低,以及MOSFET漏端pn结泄漏电流的增加引起了CMOS倒相器和门电路直流传输特性劣化。在MOSFET漏端pn结泄漏电流的影响下,高温CMOS倒相器和门电路的输出高电平下降,低电平上升,导致了电路的功能失效。给出的理论模型和实验结果一致。     

A study of hot-carrier-induced mismatch drift: a reliability issuefor VLSI circuits

The mismatch drift of dynamic circuits, which must be corrected by precharging before activation, is a fundamental process and device reliability issue for very large scale integration (VLSI) circuits. In this paper, we report the consequences of hot-carrier effects on gate capacitance variation and its impact on the mismatch drift of MOS dynamic circuits. It is shown here that the impact of hot-carrier-induced gate capacitance variation on VLSI circuits is more critical than DC parameter (saturation current, threshold voltage, etc.) degradation. An electron beam probing was performed on a 64 Mb DRAM chip to detect the influence of gate capacitance variation in dynamic circuit blocks before and after hot-carrier stress     

Characteristics analysis and optimization design of a new ESD power clamp circuit

As CMOS technology scales down, the design of ESD protection circuits becomes more challenging. There are some disadvantages for the actual power clamp circuit. In this paper, an optimization ESD power clamp circuit is proposed. The new clamp circuit adopts the edge triggering True Single Phase Clocked Logic (TSPCL) D flip-flop to turn on and time delay, it has the advantage of dynamic transmission structure. By adding a leakage transistor of small size, the clamp circuit can turn off effectively. By changing the W/L ratio, the clamp can safely protect the gate of ESD power clamp devices from thermoelectric breakdown. The results show that the circuit can reduce the false triggering and power supply noise more effectively, it can be widely used in high-speed integrated circuits. The proposed structure has the advantages of low power and low cost, and can be used to the system-level ESD protection.     

Proposal of dual-powered superconducting logic circuits

A novel structure of high-speed Josephson logic circuits is proposed. Josephson logic gates have latching characteristics and can hold data as long as bias currents are supplied. Through effective use of these latching characteristics, logic circuits can be constructed with wide operating margins. Dual power supplies, properly phased, separately drive logic circuits divided into two groups. Logic signals are transferred from one logic group to the other or vice versa, and one group is reset into a zero voltage state when the other group is active for logic operation. For combinational circuits, the basic configuration of an astable flip-flop and a delay circuit are presented to prevent the logic circuit from `racing'. As an example of sequential circuits, a bistable flip-flop to store data is constructed without any superconducting loop.     

Electron-beam fabricated high-speed digital GaAs integrated circuits

The fabrication and performance of high-speed GaAs logic circuits incorporating submicrometer gate length FET's fabricated by electron-beam lithography are discussed. The process technology required for realizing 0.5-µm gate length devices is detailed. High-speed results including a 10-GHz logic gate, 34-ps gate delay for a ring oscillator, and a 4-GHz flip-flop are described.     

RESEARCH INTO TERNARY EDGE-TRIGGERED JKL FLIP-FLOP

The design of ternary edge-triggered JKL-type flip-flop is proposed.The computersimulation and the test in experimental circuit made up with TTL gate show this flip-flop has theexpected logic functions.     

A new family of semidynamic and dynamic flip-flops with embeddedlogic for high-performance processors

In an attempt to reduce the pipeline overhead, a new family of edge-triggered flip-flops has been developed. The flip-flops belong to a class of semidynamic and dynamic circuits that can interface to both static and dynamic circuits. The main features of the basic design are short latency, small clock load, small area, and a single-phase clock scheme. Furthermore, the flip-flop family has the capability of easily incorporating logic functions with a small delay penalty. This feature greatly reduces the pipeline overhead, since each flip-flop can be viewed as a special logic gate that serves as a synchronization element as well