All-digital TX frequency synthesizer and discrete-time receiver for Bluetooth radio in 130-nm CMOS

We present a single-chip fully compliant Bluetooth radio fabricated in a digital 130-nm CMOS process. The transceiver is architectured from the ground up to be compatible with digital deep-submicron CMOS processes and be readily integrated with a digital baseband and application processor. The conventional RF frequency synthesizer architecture, based on the voltage-controlled oscillator and the phase/frequency detector and charge-pump combination, has been replaced with a digitally controlled oscillator and a time-to-digital converter, respectively. The transmitter architecture takes advantage of the wideband frequency modulation capability of the all-digital phase-locked loop with built-in automatic compensation to ensure modulation accuracy. The receiver employs a discrete-time architecture in which the RF signal is directly sampled and processed using analog and digital signal processing techniques. The complete chip also integrates power management functions and a digital baseband processor. Application of the presented ideas has resulted in significant area and power savings while producing structures that are amenable to migration to more advanced deep-submicron processes, as they become available. The entire IC occupies 10 mm/sup 2/ and consumes 28 mA during transmit and 41 mA during receive at 1.5-V supply.     

基于BLF时钟的RFID低功耗数字基带设计

提出了一种符合ISO/IEC 18000-6C协议中关于时序规定的射频识别(RFID)无源标签芯片低功耗数字基带处理器的设计.基于采用模拟前端反向散射链路频率(BLF)时钟的方案,将BLF的二倍频设置为基带中的全局时钟,构建BLF和基带数据处理速率之间的联系;同时在设计中采用门控时钟和行波计数器代替传统计数器等低功耗策略.芯片经TSMC 0.18 μmCMOS混合信号工艺流片,实测结果表明,采用该设计的标签最远识别距离为7 m,数字基带动态功耗明显降低,且更加符合RFID协议的要求.     

A complex baseband platform for spatial-temporal mobile radio channel simulations

Joint spatial-temporal signal processing has been recognized as the key to reducing the effects of the intersymbol and cochannel interference seen in very high bit-rate mobile radio communications systems. Developing hardware simulators that can simulate mobile radio propagation scenarios in time and space domains is essential for evaluating the real-time performance of spatial-temporal signal processing schemes. This paper outlines a complex baseband platform developed for spatial-temporal mobile radio channel simulations. The platform consists of a complex baseband fading/array response simulator, a digital signal processor (DSP) board, and a general-purpose parameter estimator that uses systolic array implementation of the recursive least square (RLS) algorithm. Results of experiments conducted using the developed platform are presented to confirm the proper operation of the system.     

An open baseband processing architecture for future mobile terminal design [accepted from open call]

This article introduces an open wireless architecture (OWA) mobile terminal design, focusing on the open baseband processing platform, to support different existing and future wireless communication standards through multi-dimensional open baseband processing modules with open interface parameters and baseband management systems. The article describes a multilayer, open architecture platform to maximize system flexibility and minimize terminal power consumption, so as to provide an integrated and converged next-generation wireless and mobile communication terminal system. The OWA platform is fully compatible with the computer architecture, with interface-based rather than transmission-specific system architecture, for complete openness and simplicity.     

An 11 mm$^{2}$ , 70 mW Fully Programmable Baseband Processor for Mobile WiMAX and DVB-T/H in 0.12$ mu$ m CMOS

With the rapid evolution of wireless standards and increasing demand for multi-standard products, the need for flexible RF and baseband solutions is growing. Flexibility is required to be able to adapt to unstable standards and requirements without costly hardware re-spins, and also to enable hardware reuse between products and between multiple wireless standards in the same device, ultimately saving both development cost and silicon area. In this paper a fully programmable baseband processor suitable for standards such as DVB-T/H and mobile WiMAX is presented. The processor is based on the SIMT architecture which utilizes a unique type of vector instructions to provide processing parallelism while minimizing the control complexity of the processor. The architecture has been demonstrated in a prototype chip which was proven in a complete DVB-T/H system demonstrator. The chip occupies 11 mm² in a 0.12 mum CMOS process. It includes 1.5 Mbit of single port SRAM and 200 k logic gates. The measured power consumption for the highest DVB-T/H data rate (31.67 MBit/s) is 70 mW at 70 MHz. This outperforms both area and power figures of previously presented non-programmable DVB-T/H solutions.     

A Low-power and Low-complexity Baseband Processor for MIMO-OFDM WLAN Systems

This paper presents an energy-efficient design and the implementation results of a high speed two transmitter—two receiver multi-input multi-output orthogonal frequency division multiplexing (MIMO-OFDM) wireless LAN baseband processor. The proposed processor includes a bit-parallel processing physical layer convergence procedure (PLCP) processor which lowers system clock frequency. A cost-efficient MIMO spatial multiplexing (SM) symbol detector is also proposed in a physical medium dependent (PMD) processor. The proposed symbol detection algorithm is based on a sorted QR decomposition (SQRD) scheme followed by a maximum-likelihood (ML) test. The proposed algorithm shows enhanced performance compared to the conventional algorithms such as SQRD and ordered successive interference cancellation (OSIC) algorithms. The proposed baseband processor supports a maximum data rate of 130 Mbps at a 40 MHz operation frequency. The power consumptions of the PLCP processor are 27 mW and 93 mW for TX and RX modes, respectively, which are reduced by 70% compared with that of a common bit-serial architecture. The complexity of the symbol detector in the PMD processor is reduced by 18% compared with that of the conventional hardware architecture.     

The low power analogue and digital baseband processing parts of a novel multimode DECT/GSM/DCS1800 terminal

In order to support a multimode DECT/GSM/DCS1800 terminal architecture, with low power characteristics and integrated support for direct conversion terminal architecture, the critical parts of such a terminal were designed and implemented using three different chips. These parts include a baseband processor, a modem and suitable analogue parts. The baseband processor was designed to support multimode operation, all baseband processing required and different terminal architectures (heterodyne or direct conversion). The modem features a GMSK/GFSK modulator and a novel, low power detection algorithm supports a direct conversion terminal. The analogue circuitry includes analogue filters and Digital-to-Analog and Analog-to-Digital converters. The architecture of the direct conversion wireless terminal is presented along with details on the low power characteristics of the processor and the modem. Experimental results from the operation of the multimode terminal are presented.     

An ultra-wideband transceiver architecture for low power, low rate, wireless systems

This paper presents the system architecture, modeling, and design constraints for a baseband, integrated, CMOS, impulse ultra-wideband transceiver targeting very low power consumption on the order of 1 mW. Intended for a sensor network application, the radio supports low communication rates (/spl sim/100 kpbs) and ranging capabilities over short distances (/spl sim/10 m). Based on a "mostly digital" architecture, the analog complexity is reduced by moving the A/D convertor as close to the antenna as is reasonable. Pulses are generated from simple digital switches, overlaying the signal energy on the lower FCC UWB band (0-960 MHz). Reception is achieved using baseband gain blocks feeding a time-interleaved bank of low resolution A/D converters. A window of energy is captured in time and fed to the digital backend for processing. To save power and area, the digital backend implements only a pulse template correlation filter block overlaid with an additional spreading code. As a pulse template is used, no specific channel estimation or interference cancellation is assumed. The system performance is quantified for this case and implementation tradeoffs are explored with a strong focus on reducing power consumption. In particular, the issues of modulation choice, clock generation, gain and noise figure, ADC resolution, and digital signal processing requirements will be discussed.     

Multimedia IP architecture trends in the mobile multimedia consumer device

A dedicated media processor is used in many mobile consumer devices to accelerate video, image, graphics, and display processing. Increased demand for higher pixel resolution, higher quality image and video processing, more graphics performance necessitates dramatically increased signal processing capabilities. To provide the increased performance at acceptable cost and power requires redesign of the traditional architecture. By wisely partitioning algorithms across programmable and fixed-function blocks, the performance goals can be met while still maintaining flexibility for new feature requirements and new standards. For a better than acceptable user experience and playback time, all IPs (display, graphics, video, and imaging) have to be optimized as an “end to end” system. In this paper, an overview of the future trends of multimedia IP processor architectures is provided that describes the implications on system architecture, power, and performance.     

A Disruptive Receiver Architecture Dedicated to Software-Defined Radio

The next generation of mobile terminals is faced with the emergence of the software-defined radio (SDR) concept. The communication devices tend to provide various wireless services through a multi-functional, multi-mode and multi-standard terminal. The SDR concept aims at designing a re-configurable radio architecture accepting all cellular or noncellular standards working in the 0-5-GHz frequency range. Some technical challenges have to be solved in order to address this concept. Working in the digital domain may be a solution but the analog-to-digital conversion cannot be done at Radio Frequencies, at an acceptable resolution and at an acceptable level of power consumption. The idea proposed here was to interface an analog pre-processing circuit between the antenna and a digital signal processor to pre-condition the RF signal. It uses the principle of a fast Fourier transform to carry out basic functions with high accuracy in a low-cost technology like CMOS. This paper presents the design and the behavioral simulations of this analog discrete-time device which gives the hardware flexibility required for a cognitive radio component.     

中频数字信号处理的DSP实现

介绍了软件无线电中频数字信号的处理方法及原理,并着重介绍了采用数字信号处理器(DSP)直接对中频数字信号进行数字下变频、基带和数字上变频的处理,从而使中频数字信号的处理更加灵活和方便。     

基于ARM技术的单兵扩频网络电台设计

设计了基于ARM技术的具有较高传输速率和扩频增益的全数字化单兵网络电台。核心处理器充分考虑了多任务和实时性的要求,采用ARM处理器及嵌入式操作系统uC/OS-II,扩频基带处理器选用扩频处理增益和集成度较高的AMIS-50050芯片,话音采用高压缩比的AMBE压缩算法,语音质量高,组网遵循Ad hoc组网协议。该电台的设计满足单兵对数据、话音、图像传输和系统组网的要求,并具有高性能、高集成度、抗干扰、抗截获、体积小和功耗低的特点。     

C-RAN系统中的软件基带信号处理技术

云无线接入网(C-RAN)是融合了集中化处理、协作无线电和实时云计算的无线接入网架构,不同于传统无线通信网络架构,其基带处理单元基于统一开放的软件无线电平台。本文从灵活性、实现复杂度、运算精确度、处理时延、吞吐量、资源利用率、能耗等方面对比C-RAN系统中的软件发送接收技术与传统基带信号处理技术,并以低密度奇偶校验码(LDPC)编码载波传输系统为典型案例,展示软件技术运算精确度高、性能优良,而传统技术处理时延低的特点。     

适用于软件无线电基带芯片验证的实时原型平台

随着半导体芯片器件规模急剧增长,对芯片的功能验证以及场景验证提出了更多的挑战。而对于基带SOC芯片,挑战则更加显著。基带SOC芯片的设计验证涉及到大量算法、信号处理专用电路、软硬件协同、实时复杂场景等功能评估与验证。一般通用的芯片验证方法(基于测试用例的服务器离线验证以及FPGA原型验证)无法覆盖对基带芯片评估、验证以及测试的要求。针对基带芯片设计验证需求,本文设计并实现了一个基于软件无线电的通用实时原型平台,可满足不同频段、不同协议的基带芯片的算法评估、功能及场景测试需求。本文基于该通用实时原型平台,成功的对一款GPS/BD导航基带芯片进行了实时原型验证,解决了原有离线仿真不能满足的实时场景验证需求,使得基带芯片的验证环境更加贴近真实环境,从而极大的提高了芯片的成功率。     

KISS-16V2: a one-chip ASIC DSP solution for GSM

Outlines the requirements for the various digital signal processing functions of the pan-European digital mobile cellular telephone system in terms of computational power and RAM and ROM capacities, and describes a digital signal processor (DSP) solution which is able to integrate all of these digital baseband functions for a hand-held terminal onto one VLSI chip. The KISS-16V2 processor, a low-power CMOS 16-b DSP, is optimized for digital telecommunications, especially for Groupe Speciale Mobile (GSM). A power-down mode together with the capability of memory and multiplier standby operation make this DSP well suited for handheld devices. A design strategy based on the extensive use of cell compilers and synthesis tools reduces the design of further DSP derivations to a minimum.<>     

双模对讲机中数字编码静噪系统的实现

由于数字对讲机的频谱利用率比模拟对讲机高得多,还由于数字对讲机能够提供模拟对讲机无法达到的数据处理种类及灵活性,因此模拟对讲机的数字化改造进程已势不可挡.在这个过渡时期,需要开发数模兼容的双模对讲机,以满足市场需要并实现平缓过渡.双模对讲机的数字基带信号处理系统已经用数字信号处理器(DSP)实现,以往使用专用芯片实现的...     

Multistandard Analogue Baseband Filters for Software-Defined and Cognitive Radio Receivers

Analogue baseband filters are an important circuit for channel select and anti-aliasing in wireless and mobile communication systems. For software and cognitive radio, they must be widely tunable and reconfigurable to accommodate existing, emerging, and future wireless and mobile standards. In this paper, design considerations of tunable and programmable filters for highly integrated multistandard receivers are presented. General background of multistandard integrated receivers and design challenges of analogue baseband filters are given. Circuit techniques for baseband filter design including the widely used active-RC and Gm-C circuits are described. Filter structures and design methods for high-order baseband filters are reviewed. On-chip tuning issues and methods are discussed. Results and performances of some published design examples are summarized. Future directions are also pointed out.     

π/4-DQPSK基带处理的DSP控制与实现

介绍基于TI的TMS320VC5510 DSP(以下简称5510)和CML微电子的CMX981芯片组合实现π/4-DQPSK基带处理的方法。系统中5510除实现基带信号编解码外,利用其灵活的多通道缓冲串口(McBSP)控制CMX981多功能基带处理器的各种工作模式及快速数据收发。实验测试结果表明,5510和CMX981组合能很好地实现π/4-DQPSK基带处理,同时可大幅降低系统功耗。     

基于DCR标准调制解调器的设计及仿真

目前国内数字对讲机发展相对于欧美国家比较落后,具体的数字对讲机标准没有出台。为了研发出符合中国数字对讲机标准的调制解调芯片,本文研究日本DCR[1]（digital convenience radio）数字对讲机标准,设计调制解调器。主要包括均方根余弦滚降滤波器、Inverse sinc（Isinc）滤波器和帧同步检测器的设计及仿真。整个系统经过matlab测试,结果显示仿真误码率接近理论值,满足DCR标准。     

无源UHFRFID标签芯片基带处理器的低功耗设计

在分析ISO18000-6C标准内容的基础上,提出了一种基带处理器的结构,设计了一款符合ISO18000-6C标准的UHF RFID标签芯片的基带处理器。该基带处理器可支持协议规定的所有强制命令。设计通过降低工作电压、降低工作频率、使用门控时钟、增加功耗管理模块等一系列低功耗设计以降低处理器的功率消耗。在Xillinx的Virtex-4FPGA上验证满足协议功能要求,并在工作电压为1V,时钟为1.92MHz时,功耗仿真结果为9.9μW,很好的完成了低功耗电子标签的基带处理器设计。