一种集成电路测试流程分级动态调整方法

针对集成电路测试过程中测试时间长,影响测试效率的问题,提出了一种集成电路测试流程分级动态调整方法.通过统计样本集成电路中每种测试类型和每条测试向量的测试故障率来建立贝叶斯概率模型,根据其命中故障点的概率高低分级调整它们的加载顺序.随着测试的进行,不断收集测试数据,动态更新测试类型和测试向量的测试故障率,同步调整测试类型以及测试向量的加载顺序.实验表明,使用动态调整后的测试流程可以更早的发现故障电路,显著减少故障电路的测试时间,提高测试效率.本算法是完全基于软件的,不需要增加硬件开销,可以相容于传统的集成电路测试流程.     

功能测试矢量的重排与测试时间的压缩

对于集成电路测试而言,测试时间与成本直接相关,减少测试所需的时间意味着测试成本的降低。对于大型的测试矢量集,由于ATE存储器大小的限制,无法一次装载所有的测试矢量,需要多次的loadunload过程,从而浪费了大量的时间。通过测试矢量顺序的优化可以有效地减少重载次数而大大降低测试所需时间。应用模拟退火算法可以对测试矢量顺序进行全局的优化,得到该问题的近似最优解。     

一种基于匹配理论的FPGA三级互连网络测试方法

针对FPGA中包含三级可编程开关的互连网络测试,该文提出了一种基于匹配理论的减少配置次数并且与阵列规模无关的测试方法。该方法通过建立结构测试图,按照图的道路长进行分块并应用最小覆盖和最大匹配的原理减少配置次数。对于不同的互连网络结构,与其它方法相比,该方法的配置次数至少减少了10%,并且与阵列规模无关。     

10kV电缆故障查找及定位技术探究

在大型电网工程中,对于电缆故障查找并排除是保证电网安全的重要方式之一。目前很多地区在对10kV电缆故障检修中,环境较为恶劣,对于寻找故障点造成了很到的难度,本文中利用脉冲的方式对复杂地区进行故障查找,同时对于10kV电缆故障查找及定位技术进行详细说明,利用实际工作中的经验来完成电网工程的优化,保障安全。     

统计静态时序分析方法综述

随着纳米技术的进步，工艺参数波动给电路性能带来的不确定性愈发明显，成为影响集成电路设计的主要因素之一。为了对先进工艺下超大规模集成电路更准确地进行时序分析，现代计算机辅助设计工具通过概率分布来表征电路的时序行为，并提出了统计静态时序分析（Statistical static timing analysis,SSTA）的方法。为了提高SSTA的速度，各种各样的方法及模型被陆续提出来。本文对快速蒙特卡洛仿真法、离散数值法、查找表法、解析法这四类SSTA的加速方法展开研究并对其性能进行分析，介绍了SSTA最新的研究方向并对各种时序分析方法进行总结展望。     

一种基于绝缘摇测判断的配网接地故障查找法

在电力系统中,配网结构复杂,是电力系统中的重要部分.如果配网出现故障,通常排除或者解决会非常麻烦.因此,寻求一种快速查找故障的方法,并采取积极有效的应对策略,可以缩短故障设备抢修时间,最大限度减少停电时间.本文基于绝缘摇测判断法,探索了一种快速定位配网故障的方法,提出配网故障整体绝缘遥测法.     

总线形局域网总线故障的快速定位方法

提出一种基于二分搜索思想的总线形局域网总线故障的快速定位方法，有效地提高了总线故障的查找效率。     

基于资源路由表的P2P资源查找机制研究

对等网络使用户共享和访问网络中的大量资源，但随着网络规模的扩大，原有的资源查找机制已不能满足P2P环境下查找效率与网络负载的要求。文中结合P2P相邻节点的路径选择与Internet中的路由器选路具有的相似性．给出了一种新的资源查找方法——资源路由表查找法，并以此为基础构造了一个二层P2P资源查找模型，对其中的关键问题和方法给予了详细描述．并分析了该模型的性能。     

一种3D堆叠集成电路中间绑定测试时间优化方案

中间绑定测试能够更早地检测出3D堆叠集成电路绑定过程引入的缺陷,但导致测试时间和测试功耗剧增.考虑测试TSV、测试管脚和测试功耗等约束条件,采用整数线性规划方法在不同的堆叠布局下优化中间绑定测试时间.与仅考虑绑定后测试不同,考虑中间绑定测试时,菱形结构和倒金字塔结构比金字塔结构测试时间分别减少4.39%和40.72%,测试TSV增加11.84%和52.24%,测试管脚减少10.87%和7.25%.在测试功耗约束下,金字塔结构的测试时间增加10.07%,而菱形结构和倒金字塔结构测试时间只增加4.34%和2.65%.实验结果表明,菱形结构和倒金字塔结构比金字塔结构更具优势.     

产品ESD快速低成本测试方法

静电防护(ESD)测试是半导体集成电路可靠性的重要项目,存在ESD问题会对产品的可靠性造成致命的影响.而由于目前产品的ESD测试,必须经过成品封装后才能进行,这样就无法快速进行产品的ESD认证和评估.介绍了ESD测试中如何利用陶瓷双列直插式封装(ceramic DIP或sB)来快速实现产品的ESD测试.对于一些多管脚芯片产品,举例说明了一种共地连接、分组测试的方法,克服了该封装有管脚数量限制的局限性.该方法简单、低成本、并且可以快速完成.可以极大地减少相对于传统ESD评估或认证的时间和成本,随之也大大缩短了产品的研发认证周期.     

Distributed Test Pattern Generation for Stuck-At Faults in Sequential Circuits

Automatic test pattern generation (ATPG) remains one of themost complex CAD tasks. Therefore, numerous methods were proposed tospeed up ATPG by using parallelism. In this paper, we focus onparallelizing ATPG for stuck-at faults in sequential circuits bycombining fault and search space parallelism. Fault parallelism isapplied to so-called easy-to-detect faults. The main task of thisapproach is to find a best-suited partitioning of the fault list,based on dependencies between faults. For hard-to-detect faultsleft by fault parallelism, search space partitioning is applied,integrating depth-first and breadth-first search. Since a smalltest set size is mandatory for a cheap test and fault parallelismincreases the number of test patterns, test set compaction is donein a post-processing phase. Results show that our approach is notonly capable of achieving potentially superlinear speedups, but alsoimproves test set quality. The parallel environment we use consistsof a network of 100 workstations connected via ethernet.     

Sequential circuit test generation using dynamic justification equivalence

Automatic test pattern generation (ATPG) for sequential circuits involves making decisions in the search decision spaces bounded by a sequential circuit. The flip-flops in the sequential circuit determine the circuit state search decision space. The inputs of the circuit define the combinational search decision space. Much work on sequential circuit ATPG acceleration focused on how to make ATPG search decisions. We propose a new technique to improve sequential circuit ATPG efficiency by focusing on not repeating previous searches. This new method is orthogonal to existing deterministic sequential circuit ATPG algorithms.A common search operation in sequential circuit ATPG is justification, which is to find an input assignment to justify a desired output assignment of a component. We have observed that implications in a circuit resulting from prior justification decisions form an unique justification decomposition. Since the connectivity of a circuit does not change during ATPG, test generation for different target faults may share identical justification decision sequences represented by identical decision spaces. Because justification decomposition represents the collective effects of prior justification decisions, it is used to identify previously-explored justification decisions. Preliminary results on the ISCAS 1989 circuits show that our test generator (SEST) using justification decompositions, on average, runs 2.4 and 4.5 times faster than Gentest and Hitec, respectively. We describe the details of justification equivalence and its application in ATPG accompanied with step-by-step examples.     

THE QUATERNARY INTERFACE TECHNIQUE IN ECL INTEGRATED CIRCUITS

The theory of differential current switches which applies to the design of multivaluedECL circuits is introduced.In this theory,the switching state of differential transistor pairand signal in ECL circuits are described by switching variables and quaternary signal variables,respectively.he connection operations between the two kinds of variables are introduced todescribe the action process between switching element and signal in the circuits.Based on thistheory,two kinds of interface circuits-2-4 encoder and 4-2 decoder are designed.The computersimulation for the designed circuits by using SPICE program confirms that both circuits havecorrect logic functions,desired DO transfer characteristics and transient characteristics.Theseinterface circuits are compatible with binary circuits in the integrated process,the power supplyequipment,the logic stage and the transient characteristic.Therefore,they can be used as input-output interface of the existing binary ECL integrated circuits so as to decrease the number ofpins of a chip and the connections between chips.     

Deterministic Built-in Pattern Generation for Sequential Circuits

We present a new pattern generation approach for deterministic built-in self testing (BIST) of sequential circuits. Our approach is based on precomputed test sequences, and is especially suited to sequential circuits that contain a large number of flip-flops but relatively few controllable primary inputs. Such circuits, often encountered as embedded cores and as filters for digital signal processing, are difficult to test and require long test sequences. We show that statistical encoding of precomputed test sequences can be combined with low-cost pattern decoding to provide deterministic BIST with practical levels of overhead. Optimal Huffman codes and near-optimal Comma codes are especially useful for test set encoding. This approach exploits recent advances in automatic test pattern generation for sequential circuits and, unlike other BIST schemes, does not require access to a gate-level model of the circuit under test. It can be easily automated and integrated with design automation tools. Experimental results for the ISCAS 89 benchmark circuits show that the proposed method provides higher fault coverage than pseudorandom testing with shorter test application time and low to moderate hardware overhead.     

ECL集成电路的四值接口技术

本文介绍了适用于多值ECL电路设计的差动电流开关理论。在该理论中,分别用开关变量和四值信号变量来描写ECL电路中差动晶体管对的开关状态和信号,并引入此两类变量之间的联结运算,以描写电路内部开关元件与信号的相互作用过程。基于该理论,本文对两种接口电路2-4编码器和4-2译码器进行了设计。应用SPICE程序对设计电路的计算机模拟表明,两种电路均具有正确的逻辑功能、理想的DC转移特性和瞬态特性。由于该接口电路具有与二值电路兼容的集成工艺、电源设备、逻辑级差和瞬态特性,因此它可用作现有二值ECL集成电路的输入输出接口,从而达到减少芯片的引脚数和片间连接的目的。     

Feature Vector Selection Method Using Mahalanobis Distance for Diagnostics of Analog Circuits Based on LS-SVM

Multi-fault diagnosis for analog circuits based on support vector machine (SVM) usually used a single feature vector to train all binary SVM classifier. In fact, each binary SVM classifier has different classification accuracy for different feature vectors. However, no one has discussed the optimal or near-optimal feature vector selection problem. Based on Mahalanobis distance, a near-optimal feature vector selection method has been proposed for diagnostics of analog circuits using the least squares SVM (LS-SVM). The selection problems of wavelet types, wavelet decomposition level, and normalization methods have been also discussed. Two filters with parametric faults and a nonlinear half-wave rectifier with hard and parametric faults were used as circuits under test (CUTs). The simulation results showed the following: (1) the accuracies using the feature vector with the maximum MD were better than the average accuracies using all the feature vectors, and were better than most accuracies using a single feature vector. But the computation time using the MD method was an order of magnitude larger than that using a single feature vector; (2) Most the diagnostic accuracies using the maximum MD method were near to the optimal accuracies using the exhaustive method while the computation time was reduced about 20–50?% in comparision to the exhaustive method; (3) the Haar wavelet was the best choice among Daubechie’s wavelet family for all CUTs’ diagnosis; (4) only non-normalization, all-normalization, and part-normalization methods are necessary to be considered for feature vector normalization. The proposed method can obtain a near-optimal diagnostic accuracy in a reasonable time, which is beneficial for analog IC or circuits testing and diagnosis.     

Search strategy switching: A cost model and an analysis of backtracking

Test generation algorithms contain search strategies which are used to control decision making when the algorithm encounters a choice of signal value, or what action to perform next. Our study of traditional search strategies used in automatic test pattern generation has led us to the observation that no single strategy is superior for all faults in a circuit and all circuits. Further experimentation led to the conclusion that a combination of search strategies provides better fault coverage and/or faster ATPG for a given backtrack limit. Instead of using just one strategy up to the backtrack limit, a primary strategy is used for the first half of the backtrack limit, then a secondary strategy is used for the second half of the backtrack limit. This article presents a qualitative ATPG cost model based on the number of test generation events, uses this model to explain why search strategy switching is faster, and shows experimental evidence to verify both the cost model and search strategy switching theory. The experiments were performed with the ISCAS circuits and our implementation of the FAN algorithm.     

机载传感器无引导搜索策略研究

针对机载传感器搜索任务,将无引导搜索问题分为搜索区域目标出现概率未知和已知两种情况进行了讨论。在搜索区域仅有一个目标和忽略传感器搜索视场切换的前提假设下,在搜索时间最短的要求下,提出了一种最优搜索策略,即任一视场的搜索次数与该视场中目标出现概率的平方根成正比。并通过仿真实例表现了该搜索策略:未知目标出现概率的情况下是一种顺序搜索,而已知目标出现概率的情况下是优先、多次搜索目标出现概率较大视场的同时,还无遗漏的兼顾搜索其他视场。该策略使传感器尽快满足任务要求,缩减工作时间。     

大面阵多引脚IC组件力学加固及底部除胶工艺

高可靠性产品中电子组件的力学加固对产品的整机可靠性有着重要影响,其中大面阵多引脚集成电路的力学加固是重点.分析了影响器件力学性能的主要因素,阐述了大面阵多引脚电子组件的力学加固工艺过程以及产品返修过程中器件的底部除胶工艺.经实践证明,按照该种工艺实施的产品经受住了各种环境应力试验.     

一种针对多级串联模拟电路的可测性设计技术

随着集成电路的发展,测试难度的增加,可测试性设计也越来越重要。针对串联结构的模拟电路提出一种可测性设计结构,该结构大大提高了电路内系统模块的可测试性,减少了需要额外引出的I/O数,同时不随内部模块数的增加而增加,并且可以与数字电路的边界扫描技术相兼容,通过在Cadence下仿真,证明了该结构简单有效。