几种基于MEMS的纳米梁制作方法研究

特征尺度在纳米量级的梁结构是多种纳机电器件的基本结构.提出了几种基于MEMS技术的纳米梁制作方法,通过利用MEMS技术中材料与工艺的特性实现单晶硅纳米梁的制作.在普通(111)硅片上,利用各向异性湿法腐蚀对(111)面腐蚀速率极低的特性,通过干法与湿法腐蚀相结合制成厚度在100 nm以下的纳米梁.该方法不使用SOI硅片,有效控制了成本.在(100)SOI硅片上,通过氧化减薄的方法得到厚度在100 nm以下的多种纳米梁,由于热氧化的精度高,一致性好,该方法重复性与一致性均较好.在(110)SOI硅片上,利用硅的各向异性腐蚀特性以及(110)硅片的晶向特点,制作宽度在100 nm以下的纳米梁,梁的两个侧面是(111)面.     

Fabrication methods based on wet etching process for the realization of silicon MEMS structures with new shapes

In this paper, fabrication methods are developed in order to realize the silicon microelectromechanical systems components with new shapes in {100} Si wafers. Fabrication process utilizes wet etching with a single step of photolithography. The silicon etching is carried out in complementary metal oxide semiconductor process compatible pure and surfactant Triton-X-100 [C₁₄H₂₂O(C₂H₄O] _n , n = 9–10) added tetramethylammonium hydroxide (TMAH) solutions. The fabricated structures are divided in two categories: fixed and freestanding. The fixed structures are realized in single oxidized silicon wafers, while freestanding are formed in silicon nitride-based silicon on insulator (SOI) wafers. The SOI wafers are prepared by bonding the oxidized and the nitride deposited wafers, followed by thinning and chemical mechanical polishing processes. The etching results such as {100} and {110}Si etch rates, undercutting at rounded concave and sharp convex corners and etched surface morphologies are measured in both pure and Triton added TMAH solutions. Different concentrations of TMAH are used to optimize the etching conditions for desired etched profiles.     

Direct bonding with on-wafer metal interconnections

A low temperature direct bonding process with encapsulated metal interconnections was proposed. The process can be realized between silicon wafers or silicon and glass wafers. To establish well-insulated electric connection, sputtered aluminum film was patterned between a bottom thermal SiO₂ and a top PE-SiO₂; the consequential uneven wafer surface was planarized through a chemical mechanical polishing (CMP) step. Benefit from this smooth surface finish, direct bonding is achieved at room temperature, and a general yielding rate of more than 95% is obtained. Test results confirmed the reliability of the bonding. The main advantages of this new technology are its electric connectivity, low thermal stress and hermeticity. This process can be utilized for the packaging of micro electro mechanical system (MEMS) devices or the production of SOI wafers with pre-fabricated electrodes and wires.     

Strain analysis of silicon-on-insulator films produced by zonemelting recrystallization

Silicon-on-Insulator (SOI) wafers produced by the Zone-Melting-Recrystallization (ZMR) method were evaluated to determine the level of built-in strain. Micromechanical strain measurement structures were produced by surface micromachining the thin film silicon epitaxial layer. A variety of test structures and a new tensile strain measurement device were used to determine the level of strain in the material. Results indicated that the maximum strain in the ZMR material is less than 2×10^-4 and that there is a significant orientation dependence     

Fusion bonding of rough surfaces with polishing technique for silicon micromachining

 Surface roughness is one of the crucial factors in silicon fusion bonding. Due to the enhanced surface roughness, it is almost impossible to bond wafers after KOH etching. This also applies when wafers are heavily doped, have a thick LPCVD silicon nitride layer on top or have a LPCVD polysilicon layer of poor quality. It has been demonstrated that these wafers bond spontaneously after a very brief chemical mechanical polishing step. An adhesion parameter, that comprises of both the mechanical and chemical properties of the surface, is introduced when discussing the influence of surface roughness on the bondability. Fusion bonding, combined with a polishing technique, will broaden the applications of bonding techniques in silicon micromachining. Received 30 October 1996/Accepted: 14 November 1996     

A 2-D microcantilever array for multiplexed biomolecular analysis

An accurate, rapid, and quantitative method for analyzing variety of biomolecules, such as DNA and proteins, is necessary in many biomedical applications and could help address several scientific issues in molecular biology. Recent experiments have shown that when specific biological reactions occur on one surface of a microcantilever beam, the resulting changes in surface stress deflect the cantilever beam. To exploit this phenomenon for high-throughput label-free biomolecular analysis, we have developed a chip containing a two-dimensional (2-D) array of silicon nitride cantilevers with a thin gold coating on one surface. Integration of microfluid cells on the chip allows for individual functionalization of each cantilever of the array, which is designed to respond specifically to a target analyte. An optical system to readout deflections of multiple cantilevers was also developed. The cantilevers exhibited thermomechanical sensitivity with a standard deviation of seven percent, and were found to fall into two categories-those whose deflections tracked each other in response to external stimuli, and those whose did not due to drift. The best performance of two "tracking" cantilevers showed a maximum difference of 4 nm in their deflections. Although "nontracking" cantilevers exhibited large differences in their drift behavior, an upper bound of their time-dependent drift was determined, which could allow for rapid bioassays. Using the differential deflection signal between tracking cantilevers, immobilization of 25mer thiolated single-stranded DNA (ssDNA) on gold surfaces produced repeatable deflections of 80 nm or so on 0.5-/spl mu/m-thick and 200-/spl mu/m-long cantilevers.     

Bonded thick film SOI with pre-etched cavities

We have studied direct bonding and thinning of pre-etched silicon wafers. Silicon-on-insulator (SOI) substrates with pre-etched cavities provide freedom to MEMS design and enable manufacturing of advanced sensor structures (sensor structures that would be difficult or impossible with conventional substrates). Cavities with different shapes and sizes were etched on to the handle wafers. The etched handle wafers were bonded to unpatterned cap wafers in air or in vacuum. The bonding quality was evaluated with scanning acoustic microscopy and with HF-etching test. After bonding, the cap wafers were thinned down with grinding and polishing. The thickness variation of silicon diaphragm over the cavities was evaluated with cross-sectional SEM. The deflection of the Si film was measured with surface profilometry. To decrease the deflection and the thickness variation of the film, different support structures were placed inside the cavities.The bonding experiments carried out with patterned wafers showed that vacuum bonding results in slightly higher bonding energy than bonding in air. With large cavity fraction (80% of total wafer area), the air bonded samples had large void on the bonded interface. With smaller cavity fractions or with vacuum bonded samples, no such voids were found. Thinning studies showed that the thickness variation of the silicon diaphragm increases with increasing cavity dimensions and with decreasing SOI layer thickness. Thickness variation can be reduced with support structures under the Si membrane.     

Frontside micromachining using purous-silicon sacrificial-layer technologies

Several electro- and photo-electrochemical processes are pointed out which allow silicon microstructures to be formed within ion-implanted silicon wafers. It is shown how different lateral and vertical doping profiles can be used to anodize selectively parts of the ion-implanted silicon wafers, creating isolated regions of porous silicon. After removal of the porous silicon in diluted KOH, micromachined structures emerge at the front surface of the silicon wafers which entirely consist of low-stress bulk crystalline silicon.     

Single mask fabrication process for movable MEMS devices

The current work reports on the realization of movable micromachining devices using self-aligned single-mask fabrication process. Only dry etching process utilizing inductively coupled plasma reactive ion etching was used to release 3D micro structures from single crystal silicon substrate. No wet etching process is required to release the structures as is the case with silicon on insulator (SOI) wafers. Also the developed process does not require an SOI substrate and accordingly dispensing with the application of a wet etching step, thus yielding uniform structures without stiction. The optimized process was applied to realize thermally actuated microgrippers. The article presents the development of the fabrication process and demonstrates the operation of the fabricated device. The optimized process provides an avenue for low cost fabrication of movable micromachining devices without the use of complicated wet etching steps typically associated with SOI substrates.     

Quality factors in micron- and submicron-thick cantilevers

Micromechanical cantilevers are commonly used for detection of small forces in microelectromechanical sensors (e.g., accelerometers) and in scientific instruments (e.g., atomic force microscopes). A fundamental limit to the detection of small forces is imposed by thermomechanical noise, the mechanical analog of Johnson noise, which is governed by dissipation of mechanical energy. This paper reports on measurements of the mechanical quality factor Q for arrays of silicon-nitride, polysilicon, and single-crystal silicon cantilevers. By studying the dependence of Q on cantilever material, geometry, and surface treatments, significant insight into dissipation mechanisms has been obtained. For submicron-thick cantilevers, Q is found to decrease with decreasing cantilever thickness, indicating surface loss mechanisms. For single-crystal silicon cantilevers, significant increase in room temperature Q is obtained after 700°C heat treatment in either N₂ Or forming gas. At low temperatures, silicon cantilevers exhibit a minimum in Q at approximately 135 K, possibly due to a surface-related relaxation process. Thermoelastic dissipation is not a factor for submicron-thick cantilevers, but is shown to be significant for silicon-nitride cantilevers as thin as 2.3 μm     

Arrays of monocrystalline silicon micromirrors fabricated using CMOS compatible transfer bonding

In this paper, we present CMOS compatible fabrication of monocrystalline silicon micromirror arrays using membrane transfer bonding. To fabricate the micromirrors, a thin monocrystalline silicon device layer is transferred from a standard silicon-on-insulator (SOI) wafer to a target wafer (e.g., a CMOS wafer) using low-temperature adhesive wafer bonding. In this way, very flat, uniform and low-stress micromirror membranes made of monocrystalline silicon can be directly fabricated on top of CMOS circuits. The mirror fabrication does not contain any bond alignment between the wafers, thus, the mirror dimensions and alignment accuracies are only limited by the photolithographic steps. Micromirror arrays with 4/spl times/4 pixels and a pitch size of 16 /spl mu/m/spl times/16 /spl mu/m have been fabricated. The monocrystalline silicon micromirrors are 0.34 /spl mu/m thick and have feature sizes as small as 0.6 /spl mu/m. The distance between the addressing electrodes and the mirror membranes is 0.8 /spl mu/m. Torsional micromirror arrays are used as spatial light modulators, and have potential applications in projection display systems, pattern generators for maskless lithography systems, optical spectroscopy, and optical communication systems. In principle, the membrane transfer bonding technique can be applied for integration of CMOS circuits with any type of transducer that consists of membranes and that benefits from the use of high temperature annealed or monocrystalline materials. These types of devices include thermal infrared detectors, RF-MEMS devices, tuneable vertical cavity surface emitting lasers (VCSEL) and other optical transducers.     

Realisation and characterisation of mass-based diamond micro-transducers working in dynamic mode

We report on novel MEMS micro-transducers made of diamond and targeted for bio-sensing applications. To overcome the non-straightforward micromachining of diamond, we developed a bottom up process for the fabrication of synthetic diamond micro-structures involving the patterned growth of diamond using the CVD (chemical vapour deposition) technique, inside micro-machined silicon moulds. Here typical resonant MEMS structures including cantilevers fabricated using this method were characterized by measuring their first mode resonance (frequency and Q-factor) by Doppler laser interferometry. The experimental data matched the simulation data. Data from bare diamond cantilevers and from diamond cantilevers with actuation gold track on the surface were compared and showed a significant decrease in the resonant frequency in the presence of gold tracks. Nevertheless, comparisons with equivalent silicon structures demonstrated the superior performances of diamond cantilevers: the resonance frequencies were twice higher and the Q-factors 2.5 times higher for the diamond transducers. Diamond cantilevers sensitivity were measured using PMMA deposition and values as high as 227.4 Hz ng⁻¹ were found. It was shown that diamond mass sensitivity values are typically two times higher than identical silicon devices. Finally, the limit of detection (LOD) of diamond cantilevers was found experimentally to be as low as 0.86 pg using our set up. This is suitable for many bio-sensing applications.     

覆盖Si3N4层和栅氧化物氮化对晶体管的影响

研究了在各种各样的晶体管中高于最低限度的坡面外层上覆盖硅氮化物和栅氧化物被氮化的影响,同时制作出具有高、低压晶体管的硅晶片.当干燥氧化物和降低化学蒸汽的压力使之凝固的2个步骤( LPCVD )被用于厚栅氧化物时,薄栅氧化物被氮氧化改善.薄栅氧化物的厚度是4.5nm,厚栅氧化物的厚度为29nm.低压nMOS和pMOS不显示出任何驼峰,高压pMOS也一样.高压nMOS高于最低限度的驼峰取决于工艺条件.它表明没有覆盖硅氮化层的严重驼峰取决于经过LPCVD的内部涂层氧化沉淀后化学处理期间的湿度扩散.这说明,采用氮氧化物阻止水汽扩散防止驼峰的方法是有效的.     

多孔硅残余应力的研究

利用电化学腐蚀的方法在p型单晶硅(100)衬底上制备了多孔硅薄膜。利用微拉曼光谱法分别测量了处于湿化—干燥—再湿化3个阶段的多孔硅薄膜的拉曼频移,对多孔硅内应变引起的频移改变量和纳米硅晶粒因声子限制效应引起的频移改变量进行分离,找到多孔硅薄膜残余应力与拉曼频移之间的关系式。利用这一关系式,对不同孔隙率的多孔硅薄膜的残余应力进行了计算,获得了和声子模型拟合方法相一致的结果。研究中发现,多孔硅表面残余应力随孔隙率的增加而线性增大,其原因为随着孔隙率的增加,多孔硅晶格常数增大,且干燥过程中残液的蒸发产生的毛细应力使多孔硅薄膜与基体硅间晶格错配程度增大造成的。     

6-MHz 2-N/m piezoresistive atomic-force microscope cantilevers withINCISIVE tips

Piezoresistive atomic force-microscope (AFM) cantilevers with lengths of 10 μm, displacement sensitivities of (ΔR/R)/A 1.1×10^-5, displacement resolutions of 2×10^-3 A/√Hz, mechanical response times of less than 90 ns, and stiffnesses of 2 N/m have been fabricated from a silicon-on-insulator (SOI) wafer using a novel frontside-only release process. To reduce mass, the cantilevers utilize novel inplane crystallographically defined silicon variable aspect-ratio (INCISIVE) tips with radius of curvature of 40 A. The cantilevers have been used in an experimental AFM data-storage system to read back data with an areal density of 10 Gb/cm ². Four-legged cantilevers with both imaging and thermomechanical surface modification capabilities have been used to write 2-Gb/cm² data at 50 kb/s on a spinning polycarbonate sample and to subsequently read the data. AFM imaging has been successfully demonstrated with the cantilevers. Some cantilever designs have sufficient displacement resolution to detect their own mechanical-thermal noise in air. The INCISIVE tips also have applications to other types of sensors     

Fabrication of thermal microbridge actuators and characterization of their electrical and mechanical responses

This study presents thermal silicon microbridge actuators which have been made by a novel fabrication process utilizing dry processes for all critical steps. The fabrication process results in microbridges which are fully oxide covered, with excellent surface quality and dimensional control. The microbridges are made in the device layer of a silicon-on-insulator (SOI) wafer which ensures uniform doping profile and accurate thickness control. The electrical and mechanical responses of the bridges were measured upon rapid heating up to near the melting point of silicon. Up to 12 μm mechanical deflection due to thermal expansion was detected by white light interferometry (WLI) which allowed accurate measurement. Mechanical deflection has previously not been measured for silicon microlamps. Thermal conduction in the air gap between the actuator and the neighbouring solid silicon parts was analysed and shown to be more important than convection or radiation, even at very high operation temperatures.     

多孔硅的表面状态和吸附性能的研究

用原子簇模型模拟纳米多孔硅表面及其吸附状态,并用量子化学方法计算了多孔硅表面与氢原子、氢分子、氧分子、硝酸根、二氧化硫的吸附,计算主要采用HFR方法,基组为6-31G(d)。结果表明除氢分子外,表面硅原子与吸附物质之间均产生明显的相互成键作用,在多孔硅表面生成更多活性的物质,改变了多孔硅表面状态,产生新的性能,从而可广泛用于含能材料的领域。     

Microfabricated small metal cantilevers with silicon tip for atomicforce microscopy

Atomic force microscopy with small cantilevers is faster due to higher resonant frequencies and has a lower noise level. We report a new process to microfabricate small metal cantilevers with integrated silicon tips. This process is used to fabricate gold cantilevers that are 13-40-μm long, 5-10-μm wide, and 100-160-nm thick. The tip is first formed at the free end of a sacrificial oxide cantilever. The cantilever layer of the desired metal is then deposited on the nontip side of the sacrificial oxide cantilever. The oxide layer is removed to form the cantilevers with tips on them in a batch process. The highly stressed cantilevers are rapid thermal annealed for 60 s at 300°C to relieve the stress. The gold cantilevers have been characterized through their thermal spectra and used to image in tapping mode. The process can be used, not only for gold, but also for any metal or compound that can withstand removal of sacrificial oxide cantilevers     

Towards a versatile DRIE: silicon pit structures combined with electrochemical etch stop

A novel approach for fabricating low-pitch arrays of silicon membranes on standard CMOS wafers by combining deep-reactive ion etching (DRIE) and electrochemical etching (ECE) techniques is presented. These techniques have been used to fabricate membrane-based sensors and sensor arrays featuring different membrane sizes on a single wafer with a well defined etch stop. The described procedure is particularly useful in cases when the usage of SOI wafers is not an option. The combination of a grid-like mask pattern featuring uniform-size etch openings for the DRIE process with a reliable ECE technique allowed to fabricate silicon membranes with sizes ranging from 0.01 mm/sup 2/ to 2.2 mm/sup 2/. The development of this new method has been motivated by the need to design a compact n-well-based calorimetric sensor array, where the use of a standard ECE technique would have significantly increased the overall size of the device.     

“Plug-up”–a new concept for fabricating SOI MEMS devices

This paper reports a novel process sequence for fabricating micromechanical devices on silicon-on-insulator (SOI) wafers. Among the merits of the described process are its improved immunity to stiction and elimination of conductor metal endurance problems during sacrificial etching in hydrofluoric acid. With this novel process one can controllably embed vacuum cavities within SOI substrates. Further processing of such cavity wafers enables realization of a wide variety of micromechanical devices based on single crystalline silicon or even integrated read-out circuitry.K. Järvi and T. Häkkinen are gratefully acknowledged for the device fabrication. The Finnish National Technology Agency, Okmetic, VTI Technologies, and Micro Analog Systems participated in funding this work. The ultrasonic devices were fabricated in collaboration with Autotank, Oras, Suunto, Vaisala, and Enermet.