VLSI低功耗设计方法的研究

针对近年来VLSI 功耗问题越来越被关注,尤其是在电池供电的便携式设备中CMOS 电路的功耗问题尤为重 要。本文对VLSI 的低功耗设计方法进行了研究,首先对VLSI 作了简介,其次分析了VLSI 的功耗来源,最后就如何实现VLSI 开关功耗的低功耗设计,着重讨论了几项技术。本文对电子行业从业人员有一定的积极意义。     

基于数据与控制分割方法的异步串行接口设计

根据VLSI系统设计的流程，很自然的将VLSI模块分成数据路径和控制通道两个部分，在它们之间进行数据处理的联系和格式信息的反馈，控制部分一般用状态机实现，本文根据异步串行通讯的RS232标准，利用数据与控制分割思想，实现了异步串行通讯接口的发送和接收模块SCI的VLSI设计。     

一种低功耗异步乘法器的研究与实现

同步电路由全局时钟信号周期性地驱动计算,而异步电路只在需要的时候才进行运算,因此异步电路具有天然的低功耗优势。当前的解同步异步电路设计方法仅根据同步电路的物理拓扑结构进行异步设计,而没有考虑同步电路的本身功能行为及所处理数据的特点。本文首先分析了物理拓扑结构、电路功能行为及处理数据对低功耗设计的影响,然后设计实现了一款低功耗异步乘法器。实验表明,实现的乘法器相对于传统解同步异步乘法器具有更低的功耗与更高的性能。     

中小尺寸液晶屏图形显示控制芯片的低功耗设计

在VLSI设计中，低功耗的要求已经变得越来越重要。低功耗设计可以在不同的设计层次考虑．采用低功耗技术的层次越高，对功耗的改善越显著。本文针对一款中小尺寸液晶屏图形显示控制芯片的设计，提出了一种有效的低功耗设计方案。通过功耗分析比较表明．该设计方案极大的改善了这款芯片的功耗特性。     

AFMC:一种新的异步电路设计自动化流程

随着VLSI面临的功耗及时钟问题越来越突出,异步电路及其设计方法得到了广泛关注.基于宏单元的异步电路设计流程能够采用现有的同步EDA工具和设计流程将同步电路转变成相应的异步电路.在基于宏单元的异步电路设计流程的基础上提出了一种新的异步电路设计自动化流程,并与解同步异步电路设计自动化流程进行了比较.在UMC 0.18μm工艺下采用提出的自动化流程设计实现了一款DLX异步微处理器,实验结果表明该流程能够快速地进行异步电路设计,并且在异步电路的数据通路性能优化方面具有一定的优势.相对于解同步DLX微处理器,采用基于宏单元的异步设计自动化流程实现的异步DLX微处理器能够获得6%左右的性能提高.     

异步处理器设计中的关键技术研究

异步处理器解决了传统的同步处理器时钟偏移的问题,具有低功耗和高并行性等优点。本文着重分析了设计异步处理器的关键技术及实现方法,分析比较了当前异步处理器的实现方式,指出了异步处理器的研究方向和重点。并展望了异步处理器技术在媒体处理领域中的应用。异步处理器虽然还没有得到实际的广泛应用,但具有很高的研究价值。     

“腾越-Ⅱ”嵌入式异步微处理器的设计与实现

嵌入式系统对处理器功耗开销有严格的限制,异步电路技术可以作为设计低功耗处理器的有效方法之一。针对嵌入式多媒体应用,本文设计实现了一款低功耗异步微处理器——腾越-Ⅱ。处理器中包含一个异步TTA微处理器内核、一个同步TTA微处理器内核、两个存储控制器和多个外部通信接口。异步内核通过基于宏单元的异步电路设计方法实现,其它部分通过基于标准单元的半定制设计流程实现。处理器芯片采用UMC0.18μmCMOS工艺实现,基片面积为4.89×4.89mm2,工作电压为1.8V。经测试,处理器工作主频达到200MHz,且异步内核的功耗开销低于同步内核的50%。     

无线传感器网络SOC芯片的低功耗设计

该文提出了一种无线传感器网络节点的SOC解决方案,介绍SOC设计的要点及VLSI低功耗设计的特点,在此基础上,着重分析了无线传感网络节点的体系结构,并从系统级,结构级,RTL级及物理设计几个方面阐述了无线传感网络节点芯片的低功耗设计。整个设计在FPGA上通过验证,并且完成了芯片的物理设计。     

VLSI行为层的多电压低功耗调度研究

分析了VLSI的功耗模型,综述了多电压低功耗优化调度技术,通过对已有优化调度技术的评估,表明利用多电压调度技术能够有效地降低电路功耗,同时指出行为层的多电压综合设计会带来的一些负面影响,如物理布局等问题,针对该问题提出了一种行为层综合方案--调度分区一法,最后提出了VLSI行为层综合设计研究的新方向.     

VLSI芯片的可测试性、可调试性、可制造性和可维护性设计

CMOS器件进入深亚微米阶段，VLSI集成电路（IC）继续向高集成度，高速度，低功耗发展，使得IC在制造、设计、封装，测试上都面临新的挑战，测试已从IC设计流程的后端移至前端，VLSI芯片可测试性设计已成为IC设计中必不可少的一部分，本文介绍近几年来VLSI芯片可测试性设计的趋势，提出广义可测试性设计（TDMS技术）概念，即可测试试性，可调试性，可制造性和可维护性设计，并对可调试性设计方法学和广义可测试性设计的系统化方法作了简单介绍。     

异步电路的计算机辅助设计软件

异步电路由于没有时钟频率的限制,所以较同步电路有很多优点,其研究也越来越广泛,是未来解决计算机CPU设计的一种重要方案。异步电路的计算机辅助设计软件代表了异步电路当前研究的前沿,通过研究这些软件可以对异步电路的模型有更为深入的认识。论文整理列举了有关异步电路的63种软件工具,并将其分为设计、仿真、相关设计工具、前端设计、综合和验证6个方面。最后,在这些软件中选取两种设计软件对一个简单的例子进行了设计实现,以体现异步电路的设计特点。     

基于去同步技术的异步8051设计与实现

随着半导体工艺的发展,同步电路面临的时钟偏差、功耗等问题日益突出,异步设计方法得到广泛研究和关注。去同步技术可以方便地实现从同步向异步的转化,成为很有前途的异步电路设计方法。基于去同步技术设计实现了一款异步8051微控制器,着重介绍了基于去同步技术的设计流程与异步控制器设计方法。分析表明,在相同的电压、温度条件下,该异步8051性能与同步8051相当,而功耗约为1/2。     

异步片上网络研究综述

异步片上网络具有低动态功耗、对延迟抖动的不敏感、统一的网络接口、较低的系统集成复杂度和较好的电磁兼容能力等众多特性,是下一代片上多核微处理器和多核片上系统的标准片上通信架构之一.在简单介绍异步电路的相关理论后,从多个方面概述了当前异步片上网络的研究成果,包括网络拓扑、同步?异步接口、流控制、服务质量、路由算法、低功耗设计、容错和可测性设计以及设计自动化;然后介绍并分析了一些具有代表性的异步片上网络设计案例.研究显示,异步片上网络具有众多同步片上网络所不具备的优点,大量的片上多核系统将使用异步片上网络作为其片上通信系统,但它们的易用性和网络性能亟待提高.     

VLSI asynchronous systems: specification and synthesis

Most of today's digital systems are realized using synchronous (i.e. globally clocked) VLSI circuits. For many reasons, it is becoming increasingly hard to build large synchronous circuits. Although several techniques for building non-clocked (i.e. asynchronous) sequential circuits have been known for some time, they have been largely ignored by the digital design community. Recently, however, asynchronous circuits have been enjoying a revival. After reviewing recent research in this area, we take a simple collection of examples and, through them, explain our design system for specifying and synthesizing asynchronous circuits. We show that by being able to work in a framework where circuit activities do not have to coincide with clock pulses, designers obtain several avenues for circuit optimization that are highly promising for creating efficient and modularly expandable circuits.     

Guest Editors' Introduction: GALS Design and Validation

Globally asynchronous, locally synchronous (GALS) design has grown in popularity in both academia and industry. Breaking the synchrony assumption in digital design is often unsettling for designers, and to alleviate the difficulty, researchers in EDA have been proposing various GALS-based solutions. However, the tools, verification techniques, and testing methodologies for asynchronous designs are not as widespread as for synchronous digital design, leading to the hitherto limited usage of GALS design approaches. This special issue introduces some of the basic issues of GALS design and validation in the hardware domain. The hope is that this special issue will generate more interest by researchers and industry practitioners in creating design tools, techniques, and validation methodologies for GALS design.     

异步子字并行乘累加单元的设计与实现

异步电路能很好地解决同步集成电路设计中出现的时钟扭曲和时钟功耗过大等问题。本文采用异步集成电路设计方法设计了一款32位异步子字并行乘累加单元,并在0.18μm工艺条件下实现了该单元。通过使用特殊的部分积译码电路,该乘累加单元能支持多种子字并行模式,适用于多媒体处理。评测结果表明,异步乘累加单元的性能和功耗指标均优于采用同样结构的同步乘累加单元。     

Three generations of asynchronous microprocessors

We trace the evolution of Caltech asynchronous processors from a simple proof of concept, to a high-performance MIPS-like processor using a different buffer circuit for better performance, to the latest 8051 clone targeting low-energy operation. We describe the control aspects of the evolving circuit styles. We describe these three generations of asynchronous microprocessors (Caltech asynchronous processors, MiniMIPS and Lutonium) and the corresponding circuit families and design methods. The asynchronous circuits we use are called quasidelay-insensitive (QDI) circuits. A QDI circuit involves no assumption about, or knowledge of, delays in operators and wires, except for isochronic forks, which the designer assumes have similar delays on the different branches. QDI circuits are the most conservative asynchronous circuits in terms of delays.     

A dynamic analysis of the interplay between asynchronous and synchronous communication in online learning: The impact of motivation

With the increased affordances of synchronous communication tools, more opportunities for online learning to resemble face‐to‐face settings have recently become available. However, synchronous communication does not afford as much time for reflection as asynchronous communication. Therefore, a combination of synchronous and asynchronous communication in e‐learning would seem desirable to optimally support learner engagement and the quality of student learning. It is still an open question though, how to best design online learning with a blend of synchronous and asynchronous communication opportunities over time. Few studies have investigated the relationship between learners' actual use of synchronous and asynchronous communication over time. Therefore, this study addressed that relationship in an online course (N = 110), taking into account student motivation, and employing a dynamic inter‐temporal perspective. In line with our assumptions, we found some support for the expected association between autonomous motivation and engagement in asynchronous and synchronous communication, be it restricted primarily to the first course period. Also, positive relations between engagement in synchronous and asynchronous communication were found, with the strongest influence from using asynchronous to synchronous communication. This study adds to the knowledge base needed to develop guidelines on how synchronous communication can be combined with asynchronous learning.     

基于Petri网的异步电路设计关键技术研究

Petri网是异步并发现象建模的重要工具,以异步处理器为代表的异步电路以其在解决时钟扭曲,低功耗方面的优势受到越来越广泛的关注,异步电路设计的主要问题之一是缺乏成熟的EDA工具支持异步电路的设计风格,采用基于信号转换图(STG)的方法,完成了一个基于握手协议的异步控制部件的Petri网模型建立以及仿真和实现。并进一步给出了一个异步FIFO的设计应用实例。通过标准的时序仿真方法,得到的仿真结果表明上述方法能够很好地完成异步电路的设计而且在综合效率和资源利用上有明显的改进。     

Modelling and distributed simulation of asynchronous hardware

Synchronous VLSI design is approaching a critical point, with clock distribution becoming an increasingly costly and complicated issue and power consumption rapidly emerging as a major concern. Hence, recently, there has been a resurgence of interest in asynchronous digital design techniques as they promise to liberate VLSI systems from clock skew problems, offer the potential for low power and high performance and encourage a modular design philosophy which makes incremental technological migration a much easier task. This activity has revealed a need for modelling and simulation techniques suitable for the asynchronous design style. Contributing to the quest for modelling and simulation techniques suitable for asynchronous design, and motivated by the increasing debate regarding the potential of CSP for this purpose, this paper investigates the suitability of occam, a CSP-based programming language, for the modelling and simulation of complex asynchronous systems. A generic modelling framework is introduced and issues arising from the parallel semantics of CSP/occam when the latter is employed to perform simulation are addressed.