Drain current enhancement and negligible current collapse in GaN MOSFETs with atomic-layer-deposited HfO2 as a gate dielectric

Accumulation-type GaN metal-oxide-semiconductor field-effect-transistors (MOSFET’s) with atomic-layer-deposited HfO₂ gate dielectrics have been fabricated; a 4 μm gate-length device with a gate dielectric of 14.8 nm in thickness (an equivalent SiO₂ thickness of 3.8 nm) gave a drain current of 230 mA/mm and a broad maximum transconductance of 31 mS/mm. Owing to a low interfacial density of states (D_it) at the HfO₂/GaN interface, more than two third of the drain currents come from accumulation, in contrast to those of Schottky-gate GaN devices. The device also showed negligible current collapse in a wide range of bias voltages, again due to the low D_it, which effectively passivate the surface states located in the gate-drain access region. Moreover, the device demonstrated a larger forward gate bias of +6 V with a much lower gate leakage current.     

Simulation and fabrication of high voltage AlGaN/GaN based Schottky diodes with field plate edge termination

In this paper, we report the breakdown voltage (BV) of AlGaN/GaN based Schottky diodes with field plate edge termination. Simulation and fabrication of AlGaN/GaN Schottky diodes were carried out. The simulations were performed using the commercial 2-D device simulator DESSIS. From the simulations, it is found that for a given gate-Ohmic distance (L_gd) of 10 μm, 2DEG of 1 × 10¹³ cm⁻² and field plate length (L_FP) of 2.5 μm, highest BV can be obtained for a silicon nitride thickness of 8000 Å and this BV value is more than 5 times that for a Schottky diode without field plate. The breakdown voltages were also simulated for different field plate lengths. The BV values obtained on the fabricated Schottky diodes are compared with the simulation data and the experimental results follow the trend obtained from the simulation. Simulations were also carried out on a Schottky diode with field plate placed over a stepped insulator with L_gd = 10 μm, L_FP = 5 μm and 2DEG = 1 × 10¹³ cm⁻² and the obtained BV values are about 7 times that without field plate.     

Cubic GaN/AlGaN Schottky-barrier devices on 3C-SiC substrates

In this work, we focus on the fabrication of cubic GaN based Schottky-barrier devices (SBDs) and measured current voltage (I-V) characteristics and the critical field for electronic breakdown. Phase-pure cubic GaN and c-Al_xGa_1 − xN/GaN structures were grown by plasma assisted molecular beam epitaxy (MBE) on 200 μm thick free-standing 3C-SiC (1 0 0) substrates, which were produced by HOYA Advanced Semiconductor Technologies Co., Ltd. The thickness of the c-GaN and c-Al_0.3Ga_0.7N epilayers were about 600 and 30 nm, respectively. Ni/In Schottky contacts 300 μm in diameter were produced on c-GaN and c-Al_0.3Ga_0.7N/GaN structures by thermal evaporation using contact lithography. A clear rectifying behavior was measured in our SBDs and the I-V behavior was analyzed in detail, indicating the formation of a thin surface barrier at the Ni-GaN interface. Annealing of the Ni Schottky contacts in air at 200 °C reduces the leakage current by three orders of magnitude. The doping density dependence of breakdown voltages derived from the reverse breakdown voltage characteristics of c-GaN SBDs is investigated. The experimental values of breakdown voltage in c-GaN are in good agreement with theoretical values and show the same dependence on doping level as in hexagonal GaN. From our experimental data, we extrapolate a blocking voltage of 600 V in c-GaN films with a doping level N_D = 5 × 10¹⁵ cm⁻³.     

Observation of Ni silicide formations and field emission properties of Ni silicide nanowires

The Ni silicide nanowires were grown by physical vapor deposition. The morphological changes of silicide formation were observed on a gradient Ni film thickness, which visualized the critical thickness is 60-80 nm to grow nanowires. The field emission measurement provided uniform characteristics and high field enhancement factors were obtained to be 3180 and 3002 from the Ni silicide nanowires grown on a Si substrate and a tungsten plate, respectively. By using a conductive tungsten plate, the emission current was enhanced to be 172.5 μA/cm² comparing to 76.5 μA/cm² from a Si substrate at 5 V/μm.     

Transport and interface states in high-κ LaSiOx dielectric

The paper presents the results of capacitance-voltage, conductance-frequency and current-voltage characterization in the wide temperature range (140-300 K) as well as results of low temperature (5-20 K) thermally stimulated currents (TSC) measurements of metal-oxide-semiconductor (MOS) structures with a high-κ LaSiO_x dielectric deposited on p- and n-type Si(1 0 0) substrate. Interface states (D_it) distribution determined by several techniques show consistent result and demonstrates the adequacy of techniques used. Typical maxima of interface states density were found as 4.6 × 10¹¹ eV⁻¹cm⁻² at 0.2 eV and 7.9 × 10¹¹ eV⁻¹cm⁻² at 0.77 eV from the silicon valence band. The result of admittance spectroscopy showed the presence of local states in bandgap with activation energy E_a = 0.38 eV from silicon conductance band, which is in accord with interface states profile acquired by conductance method. Low-temperature TSC spectra show the presence of shallow traps at the interface with activation energies ranging from 15 to 32 meV. The charge carrier transport through the dielectric film was found to occur via Poole-Frenkel mechanism at forward bias.     

InGaAs and Ge MOSFETs with high κ dielectrics

InGaAs and Ge MOSFETs with high κ’s are now the leading candidates for technology beyond the 15 nm node CMOS. The UHV-Al₂O₃/Ga₂O₃(Gd₂O₃) [GGO]/InGaAs has low electrical leakage current densities, C-V characteristics with low interfacial densities of states (D_it’s) and small frequency dispersion in both n- and p-MOSCAPs, thermal stability at temperatures higher than >850 °C, a CET of 2.1 nm (a CET of 0.6 nm in GGO), and a well tuning of threshold voltage V_th with metal work function. Device performances in drain currents of >1 mA/μm, transconductances of >710 μS/μm, and peak mobility of 1600 cm²/V s at 1 μm gate-length were demonstrated in the self-aligned, inversion-channel high In-content InGaAs n-MOSFETs using UHV-Al₂O₃/GGO gate dielectrics and ALD-Al₂O₃. Direct deposition of GGO on Ge without an interfacial passivation layer has given excellent electrical performances and thermodynamic stability. Self-aligned Ge p-MOSFETs have shown a high drain current of 800 μA/μm and peak transconductance of 420 μS/μm at 1 μm gate-length.     

Effect of dimensional parameters on the current of MSM photodetector

In this work, we present the influence of dimensional parameters on dark current and photocurrent of the metal-semiconductor-metal photodetector (MSM). MSM photodetectors of different sizes have been fabricated on GaAs (NID). The active area of MSM samples varies between 1×1 μm² and 10×10 μm² with equal electrodes spacing and finger widths (l=D) varying between 0.2 and 1 μm. The I(V) characterization in inverse and direct polarization in darkness shows good symmetry of curves, which shows the good performance of components and successful fulfillment of the Schottky contacts. The application of laser fiber of incident light power of 16 mW at wavelength of 850 nm for the illumination of the MSM photodetectors showed the evolution of the photocurrent ranging from 0.75 to 1.81 mA, respectively, for 1 to 0.2 μm electrodes spacing at 3 V and active area S=3×3 μm². We showed also that variation ranging from 0.45 to 2.5 mA, respectively, for S=1×1 μm² to S=10×10 μm² at 3 V and 0.3 μm electrodes spacing. The resistance of MSM photodetectors obtained evolved proportionally to the electrodes spacing (0.87 kΩ for D=0.2 μm and 2.27 kΩ for D=1 μm with S=3×3 μm²) and inversely proportional to the surface area (2.02 kΩ for S=1×1 μm², and 0.56 kΩ for S=10×10 μm² with 0.3 μm inter electrodes spacing).     

Sub-100 nm ALD-assisted nanoimprint lithography for realizing vertical organic transistors with high ON/OFF ratio and high output current

We introduced a conformal atomic-layer-deposited aluminum oxide layer to cover the imprint mold to reduce the feature size and to strengthen the mold durability. A nano-hole array pattern with diameter down to 85 nm was successfully transferred to sample substrate to fabricate a vertical organic transistor. The Imprint vertical organic transistor exhibited high output current density as 4.35 cm²/V s and high ON/OFF current ratio as 11,000 at a low operation voltage as 1.5 V.     

Improved electrical characteristics and reliability of amorphous InGaZnO metal-insulator-semiconductor capacitor with high κ HfOxNy gate dielectric

High κ HfO_xN_y film was deposited on amorphous InGaZnO (a-IGZO) by radio-frequency reactive sputtering using an HfO₂ target in nitrogen plus argon ambience, the electrical characteristics and reliability of a-IGZO metal-insulator-semiconductor (MIS) capacitors were investigated. Experimental results indicate that the nitrogen incorporation into HfO₂ can produce a strong nitride interfacial barrier layer, thus lead to reducing the interface state density, suppressing the hysteresis voltage, and decreasing the gate-leakage current. Improved performance has been achieved for HfO_xN_y gate dielectric a-IGZO MIS capacitors, with a interface state density of 5.1 × 10¹¹ eV⁻¹ cm⁻², a gate-leakage current density of 3.9 × 10⁻⁵ A/cm² at V_fb + 1 V, an equivalent permittivity of 24, and a hysteresis voltage of 105 mV. Moreover, the enhanced reliability of Al/HfO_xN_y/a-IGZO MIS capacitor is observed with a small degradation of electrical characteristics after a high field stressing at 10 MV/cm for 3600 s.     

Pentacene thin-film transistors with sol-gel derived amorphous Ba0.6Sr0.4TiO3 gate dielectric

An amorphous Ba_0.6Sr_0.4TiO₃ (BST) film with the thickness of 200 nm was deposited on indium-tin-oxide (ITO)-coated glass substrate through sol-gel route and post-annealing at 500 °C. The dielectric constant of the BST film was determined to be 20.6 at 100 kHz by measuring the Ag/BST/ITO parallel plate capacitor, and no dielectric tunability was observed with the bias voltage varying from −5 to 5 V. The BST film shows a dense and uniform microstructure as well as a smooth surface with the root-mean-square (RMS) roughness of about 1.4 nm. The leakage current density was found to be 3.5 × 10⁻⁸ A/cm² at an applied voltage of −5 V. The transmittance of the BST/ITO/glass structure is more than 70% in the visible region. Pentacene based transistor using the as-prepared BST film as gate insulator exhibits a low threshold voltage of −1.3 V, the saturation field-effect mobility of 0.68 cm²/Vs, and the current on/off ratio of 3.6 × 10⁵. The results indicate that the sol-gel derived BST film is a promising high-k gate dielectric for large-area transparent organic transistor arrays on glass substrate.     

Flexible metal-insulator-metal capacitor using plasma enhanced binary hafnium-zirconium-oxide as gate dielectric layer

We have used a sol-gel spin-coating process to fabricate a new metal-insulator-metal capacitor comprising 10-nm thick binary hafnium-zirconium-oxide (Hf_xZr_1−xO₂) film on a flexible polyimide (PI) substrate. The surface morphology of this Hf_xZr_1−xO₂ film was investigated using atomic force microscopy and scanning electron microscopy, which confirmed that continuous and crack-free film growth had occurred on the PI. After oxygen plasma pre-treatment and subsequent annealing at 250 °C, the film on the PI substrate exhibited a low leakage current density of 3.22 × 10⁻⁸ A/cm² at −10 V and maximum capacitance densities of 10.36 fF/μm² at 10 kHz and 9.42 fF/μm² at 1 MHz. The as-deposited sol-gel film was oxidized when employing oxygen plasma at a relatively low temperature (∼250 °C), thereby enhancing the electrical performance.     

High-power broad-area InGaNAs/GaAs quantum-well lasers in the 1200 nm range

High-power broad-area InGaNAs/GaAs quantum-well (QW) edge-emitting lasers on GaAs substrates in the 1200 nm range are reported. The epitaxial layers of the InGaNAs/GaAs QW laser wafers were grown on n⁺-GaAs substrates by using metal-organic chemical vapor deposition (MOCVD). The thickness of the InGaNAs/GaAs QW layers is 70 Å/1200 Å. The indium content (x) of the In_xGa_1−xN_yAs_1−y QW layers is estimated to be 0.35-0.36, while the nitrogen content (y) is estimated to be 0.006-0.009. More indium content (In) and nitrogen content (N) in the InGaNAs QW layer enables the laser emission up to 1300 nm range. The epitaxial layer quality, however, is limited by the strain in the grown layer. The devices were made with different ridge widths from 5 to 50 μm. A very low threshold current density (J_th) of 80 A/cm² has been obtained for the 50 μm × 500 μm LD. A number of InGaNAs/GaAs epi-wafers were made into broad-area LDs. A maximum output power of 95 mW was measured for the broad-area InGaNAs/GaAs QW LDs. The variations in the output powers of the broad-area LDs are mainly due to strain-induced defects the InGaNAs QW layers.     

Thin titanium oxide films deposited by e-beam evaporation with additional rapid thermal oxidation and annealing for ISFET applications

Titanium oxide (TiO₂) has been extensively applied in the medical area due to its proved biocompatibility with human cells [1]. This work presents the characterization of titanium oxide thin films as a potential dielectric to be applied in ion sensitive field-effect transistors. The films were obtained by rapid thermal oxidation and annealing (at 300, 600, 960 and 1200 °C) of thin titanium films of different thicknesses (5 nm, 10 nm and 20 nm) deposited by e-beam evaporation on silicon wafers. These films were analyzed as-deposited and after annealing in forming gas for 25 min by Ellipsometry, Fourier Transform Infrared Spectroscopy (FTIR), Raman Spectroscopy (RAMAN), Atomic Force Microscopy (AFM), Rutherford Backscattering Spectroscopy (RBS) and Ti-K edge X-ray Absorption Near Edge Structure (XANES). Thin film thickness, roughness, surface grain sizes, refractive indexes and oxygen concentration depend on the oxidation and annealing temperature. Structural characterization showed mainly presence of the crystalline rutile phase, however, other oxides such Ti₂O₃, an interfacial SiO₂ layer between the dielectric and the substrate and the anatase crystalline phase of TiO₂ films were also identified. Electrical characteristics were obtained by means of I-V and C-V measured curves of Al/Si/TiO_x/Al capacitors. These curves showed that the films had high dielectric constants between 12 and 33, interface charge density of about 10¹⁰/cm² and leakage current density between 1 and 10⁻⁴ A/cm². Field-effect transistors were fabricated in order to analyze I_D x V_DS and log I_D × Bias curves. Early voltage value of −1629 V, R_OUT value of 215 MΩ and slope of 100 mV/dec were determined for the 20 nm TiO_x film thermally treated at 960 °C.     

Thermal measurements and analysis of AlGaInP/GaInP MQW red LEDs with different chip sizes and substrate thicknesses

Thermal properties of AlGaInP/GaInP MQW red LEDs are investigated by thermal measurements and analysis for different chip sizes and substrate thicknesses. To extract the thermal resistance (R_th), junction temperature (T_j) is experimentally determined by both forward voltage and electroluminescence (EL) emission peak shift methods. For theoretical thermal analysis, thermal parameters are calculated in simulation using measured heat source densities. The T_j value increases with increasing the injection current, and it decreases as the chip size becomes larger. The use of a thin substrate improves the heat removal capability. At 450 mA, the T_j values of 315 K and 342 K are measured for 500 × 500 μm² LEDs with 110 μm and 350 μm thick substrates, respectively. For 500 × 500 μm² LEDs with 110 μm thick substrate, the R_th values of 13.99 K/W and 14.89 K/W are obtained experimentally by the forward voltage and EL emission peak shift methods, respectively. The theoretically calculated value is 13.44 K/W, indicating a good agreement with the experimental results.     

Field electron emission from amorphous CNx:B films

CN_x:B thin films were prepared on titanium coated ceramic substrate by pulsed laser deposition technique (PLD). The microstructure of the film was examined using scanning electron microscopy (SEM), X-ray diffraction (XRD), X-ray photoelectron spectroscopy (XPS) and Raman spectroscopy. The analyses indicate that the deposited samples are amorphous CN_x:B thin films. Field electron emission characteristics of amorphous CN_x:B thin films were measured in a vacuum chamber with a base pressure of about 3.2×10⁻⁵ Pa. The turn-on field of the film was 3.5 V/μm. The current density was 60 μA/cm² at an electric field of 9 V/μm. The experimental results indicate that this film could be a promising material applicable to cold cathodes.     

Imaging one-dimensional and two-dimensional planar photodiode detectors fabricated by ion milling molecular beam epitaxy CdHgTe

Imaging one-dimensional (1-D) and two-dimensional (2-D) arrays of mid-wavelength infrared (MWIR) and long-wavelength infrared (LWIR) planar photodiodes were fabricated by ion milling of vacancy-doped molecular beam epitaxy Cd_xHg_1−xTe layers. Sixty-four-element 1-D arrays of 26×26 μm² or 26×56 μm² diodes were processed. Zero-bias resistance-area values (R₀A) at 77 K of 4×10⁶ Θcm² at cutoff wavelength λ_CO=4.5 μm were measured, as well as high quantum efficiencies. To avoid creating a leakage current during ball bonding to the 1-D array diodes, a ZnS layer was deposited on top of the CdTe passivation layer, as well as extra electroplated Au on the bonding pads. The best measured noise equivalent temperature difference (NETD) on a LWIR array was 8 mK, with a median of 14 mK for the 42 operable diodes. The best measured NETD on a MWIR array was 18 mK. Two-D arrays showed reasonably good uniformity of R₀A and zero-bias current (I₀) values. The first 64×64 element 2-D array of 16×16 μm² MWIR diodes has been hybridized to read-out electronics and gave median NETD of 60 mK.     

The structural and electrical properties of the SrTa2O6/In0.53Ga0.47As/InP system

The structural and electrical properties of SrTa₂O₆(SrTaO)/n-In_0.53GaAs_0.47(InGaAs)/InP structures where the SrTaO was grown by atomic vapor deposition, were investigated. Transmission electron microscopy revealed a uniform, amorphous SrTaO film having an atomically flat interface with the InGaAs substrate with a SrTaO film thickness of 11.2 nm. The amorphous SrTaO films (11.2 nm) exhibit a dielectric constant of ∼20, and a breakdown field of >8 MV/cm. A capacitance equivalent thickness of ∼1 nm is obtained for a SrTaO thickness of 3.4 nm, demonstrating the scaling potential of the SrTaO/InGaAs MOS system. Thinner SrTaO films (3.4 nm) exhibited increased non-uniformity in thickness. From the capacitance-voltage response of the SrTaO (3.4 nm)/n-InGaAs/InP structure, prior to any post deposition annealing, a peak interface state density of ∼2.3 × 10¹³ cm⁻² eV⁻¹ is obtained located at ∼0.28 eV (±0.05 eV) above the valence band energy (E_v) and the integrated interface state density in range E_v + 0.2 to E_v + 0.7 eV is 6.8 × 10¹² cm⁻². The peak energy position (0.28 ± 0.05 eV) and the energy distribution of the interface states are similar to other high-k layers on InGaAs, such as Al₂O₃ and LaAlO₃, providing further evidence that the interface defects in the high-k/InGaAs system are intrinsic defects related to the InGaAs surface.     

Influence of the channel layer thickness on electrical properties of indium zinc oxide thin-film transistor

Thin-film transistors (TFTs) were fabricated on SiO₂/n⁺-Si substrates using amorphous binary In₂O₃-ZnO (a-IZO) films with different thickness for active channel layers deposited by the rf magnetron sputtering at room temperature. The performance of devices was found to be thickness dependent. With the active layer thickness from 33 to 114 nm, the field-effect mobility μ_FE increased from 1.60 to 4.59 cm²/V s, the threshold voltage V_TH decreased from 62.26 to 20.82 V, and the subthreshold voltage swing S decreased from 4.06 V/decade to 1.30 V/decade. Further, the dependence of TFTs’ electrical properties on active layer thickness was investigated in detail on the basis of free carrier density and interface scattering.     

Prediction of transmission line lifetimes over temperature and current density

Transmission line test structures are stressed at ambient temperatures ranging from 75 to 160 °C and current densities from ∼5 to 7 MA/cm². Failure is considered to have occurred when the resistance increases by 10% over its initial value. Failure times are modeled using Black’s equation and the E_a and current density exponent ‘n’ are found to be ∼1 eV and ∼2-4, respectively, in agreement with the literature. Predicted FIT rates are found to be negligible easily meeting even the most severe FIT budget. Experimental evidence suggests that the current density used in testing is well above the critical Blech value. Predicted lifetimes at J = 2.3 MA/cm² are consistent with observation, indicating that high stress data can be used to predict low stress behavior.     

Hydrogen passivation effects under negative bias temperature instability stress in metal/silicon-oxide/silicon-nitride/silicon-oxide/silicon capacitors for flash memories

The paper presents the passivation effect of post-annealing gases on the negative bias temperature instability of metal/silicon-oxide/silicon-nitride/silicon-oxide/silicon (MONOS) capacitors. MONOS samples annealed at 850 °C for 30 s by a rapid thermal annealing (RTA) are treated by additional annealing in a furnace, using annealing gases N₂ and N₂-H₂ (2% hydrogen and 98% nitrogen gas mixture) at 450 °C for 30 min. MONOS samples annealed in an N₂-H₂ environment are found to have lowest oxide trap charge density shift, ΔN_ot = 8.56 × 10¹¹ cm⁻², and the lowest interface-trap density increase, ΔN_it = 4.49 × 10¹¹ cm⁻² among the three samples as-deposited, annealed in N₂ and N₂-H₂ environments. It has also been confirmed that the same MONOS samples have the lowest interface-trap density, D_it = 0.834 × 10¹¹ eV⁻¹ cm⁻², using small pulse deep level transient spectroscopy. These results indicate that the density of interface traps between the silicon substrate and the tunneling oxide layer are significantly reduced by the additional furnace annealing in the N₂-H₂ environment after the RTA.