新型DVI数字视频接口电路的研究

随着各种平板显示器的广泛应用,高画质视频接口技术的研究凸显重要.采用基于DVI接口解码芯片SiI161硬件电路设计方案,进行了高分辨率平板显示嚣视频接口电路的试验研究,实现了平板显示器可用高质量数字视频 数据的解码输出.该设计方案已在液晶显示器等接口电路系统中得到验证,为系统提供优质稳定的数字视频源,最高图像显示分辨率...     

A 12-b 5-Msample/s two-step CMOS A/D converter

Two-step flash architectures are an effective means of realizing high-speed high-resolution analog-to-digital converters (ADCs) because they can be implemented without the need for operational amplifiers having either high gain or a large output swing. Moreover, with conversion rates approaching half those of fully parallel designs, such half-flash architectures provide both a relatively small input capacitance and low power dissipation. The authors describe the design of a 12-b 5-Msample/s A/D converter that is based on a two-step flash topology and has been integrated in a 1-μm CMOS technology. Configured as a fully differential circuit, the converter performs a 7-b coarse flash conversion followed by a 6-b fine flash conversion. Both analog and digital error correction are used to achieve a resolution of 12 b. The converter dissipates only 200 mW from a single 5-V supply and occupies an area of 2.5 mm × 3.7 mm     

Spread spectrum clock Generator with delay cell array to reduce electromagnetic interference

In high-speed digital systems, most of the electromagnetic interference (EMI) from the system is caused by high-speed digital clock drivers and synchronized circuits. To reduce the EMI from the system clocks, spread spectrum clock (SSC) techniques that modulate the system clock frequency have been proposed. A conventional SSC generator (SSCG) has been implemented with a phase locked loop (PLL) by controlling a period jitter. However, the conventional SSCG with PLL becomes more difficult to implement at higher clock frequencies, in the gigahertz range, because of the random period jitter of the PLL. Furthermore, the attenuation of EMI is decreased due to the random period jitter of the PLL. To overcome the problems associated with the random period jitter, we propose an SSCG with a delay cell array (DCA), which controls the position of clock transitions with a triangular modulation profile. Measurement and simulation have demonstrated that the proposed SSCG with DCA is easier to implement and more effective in attenuating the EMI compared with the conventional SSCG with PLL. The proposed SSCG with DCA was implemented on a chip using a 0.35-/spl mu/m CMOS process and achieved a 9-dB attenuation of the EMI at 390 MHz.     

平板扬声器的振动分析

研究了适用于平板显示器的平板音响,将平板显示器的屏作为扬声器的振膜,在此基础上阐述了底边固定的平板的振动特性。对不同大小不同形状的板的自振频率及激振情况进行计算,通过对计算结果的分析研究,提出了应该使平板底边与侧边的比值尽可能大、平板面积也尽可能大,以便减小共振时产生的噪音;同时限制激励幅值在一定范围内以减小平板产生的最大位移值。     

A Wired-AND Current-Mode Logic Circuit Technique in CMOS for Low-Voltage, High-Speed and Mixed-Signal VLSIC

A wired-AND current-mode logic (WCML) circuit techniquein CMOS technology for low-voltage and high-speed VLSI circuitsis proposed, and a WCML cell library is developed using standard0.8 micron CMOS process. The proposed WCML technique appliesthe analog circuit design methodologies to the digital circuitdesign. The input and output logic signals are represented bycurrent quantities. The supply current of the logic circuitis adjustable for the required logic speed and the switchingnoise level. The noise is reduced on the power supply lines andin the substrate by the current-steering technique and by thesmooth swing of the reduced node potentials. Precise analogcircuits and fast digital circuits can be integrated on the samesilicon substrate by using the low noise property of the WCML.It is shown by the simulations that at low supply voltages, theWCML is faster and generates less switching noise when comparedto the static-CMOS logic. At high speeds, the power dissipationof the WCML is less than that of the static-CMOS logic.     

An electronic ballast with wide dimming range, high PF, and low EMI

The authors describe an electronic ballast design with the capability of low radiated and conducted EMI over a wide dimming range. It overcomes some limitations of traditional electronic ballasts that use frequency variation for dimming control. The proposed design allows soft switching of the ballast from full-power operation down to less than 10% power. Low-cost and low-voltage power metal oxide semiconductor field effect transmitters (MOSFETs) can be used in the proposed dimmable electronic ballast. The design approach is described and implemented successfully in a 2×36 W fluorescent lamp system     

A Phase Interpolator CDR with Low-Voltage CML Circuits

In this paper, a phase interpolator clock and data recovery (CDR) with low-voltage current mode logic (CML) latched, buffers, and muxes is presented. Because of using the CML circuits, the CDR can operate in a low supply voltage. And the original swing of the differential inputs and outputs is less than that of the CMOS logic. The power supply voltage is 1.2 V, and the static current consumption is about 20 mA. In this phase interpolator CDR, the charge pump and loop filter are replaced by a digital filter. And this structure offers the benefits of increased system stability and faster acquisition.     

Cameras and display systems

We first discuss the position of cameras and displays in digital television systems. It is difficult to realize these devices in digital form so cameras and displays will remain analog for some time, even after television signal processing is implemented digitally. Nevertheless, the importance of camera and display in television systems will not diminish. These devices will always be key elements in the human interface. Second, we describe the current state of the art and future trends in camera and display technology. In addition to providing an overview of the charge coupled device (CCD), we discuss the digital technologies used in a CCD camera. We also provide an overview of currently available displays-CRT's, flat panel displays, projection displays, and head-mounted displays (HMD's)-and discuss future possible lines of research. Finally, we discuss camera and display technology as applied to digital television systems, including the use of these devices in a multimedia environment     

一种新型的低电磁干扰的亚低压差分接收器

本文介绍了一种低电磁干扰的用于标准移动图像架构的亚低压差分（subLVDS）接收器，它符合标准移动图像架构（SMIA）标准。由于使用了差分结构和小摆幅信号，它可以同时实现低功耗和高速传输。在本文描述的接收器电路里，高速的共模范围变化的小幅度信号成功的被接收和恢复。本电路在中芯国际1．2V／2．5V1p5m0．13μm CMOS逻辑工艺上投片，伪随机码传输高达1．4Gbps。     

三种改进结构型BiCMOS逻辑单元的研究

为满足低压、高速、低耗数字系统的应用需求 ,通过采用改进电路结构和优化器件参数的方法 ,设计了三种改进结构型BiCMOS逻辑单元电路。实验结果表明 ,所设计电路不但具有确定的逻辑功能 ,而且获得了高速、低压、低耗和接近于全摆幅的特性 ,它们的工作速度比高速CMOS和原有的互补对称BiCMOS(CBiCMOS)电路快约一倍 ,功耗在 6 0MHz频率下仅高出 1 4 9～ 1 71mW ,但延迟 功耗积却比原CBiCMOS电路平均降低了4 0 3%。     

HDMI接口在FED中的应用

HDMI作为新型的高清晰数字多媒体接口规范，已广泛运用于各种平板显示设备中．FED是一种新型的平板显示器件，其视频接口也须向高清晰、高集成方向发展。文章结合HDMI的规范，介绍接口器件Si19023的内部机构，着重论述了Si19023的性能、工作原理及其在FED显示器视频驱动电路中的硬件设计方案。该方案利用AL310控制器．可以运用于多种平板显示器件中。     

Low-Power Ternary Content-Addressable Memory Design Using a Segmented Match Line

Power consumption in match lines is the most critical issue for low-power ternary content-addressable memory (TCAM) designs. In the proposed match-line architecture, the match line in each TCAM word is partitioned into four segments and is selectively pre-charged to reduce the match-line power consumption. The partially charged match lines are evaluated to determine the final comparison result by sharing the charges deposited in various parts of the partitioned segments. This arrangement reduces the match-line power consumption by reducing effective capacitor loading and voltage swing at match lines. The segmented architecture also enhances operational speed by evaluating multiple segments in parallel and by overlapping the pre-charging and evaluation stages. 512 $times$ 72 TCAM is designed using 0.18-$mu{hbox {m}}$ CMOS technology. The extracted RC values are used to show the power reduction benefits. The sample design demonstrated that the match-line power consumption using a segmented match line was conservatively 44% of that produced by traditional parallel TCAM. The power savings by segmenting match lines can be up to 41% over a low-voltage swing technique due to the independent discharge capability in segmented match-line architecture.      

基于ActelFPGA的DVI控制器设计

DVI接口(Digital Visual Interface)标准作为新一代的数字显示技术通讯标准[1],以全数字化的数据码流在传输信道上传输,文章通过对DVI接口应用系统的研究,提出了一个数字视频传输到数字显示的解决方案。通过分析与DVI应用相关的DDC(Display Data Channel)和EDID(Extended Display Identification Data)的设计方法,介绍了数字视频接口DVI系统的基本结构和原理,该接口系统应用在16x32像素全彩色LED显示屏系统上,能够很好地解码计算机输出的数据流,R、G、B数据可以正确地传输到LED屏显示系统并实时显示,经测试系统能稳定运行。     

A 2-ns 16K bipolar ECL RAM with reduced word-line voltage swing

A reduced word-line voltage swing (RWS) circuit configuration that results in a high-speed bipolar ECL (emitter coupled logic) RAM is proposed. The write operation can be performed with the configuration in the condition of reduced word-line voltage swing, which causes write operation error in conventional circuit configurations. The proposed configuration cuts off the hold current of the selected memory cell, and then the low-voltage node is charged up through the load p-n-p transistor. A 16-kb ECL RAM with a p-n-p loaded memory cell was fabricated by advanced silicide-base transistor (ASBT) process technology. A 2-ns access time was obtained with 1.8-W power consumption in which the word-line voltage swing was reduced by 0.7 V from a conventional case. Simulation results show that the access time is improved by 25% compared with a conventional case. Simulation results also show that writing time becomes comparable with the conventional time of 1.7 ns when the load p-n-p transistor has a saturation current of 5.0× 10¹⁷ A and a current gain of 1.0. The saturation current is 5 times larger and the current gain is 5 times smaller than those of the standard lateral p-n-p transistor     

Twisted differential line structure on high-speed printed circuit boards to reduce crosstalk and radiated emission

Differential signaling has become a popular choice for high-speed digital interconnection schemes on printed circuit boards (PCBs), offering superior immunity to crosstalk and external noise. However, conventional differential lines on PCBs still have unsolved problems, such as crosstalk and radiated emission. When more than two differential pairs run in parallel, a line is coupled to the line adjacent to it because all the lines are parallel in a fixed order. Accordingly, the two lines that constitute a differential pair are subject to the differential-mode crosstalk that cannot be canceled out by virtue of the differential signaling. To overcome this, we propose a twisted differential line (TDL) structure on a high-speed multilayer PCB by using a concept similar to a twisted pair in a cable interconnection. It has been successfully demonstrated by measurement and simulation that the TDL is subject to much lower crosstalk and achieves a 13-dB suppression of radiated emission, even when supporting a 3-Gb/s data rate.     

应用于平板显示器封装的ACF新进展

随着平板显示器大型化、薄型化、高分辨率的发展趋势,对平板显示器封装技术提出了更高的要求.ACF符合电子线路封装精细化、集成化的发展要求,目前已广泛应用于平板显示器(例如LCD)的封装领域.综述了ACF应用于平板显示器封装的主要形式如TCP、COF、COG,分析了各种不同封装形式对ACF提出的不同性能要求,以及为了满足这些要求对ACF中导电粒子的大小、含量、硬度以及ACF中使用树脂的种类等方面进行结构性能改进的最新进展.     

A class-B output buffer for flat-panel-display column driver

Due to the large number of output buffers on a column driver chip of a flat-panel display, the quiescent current and die area of the output buffer must be minimized. This paper presents a low static power, large output swing, and wide operating voltage range class-B output buffer amplifier for driving the large column line capacitance in a flat-panel display. A comparator is used in the negative feedback path to eliminate quiescent current in the output stage. The proposed output buffer circuit was implemented in a 0.8 μm CMOS process. Its output voltage swing is from 1 V to the supply voltage. With 5 V supply and 600 pF load, the maximum tracking error is ±7 mV. The measured static current is 24 μA. The settling time for 4 V swing to within 0.2% is 8 μs, which is more than adequate for driving 1280×1024 pixels liquid crystal displays with 86 Hz frame rate and 256 gray levels in each color     

A 3.3-V, 15-bit, delta-sigma ADC with a signal bandwidth of 1.1 MHzfor ADSL applications

The design of a high-resolution, high-speed, delta-sigma analog to-digital converter that operates from a single 3.3-V supply is presented. This supply voltage presents several design problems, such as reduced signal swing and nonzero switch resistance in the switched-capacitor circuits. These problems are tackled in this design by a careful optimization at the system level and by a detailed analysis of several circuit nonidealities. The converter uses a 2-1-1 cascade topology with optimized coefficients. For an oversampling-ratio of only 24, the converter achieves a signal-to-noise ratio of 87 dB, a signal-to-(noise+distortion) ratio of 82 dB, and an input dynamic range of 15 bits after comb filtering. The converter is sampled at 52.8 MHz, which results in the required signal bandwidth for asymmetrical digital subscriber line applications of 1.1 MHz. It is implemented in a 0.5-μm CMOS technology, in a 5-mm² die area, and consumes 200 mW from a 3.3-V power supply     

基于LVDS技术与FPGA的高速通讯应用研究

针对电子系统设计中不同电路板之间的大量数据的高速实时传送问题,提出采用并行低压传送技术的解决方案;由于Altera公司的Cyclone系列产品提供了对低压差分信号(LVDS)接口的支持,因此选用该器件在宽幅面喷墨绘图机设计中实现了高速的并行低压差分传送接口,数据传输的速率达到20 MB/s。     

Autostereoscopic 3D flat panel display using an LCD-pixel-associated parallax barrier

This letter reports an autostereoscopic three-dimensional （3D） fiat panel display system employing a newly designed LCD-pixel-associated parallax barrier （LPB）. The battler＇s parameters can be conveniently determined by the LCD pixels and can help to greatly simplify the conventional design. The optical system of the proposed 3D display is built and simulated to verify the design. For further experimental demonstration, a 508-mm autostereoscopic 3D displayprototype is developed and it presents good stereoscopic images. Experimental results agree well wlth the simulation, which reveals a strong potential for 3D display applications.