一种新的准正交空时分组码设计

根据正交设计理论,当发送天线数大于2时,不存在可以获得完全分集增益和全速率的复正交空时分组码。对空时分组码采用准正交设计,能够保证数据以全速率传输,但是会使其误码性能降低。本文根据矩阵正交理论提出了一种新的全速率准正交空时分组码并给出了一种基于QR分解的最大似然译码方法。仿真结果表明,本文方案与已有典型的准正交空时分组码相比,具有更好的误码性能。     

基于坐标间交织正交设计的空时分组码方案

依据空时分组码的复正交设计理论的推广,推导了基于坐标间交织正交设计（CIOD）的空时分组码设计方法,并根据Alamouti正交接收原理,对接收信号依次经过矢量正交变换、矢量虚部交换和矢量加权旋转处理,进行解调运算。最后在准静态平坦Rayleigh衰落信道中,对802.16d/e中使用的4发射天线基于CIOD的发射分集配置方案A进行了性能仿真,结果表明这些码具有较低的译码复杂性,与基于复数正交设计的空时分组码的译码复杂度相当,但性能要好。     

Customizing short-length LT codes with evolution strategies for video streaming protection

Designing short-length Luby Transform (SLLT) codes to best protect video streaming and multicasting over lossy communication remains largely an empirical exercise. In this paper, we present a systematic approach to customize the decoding performance of these codes so that the protected video bitstreams may have the best playback quality over a wide range of channel loss rates. Our approach begins with the proposal of a new SLLT decoding performance model based on three parameters: decoding overhead, symbol decoding failure rate and tail probability of symbol decoding failure rate. We then formulate the design of SLLT codes as a multi-objective optimization problem, specify the design objectives in terms of goal program, and search for the most suitable codes using an augmented weighted Tchebycheff method implemented with the Covariance Matrix Adaptation Evolution Strategy (CMA-ES). Two design examples are provided to illustrate the effectiveness of our approach: (1) an SLLT post-code of a short-length raptor code that provides erasure protection to H.264 AVC bitstreams, and (2) an SLLT post-code of a rateless UEP code that supports graceful degradation of H.264 SVC playback quality. Empirical results demonstrate that the proposed method is capable of producing SLLT codes with customized decoding performance, whereas, the customized codes enable the playback pictures to attain significantly higher PSNR values at different stages of the decoding process than the pictures recovered under the protection of conventionally optimized codes.     

TPC码译码器硬件仿真的优化设计

介绍一种TPC码迭代译码器的硬件设计方案,基于软判决译码规则,采用完全并行规整的译码结构,使用VHDL硬件描述语言,实现了码率为1/2的(8,4)二维乘积码迭代译码器,并特别通过硬件测试激励来实时测量所设计迭代译码器的误码率情况,提出了优化设计方案,和传统的硬件仿真方法相比大大提高了仿真效率。仿真结果证明该译码器有很大的实用性和灵活性。     

Processor architecture exploration and synthesis of massively parallel multi-processor accelerators in application to LDPC decoding

Numerous modern applications in various fields, such as communication and networking, multimedia, encryption, etc., impose extremely high demands regarding performance while at the same time requiring low energy consumption, low cost, and short design time. Often these very high demands cannot be satisfied by application implementations on programmable processors. Massively parallel multi-processor hardware accelerators are necessary to adequately serve these applications. The accelerator design for such applications has to decide both the micro-architectures of particular processors and the multi-processor system macro-architecture. Due to complex tradeoffs between the micro-architectures and macro-architectures, the micro- and macro-architecture design has to be performed in combination and not in separation, as with the state-of-the-art design methods and tools. To ensure effective and efficient application implementations, an adequate design space exploration (DSE) is necessary. It has to construct and analyze several most promising micro- and macro-architecture combinations and to select the best of them. In this paper, we will show that the lack of such a design space exploration would not only make it very difficult to satisfy the ultra-high performance demands of such applications, but it would also seriously degrade the accelerator quality in other design dimensions. To adequately design the multi-processor accelerators for highly-demanding applications, we proposed a quality-driven model-based design method. This paper is devoted to the processor architecture exploration and synthesis of the heterogeneous multi-processor system being one of the most important aspects of our method. The method is implemented in our automatic DSE tool. Using our DSE tool and the LDPC decoding application as a case study, we performed an extensive experimental research of automatic synthesis of various hardware multi-processors for LDPC decoding to show various complex issues and tradeoffs in the processor architecture design, and to demonstrate the high quality of our method and DSE tool in relation to this aspect.     

基于CPLD的正交编码信号采集和处理

介绍一种采用复杂可编程逻辑器件(CPLD)对正交编码信号采集和处理的设计.为提高光电增量编码器的解码精度,以CPLD为控制核心,设计信号采集、信号处理和硬件驱动3个模块.采用VHDL硬件描述语言设计信号处理模块,将其划分为滤波器、鉴相倍频器、计数器,并进行仿真和实验验证.结果表明该设计运行稳定、反馈精度高、可靠性强,分辨率可达0.09°.     

Performance of multiuser CDMA system with space-time block coding in MIMO Rayleigh fading channels

In this paper, by introducing orthogonal space-time coding scheme, the multiuser CDMA systems with different space time codes are given, and corresponding system performance is investigated over Rayleigh fading channel. A low-complexity multiuser receiver scheme is developed for space-time coded CDMA systems. The scheme can make full use of the complex orthogonality of space-time coding to simplify the high decoding complexity of the existing scheme. Compared to the existing scheme with exponential decoding complexity, it has linear decoding complexity. Based on the performance analysis and mathematical calculation, average bit error rate (BER) of the system is derived in detail, and tight closed-form approximation expressions of BER are attained. Simulation results on average BER are in agreement with the theory analysis. The results show that the proposed scheme can achieve almost the same performance as the existing scheme. Moreover, on the condition of same system throughput and concatenation of channel code, the given full-rate space-time coded CDMA system has lower BER than the full-diversity space-time coded CDMA systems.     

Robust nonlinear model identification methods using forward regression

In this correspondence new robust nonlinear model construction algorithms for a large class of linear-in-the-parameters models are introduced to enhance model robustness via combined parameter regularization and new robust structural selective criteria. In parallel to parameter regularization, we use two classes of robust model selection criteria based on either experimental design criteria that optimizes model adequacy, or the predicted residual sums of squares (PRESS) statistic that optimizes model generalization capability, respectively. Three robust identification algorithms are introduced, i.e., combined A- and D-optimality with regularized orthogonal least squares algorithm, respectively; and combined PRESS statistic with regularized orthogonal least squares algorithm. A common characteristic of these algorithms is that the inherent computation efficiency associated with the orthogonalization scheme in orthogonal least squares or regularized orthogonal least squares has been extended such that the new algorithms are computationally efficient. Numerical examples are included to demonstrate effectiveness of the algorithms.     

Differential space-time block-diagonal codes

A new differential space-time code, called differential space-time block-diagonal code (DSTBDC), is proposed for multiple-input multiple-output (MIMO) wireless communication systems. By exploiting the block-diagonal construction of DSTBDC, we can design a variety of high-performance DSTBDC, especially for the cases of large numbers of transmit antennas and high date rates. In flat fading channels, DSTBDC outperforms traditional differential space-time codes if the data rate is higher than 1 bps/Hz, especially when the number of transmit antennas is large. In frequency-selective fading channels, multiple-input multiple-output orthogonal frequency-division multiplexing (MIMO-OFDM) systems using DSTBDC have the powerful ability to achieve very high diversity gain in space, time, and frequency simultaneously. Due to the special orthogonal construction, DSTBDC has a simple decoding algorithm. In addition, DSTBDC can significantly save the cost of radio frequency circuits.     

SER analysis of PTS based techniques for PAPR reduction in OFDM systems

A major drawback of orthogonal frequency division multiplexing (OFDM) is high peak-to-average power ratio (PAPR). An OFDM signal with high PAPR requires power amplifier?s (PAs) with large linear operating ranges but such PAs are difficult to design and costly to manufacture. Therefore, to reduce PAPR various methods have been proposed. One of the existing technique to reduce PAPR is partial transmit sequences (PTS). The major drawback of this technique is that it requires transmission of side information (SI) with each OFDM symbol, which results in low bandwidth efficiency. It is hard to recover the side information from the OFDM signal received at the receiver.The two methods, which do not require SI to decode the OFDM symbol at the receiver, are multi-point square mapping combined with PTS (M-PTS) and concentric circle mapping based PTS (CCM-PTS). In this paper, the SER performance of PTS based methods namely CCM-PTS and M-PTS over AWGN channel is mathematically analyzed. The SER performance of CCM-PTS over AWGN is analyzed using two decoding techniques, namely minimum distance decoding and circular boundary decoding, whereas M-PTS is analyzed using minimum distance decoding. The simulation results for SER performance of CCM-PTS and M-PTS, over fading channel, have been presented using computer simulations and the SER performance of CCM-PTS by both the decoding techniques is compared with M-PTS. Also, a comparison of PAPR reduction capability and computational complexity of CCM-PTS and M-PTS has been presented. CCM-PTS method almost has the same PAPR reduction capability as M-PTS, but its SER performance is better than M-PTS and uses a simpler method to decode the data symbols.     

改进的分形矢量量化编码

为了提高图象的分形矢量量化编码效果，在利用四叉树对图象进行自适应分割的基础上，基于正交基三维分量投影准则，提出了图象块非平面近似方法，进而形成一种新的静态图象分形矢量量化编码方法。该方法首先通过对投影参数进行DPCM编码来构造粗糙图象，然后由此来构成差值图象编码的码书。由于该方法把分形和矢量量化编码结合起来，因此解码时只需查找码书，并仅进行对比度变换。计算机编、解码实验结果表明，该编码方法具有码书不需外部训练，解码也不需迭代等优点，且与其他同类编码器相比，该方法在压缩比和恢复图象质量（PSRN）方面均有明显改善。     

使用密集弱注意力机制的图像显著性检测

目的 基于全卷积网络（FCN）模型的显著性检测（SOD）的研究认为,更大的解码网络能实现比小网络更好的检测效果,导致解码阶段参数量庞大。视觉注意力机制一定程度上缓解了模型过大的问题。本文将注意力机制分为强、弱注意力两种：强注意力能为解码提供更强的先验,但风险很大;相反,弱注意力机制风险更小,但提供的先验较弱;基于此提出并验证了采用弱注意力的小型网络架构也能达到大网络的检测精度这一观点。方法 本文设计了全局显著性预测和基于弱注意力机制的边缘优化两个阶段,其核心是提出的密集弱注意力模块。它弥补了弱注意力的缺点,仅需少量额外参数,就能提供不弱于强注意力的先验信息。结果 相同的实验环境下,提出的模型在5个数据集上取得了总体上更好的检测效果。同时,提出的方法将参数量控制在69.5 MB,检测速度达到了实时32帧/s。实验结果表明,与使用强注意力的检测方法相比,提出的密集弱注意力模块使得检测模型的泛化能力更好。结论 本文目标是使用弱注意力机制来提高检测效能,为此设计了兼顾效率和风险的弱注意力模块。弱注意力机制可以提高解码特征的效率,从而压缩模型大小和加快检测速度,并在现有测试集上体现出更好的泛化能力。     

基于四元数的全速率满发射分集正交空时分组码

介绍了一种改进的4×4全速率满发射分集的正交空时分组码(Modified O-STBC)方法,其中的编码矩阵由4个2×2的Almouti编码矩阵构成,而每个Almouti编码矩阵可以看作是由一个四元数构成的,其可以表示三维空间R3中向量的旋转。对于QPSK和8PSK调制来说,调制信号的取值来自于二十面体群中的元素。该MO-STBC码在发射端可以实现全速率满发射分集,而没有引起调制星座点的增加。利用四元数的结构,接收端使用了一种计算复杂度较低的译码方法,而性能接近最大似然译码。     

采用并行分层译码的LDPC译码器设计研究

基于并行分层译码算法的LDPC译码器可以使用较小的芯片面积实现较高的译码速率。提出一种基于该算法的译码器硬件设计方法。该设计方法通过使用移位寄存器链,来进一步降低基于并行分层译码算法的译码器芯片面积。该硬件设计使用TSMC 65 nm工艺实现,并在实现中使用IEEE 802.16e中的1/2码率LDPC码。该译码器设计在迭代次数设置为10次时可实现1.2 Gb/s的译码速率,芯片面积1.1 mm2。译码器设计通过打孔产生1/2至1之间的连续码率。     

基于正交设计的多目标演化算法

提出一种基于正交设计的多目标演化算法以求解多目标优化问题(MOPs)．它的特点在于：(1)用基于正交数组的均匀搜索代替经典EA的随机性搜索,既保证了解分布的均匀性,又保证了收敛的快速性;(2)用统计优化方法繁殖后代,不仅提高了解的精度,而且加快了收敛速度;(3)实验结果表明,对于双目标的MOPs,新算法在解集分布的均匀性、多样性与解精确性及算法收敛速度等方面均优于SPEA;(4)用于求解一个带约束多目标优化工程设计问题,它得到了最好的结果——Pareto最优解,在此之前,此问题的Pareto最优解是未知的．     

基于CPLD的光栅信号解码与仿真分析

运用可编程逻辑器件,设计了光栅信号的解码方案,针对信号转向计数缺失的问题,提出了一种二次计数的修正方法,并进行了仿真验证与分析.首先简述了光栅信号的运动特征;其次根据光栅信号的变化特点,采用硬件描述语言编程(Verilog)的方法,设计了信号逻辑处理电路,包括细分辨向电路、转向识别电路与双向计数电路;最后通过仿真验证了该方案的可行性,并具体分析了解码速率.仿真结果表明,该方案实现了光栅信号的细分辨向与转向修正,最终计数值准确可靠,解码速度快,达到了设计目的.     

An efficient multiobjective differential evolution algorithm for engineering design

Solving engineering design and resources optimization via multiobjective evolutionary algorithms (MOEAs) has attracted much attention in the last few years. In this paper, an efficient multiobjective differential evolution algorithm is presented for engineering design. Our proposed approach adopts the orthogonal design method with quantization technique to generate the initial archive and evolutionary population. An archive (or secondary population) is employed to keep the nondominated solutions found and it is updated by a new relaxed form of Pareto dominance, called Pareto-adaptive ϵ-dominance (paϵ-dominance), at each generation. In addition, in order to guarantee to be the best performance produced, we propose a new hybrid selection mechanism to allow the archive solutions to take part in the generating process. To handle the constraints, a new constraint-handling method is employed, which does not need any parameters to be tuned for constraint handling. The proposed approach is tested on seven benchmark constrained problems to illustrate the capabilities of the algorithm in handling mathematically complex problems. Furthermore, four well-studied engineering design optimization problems are solved to illustrate the efficiency and applicability of the algorithm for multiobjective design optimization. Compared with Nondominated Sorting Genetic Algorithm II, one of the best MOEAs available at present, the results demonstrate that our approach is found to be statistically competitive. Moreover, the proposed approach is very efficient and is capable of yielding a wide spread of solutions with good coverage and convergence to true Pareto-optimal fronts.     

JPEG图像解码器在STM32上的应用研究

为了解决图像解码速度慢的问题,完成了基于STM32的JPEG图像解码系统的设计。以ARM处理器STM32F103ZET6作为JPEG图像的解码芯片,设计了系统的硬件电路。为了节省片内存储器的资源,对图像进行分块解码,这种方法减少了内存容量。实验结果表明:系统具有解码速度较快、效果好、稳定性高、成本低、实用性较强的特点,在数码相框、桌面电子广告牌等图像显示设备上具有较好的应用价值。     

一种改进的LLR BP译码算法研究

运用LLR BP经典算法对低密度奇偶校验(LDPC)码译码时,由于译码时迭代次数过多和每次循环时校验节点的计算复杂度过高,导致译码复杂度非常高.提出了一种改进型LLR BP译码算法,采用泰勒级数将LLR BP算法中复杂度高的雅克比修正项进行分段线性近似.仿真表明:该算法在译码性能损失不大的情况下可大幅降低LDPC码的译码复杂度.     

伺服电机正交解码器的设计与实现

正交解码器是伺服电机实现速度、位置的精确定位的重要组成部分.传统的正交解码器选用专用芯片,性能虽优异但价格昂贵且采购不易.本文提出一种以CPLD为硬件平台的正交解码器设计方案,实测性能稳定,成本低廉,软件设计灵活,为伺服电机正交解码提供了一条新的途径,供用户选择.