一种高电源抑制比带隙基准电压源的设计

采用共源共栅运算放大器作为驱动,设计了一种高电源抑制比和低温度系数的带隙基准电压源电路,并在TSMC 0.18μm CMOS工艺下,采用HSPICE进行了仿真.仿真结果表明:在-25～115℃温度范围内电路的温漂系数为9.69×10-6/℃,电源抑制比达到-100 dB,电源电压在2.5～4.5 V之间时输出电压Vref的摆动为0.2 mV,是一种有效的基准电压实现方法.     

高性能分段温度曲率补偿基准电压源设计

针对带隙基准电压源温漂高、电源抑制比(PSRR)低的问题,提出一种新颖的分段曲率补偿技术.该电路将基准源工作的全温度范围划分为3个区间,对各段温度区间进行不同的温度补偿,同时引入电流环负反馈结构,提高电路在低频时的电源抑制比,实现在-40～150℃内,温度系数为1.24×10-6,在DC时电源抑制比为-137dB.该电路采用TSMC0.6μmBCD工艺设计实现,芯片面积为0.5mm2,关断电流小于0.1μA,工作静态功耗为125μW.投片测试结果验证了电路设计的正确性,当电源电压为2.5～6.0V时,该基准源输出电压摆幅仅为0.220mV.     

低电压、高PSRR的带隙电压基准源

设计了一款高精度、低电源电压的CMOS带隙基准源,具有良好的电源抑制比。电路采用电流模结构和反馈控制实现了低电压、低功耗和高电源抑制比。基于0.25μm CMOS工艺,测试结果表明:在1V电源电压下,1KHz频率时,电源抑制比约为80dB,在0-70℃温度范围内,输出电压变化率不超过0.3%。     

CMOS带隙基准电压源电路的模拟

利用CSMC0．6μmCMOS标准工艺及OrCAD模拟电路设计软件环境,设计了2种具有曲率补偿的带隙基准电压源电路,并用Hspice对电路的温漂、电源抑制比、电源电压稳定性及电路功耗进行了仿真。仿真结果表明,第1种在-20℃～130℃温度范围内,温度系数为29．97×10^-6／℃;第2种在-20℃～130℃温度范围内,温度系数为12．73×10^-6／℃。     

一种高精度自偏置带隙基准电压源的设计

根据当前集成电路设计中对基准电压源的低功耗、高电源调整率、高电源抑制比的要求,设计了一种CMOS工艺下的高精度自偏置带隙基准电压源.该电压源由自身直流通路上的电阻来实现电压自偏置,由三级共源共栅电压偏置来实现电流匹配和电压均衡,静态电流约为13μA,具有31ppm/℃的低温度系数、22.7μV/V的高电源调整率和93.7 dB的高电源抑制比.     

一种用于电子标签芯片的基准电压源电路

文章分析了射频电子标签芯片电源的特点,根据电源低电压和低成本要求,讨论了传统的带隙基准源和全CMOS的基准电压源电路方案,设计并实现了一种适合电子标签芯片应用的全CMOS的基准电压源电路。该电路采用SMIC 0.18μm标准CMOS工艺实现,电源电压范围为1~5 V,电源敏感度为1~3%/V,输出电压的温度特性为3~20.7 ppm/℃,符合射频电子标签的设计要求。     

一种新颖自偏置带隙基准电压源的设计

基于0.6μm BCD工艺参数,设计了一种新颖的低温漂、低功耗、高电源抑制比的自偏置带隙基准电压源.电路仿真结果表明:其工作电源电压低至1.7V,输出基准电压为1.24 V,温度系数仅6.68×10-6V/℃,电流消耗22 μA,电源抑制比高达82 dB.该电压源可广泛应用于模/数、数/模转换电路和电源管理芯片中.     

高电源抑制比的CMOS带隙基准电压源

介绍了一种采用0.5 μm CMOS N阱工艺制作的带隙基准电压源电路,该电路具有高电源抑制比和较低的温度系数。通过将电源电压加到运算放大器上,运算放大器的输出电压为整个核心电路提供偏置电压,整个核心电路的偏置电压独立于电源电压,使得整个带隙基准电路具有非常高的电源抑制比。基于SPECTRE的仿真结果表明,其电源抑制比可达116 dB,在-40℃~85℃温度范围内温度系数为46 ppm/℃,功耗仅为1.45 mW,可以广泛应用于模/数转换器、数/模转换器、偏置电路等集成电路模块中。     

一种可快速启动的高PSRR带隙基准源

针对电源噪声影响图像、声音信息的传输质量,系统电源上电时间过长导致延时增大、时序紧张等问题设计了一种可快速启动的高电源抑制比的带隙基准源。通过引入负反馈回路,维持基准电压的稳定,以提升基准源的电源抑制比。设计了快速启动电路,在电源上电时通过开关管快速导通以拉高基准电压,加速了带隙基准源的启动,在基准建立好之后启动电路停止工作。基于5 V 0.35μm互补金属氧化物半导体(Complementary Metal Oxide Semiconductor, CMOS)工艺设计了基准电压源,仿真结果表明,在-40℃～125℃温度变化范围内,基准源电压变化为5.33 mV,电源抑制比在100 Hz以下达到-90.1 dB,启动时间为9μs。设计的带隙基准电压源启动速度较快,电源抑制比较高。     

高端基准电流源的设计

针对集成电路中需要多路不同基准电流的问题,设计了一种高性能的双极型基准电流源.分析了传统带隙基准源的基本原理,并对传统电流源的电路结构进行改进与优化,实现了温度补偿,大大降低了电路的温度系数,提高了电路的电源抑制比.在BL双极工艺模型下,采用HSPICE软件进行了仿真,结果表明,在-40～85℃温度范围内基准电流源的温度系数降至百万分之五每摄氏度,电源抑制比可以达到104dB,很好地实现了基准电流源低温度系数、高电源抑制比的性能.     

A band-gap voltage reference for interface circuit of microsensor

A high performance CMOS band-gap voltage reference circuit that can be used in interface integrated circuit of microsensor and compatible with 0. 6 μm ( double poly) mix process is proposed in this paper. The circuit can be employed in the range of 1. 8 - 8 V and carry out the first-order PTAT ( proportional to absolute temperature) temperature compensation. Through using a two-stage op-amp with a NMOS input pair as a negative feedback op-amp,the PSRR ( power supply rejection ratio) of the entire circuit is increased,and the temperature coefficient of reference voltage is decreased. Results from HSPICE simulation show that the PSRR is - 72. 76 dB in the condition of low-frequency,the temperature coefficient is 2. 4 × 10 -6 in the temperature range from - 10 ℃ to 90 ℃ and the power dissipation is only 14 μW when the supply voltage is 1. 8 V.     

Low-offset high-PSRR bandgap voltage reference

Based on the problem that the accuracy of the bandgap affects the performance of the integrated circuit, a novel BGR (bandgap voltage reference) is proposed. It utilizes a feedback compensation network to enhance PSRR and reduce the offset voltage, which improves the system stability and precision. Cadence spectre simulation has been done by the SMIC 018μm 1.8V CMOS process for validation. The results show that the achieved temperature coefficient is 34.6×10^-6/℃ over -30℃ to 100℃ and that the PSRR is -63.5dB at a low frequency. The power assumption is only 1.5μW. The circuit is suitable for a low-voltage low-power energy harvesting system.     

一种二阶曲率补偿的高精度带隙基准电压源

提出了一种输出电压可调的带隙基准电路．通过对双极晶体管基极-发射极电压的二阶温度补偿,大大改善了带隙基准的温度特性,并增加嵌套密勒补偿,进一步提高了系统的稳定性．基于0.6μm CMOS工艺,利用Hspice进行了仿真验证,结果表明,在-40～120℃温度范围内,0.8V基准电压的温度系数为6.1×10^-6／℃,低频时电源抑制比为-82dB,正常工作时静态工作电流小于6.5μA．     

Curvature Compensated CMOS Bandgap Reference with Novel Process Variation Calibration Technique

A lowtemperature coefficient( TC) bandgap reference( BGR) with novel process variation calibration technique is proposed in this paper. This proposed calibration technique compensating both TC and output value of BGR achieves fine adjustment step towards the reference voltage,while keeping optimal TC by utilizing large resistance to help layout match. The high-order curvature compensation realized by poly and p-diffusion resistors is introduced into the design to guarantee the temperature characteristic. Implemented in 180 nm technology,the proposed BGR has been simulated to have a power supply rejection ratio( PSRR) of 91 dB@100 Hz. The calibration technique covers output voltage scope of 0. 49 V-0. 56 Vwith TC of 9. 45 × 10~(-6)/℃-9. 56 × 10~(-6)/℃ over the temperature range of-40 ℃-120 ℃. The designed BGR provides a reference voltage of 500 mV,with measured TC of 10. 1 × 10~(-6)/℃.     

High precision voltage reference generator for 16-bit 100MS/s ADC

An output adjustable voltage reference generator for the 16-bit 100MS/s pipelined ADC is presented. An adjustable output voltage, fast-setting, high precision reference voltage buffer is designed by using current summing and floating current control techniques. In order to further improve the PSRR and reduce the output impedance, the push pull output and replica circuit structure is introduced. The prototype 16-bit 100MS/s ADC is fabricated by 0.18μm 1.8V 1P6M CMOS technology.Test results show that the voltage reference generator consumes an area of 1.3mm×2.0mm, and the power consumption is 23mW. The average temperature coefficient of the output voltage is 16×10^-6℃^-1 in the range of -55℃ to 125℃. The 16-bit 100MS/s ADC achieves the SNR of 76.3dBFS and SFDR of 89.2dBc, with 10.1MHz input at the full sampling speed, and it consumes the power of 300mW and occupies an area of 3.5mm×5.0mm.     

一种高精度低温漂带隙基准源的设计

该文参考了带隙基准电压源领域的现阶段技术,结合自偏置共源共栅电流镜以及适当的启动电路、补偿电路,设计了一种高精度、低温漂的多输出带隙基准电路。首先简述了传统带隙电压基准的基本原理,然后详细阐述了具体的各电路设计过程。该基准电压源可广泛应用于电源管理芯片等对能耗要求极高的芯片中。