On the Evolution of Remote Laboratories for Prototyping Digital Electronic Systems

The design of digital electronic systems for industrial applications can benefit in many ways from the prototyping capabilities of field-programmable gate array (FPGA) platforms. This paper presents three evolutionary releases of an FPGA-based remote laboratory and discusses the didactical and technical motivations behind each release, aiming to reduce the overhead of setting up and operate a laboratory environment where designers and students can use FPGA prototyping to validate their designs. To achieve that, a number of abstraction layers were introduced, allowing configuration and data processing in remote FPGA platforms, as well as integrating such platforms within a simulation environment. The proposed approach supported a number of projects where groups of designers and students could specify, refine, and prototype electronic systems using a pool of remotely available FPGA platforms.     

基于FPGA的ARM SoC原型验证平台设计

基于FPGA的验证平台是SoC有效的验证途径,在流片前建立一个基于FPGA的高性价比的原型验证系统已成为SoC验证的重要方法。ARM嵌入式CPU是目前广泛应用的高性价比的RISC类型CPU核,文中主要描述了以FPGA为核心的ARM SoC验证系统的设计实现过程,并对SoC设计中的FPGA验证问题进行了分析和讨论。     

基于FPGA的无线传感器网络SoC验证平台设计

基于FPGA的验证平台是SoC有效的验证途径,在流片前建立一个基于FPGA的高性价比的原型验证系统已成为SoC验证的重要方法。针对8位无线传感器网络SoC的设计要求,提出了一种高度集成化的FPGA功能验证平台。描述了以FPGA为核心的SoC验证系统的设计实现过程,并对SoC设计中的FPGA验证问题进行了分析和讨论。该验证平台结构简单,扩展灵活,提高了功能验证的效率和自动程度,缩短了开发周期,保证了SOC设计的可靠性。     

基于ARCA3 CPU的嵌入式SoC的FPGA原型验证

基于FPGA的验证是SoC功能验证的有效途径,建立一个基于FPGA的原型验证系统已成为SoC验证的重要方法.ARCA3是一种高性能、低功耗,国产的嵌入式微处理器.在ARCA3和AMBA架构上集成存储器控制器等IP核和外设,构建一个嵌入式SoC,并在FPGA上实现SoC的原型验证系统和软硬件协同验证环境.在FPGA原型机上运行Bootloader和操作系统,验证整个系统硬件的可操作性和软硬件之间的交互.基于FPGA的原型验证系统的实现可以快速验证基于ARCA3的各种抽象层次的IP核和开发基于ARCA3的软件应用.     

Hardware-accelerated design space exploration framework for communication systems

The efficient hardware implementation of signal processing algorithms requires a rigid characterization of the interdependencies between system parameters and hardware costs. Pure software simulation of bit-true implementations of algorithms with high computational complexity is prohibitive because of the excessive runtime. Therefore, we present a field-programmable gate array (FPGA) based hybrid hardware-in-the-loop design space exploration (DSE) framework combining high-level tools (e.g. MATLAB, C++) with a System-on-Chip (SoC) template mapped on FPGA-based emulation systems. This combination significantly accelerates the design process and characterization of highly optimized hardware modules. Furthermore, the approach helps to quantify the interdependencies between system parameters and hardware costs. The achievable emulation speedup using bit-true hardware modules is a key enabling the optimization of complex signal processing systems using Monte Carlo approaches which are infeasible for pure software simulation due to the large required stimuli sets. The framework supports a divide-and-conquer approach through a flexible partitioning of complex algorithms across the system resources on different layers of abstraction. This facilitates to efficiently split the design process among different teams. The presented framework comprises a generic state of the art SoC infrastructure template, a transparent communication layer including MATLAB and hardware interfaces, module wrappers and DSE facilities. The hardware template is synthesizable for a variety of FPGA-based platforms. Implementation and DSE results for two case studies from the different application fields of synthetic aperture radar image processing and interference alignment in communication systems are presented.     

Synchronization in digital system design

A unified framework and terminology is presented for synchronization design in digital systems, borrowing techniques and terminologies from digital system and digital communication design disciplines. The throughput of synchronous and asynchronous interconnect is compared, emphasizing how it is affected by interconnect delay. A discussion is presented of opportunities to apply principles long used in digital communications to the design of digital systems, with the goal of reducing the dependence on interconnect delay     

MEM-DnP—A Novel Energy Efficient Approach for Memory Integrity Detection and Protection in Embedded Systems

The pervasiveness of modern day embedded systems has led to the storing of huge amounts of sensitive information in them. These embedded devices often have to operate under insecure environments and are hence susceptible to software and physical attacks. Thus, security has been and will remain one of the prime concerns in the embedded systems. Although a lot of hardware and software techniques have been proposed to provide high levels of security, they are hampered by the trade-offs created by the design constraints in embedded systems. This paper presents a novel energy efficient approach for MEMory integrity Detection and Protection (MEM-DnP). The key feature of the proposed MEM-DnP is that it can be adaptively tuned to a memory integrity verification module by using a sensor module. This significantly reduces the energy overheads imposed on an embedded system as compared to the conventional memory integrity verification mechanisms. The simulation results show that the average energy saved in the combined detection and protection mechanism ranges from 85.5 % to 99.998 %. This is substantially higher compared to the results achieved in basecase simulations with traditional memory integrity verification techniques.     

总线功能模型在集成电路功能验证中的设计和应用

随着集成电路的设计规模不断增大，功能验证逐渐成为整个设计过程中的瓶颈。文章在对传统的验证方法进行分析的基础上，介绍了使用总线功能模型的验证方法，并对总线功能模型设计的策略和方法进行了探讨。     

Formal Verification of Analog and Mixed Signal Designs Using SPICE Circuit Simulation Traces

Analog and Mixed Signal (AMS) designs can be formally modeled as hybrid systems [45] and therefore formal verification techniques applicable to hybrid systems can be deployed to verify them. An extension to a formal verification approach applicable to hybrid systems is proposed to verify AMS designs [31]. In this approach formal verification (FV) is carried out on an AMS block using simulation traces from SPICE, a simulator widely used in the design and verification of analog and AMS blocks. A broader implication of this approach is the ability to carry out hierarchical verification using relevant simulation traces obtained at different abstraction levels of a design when modeled in appropriate platforms. This enables a seamless transition of design and verification artifacts from the highest level of abstraction to the lowest level of implementation at the transistor level of any AMS design and a resulting increase in confidence on the correctness of the final implementation. The proposed approach has been justified with its applications to different AMS design blocks. For each design, its formal model and the proposed computational techniques have been incorporated into CheckMate [11] - a FV tool for hybrid systems based on MATLAB and the Simulink/Stateflow framework from MathWorks. A further justification of the proposed approach is the resulting improvements observed in terms of reduced verification time for different specifications in each design.     

基于DSP Builder的数字滤波器设计与实现

现场可编程门阵列（FPGA）器件广泛用于数字信号处理领域,而使用VHDL或VerilogHDL语言进行设计比较复杂。提出一种采用FDATOOL工具和DSP Builder实现FIR滤波器的设计方案,按照MATLAB/Simulink/DSP Builder/QuartusII设计流程,使用FDATOOL工具可以实时调整滤波器的参数,采用DSP Builder设计了一个16阶FIR低通滤波器模型,并完成了仿真与验证,将模型转换生成VHDL代码,实现了基于FPGA的数字滤波器的设计。结果表明,该方法简单易行,易修改与移植,可满足设计要求,它验证了采用DSP Builder实现数字滤波器设计的独特优势。     

Automatic adjustment of a medical imaging data acquisition system to unknown delays in the input communication channels

In this article, novel FIFO and RAM-based Synchronization Modules to keep synchronism throughout the input channels of a Data Acquisition Electronics (DAE) system are proposed. DAE is a main component of a Medical Imaging System, namely, a Positron Emission Mammography (PEM) system. DAE input data comes from a scanner constituted by an array of scintillating crystals. The scanner captures radiation generated by human cells injected with a radioactive substance and converts it into electrical signals. The corresponding digital information is sent to the DAE. In order to deal with the huge amount of data, flowing at high data rates, point-to-point (p2p) communication channels are used between the scanner and the DAE. Propagation delays associated with the different communication channels may change differently. Additionally, differences among channel delays may exceed one clock period. Keeping synchronism in these circumstances requires more than the classical asynchronous FIFO solution. All these aspects motivate the work proposed in this article. The PEM DAE system is a multi-board, multi-FPGA, multi-clock domain system. Therefore, the DAE architecture follows a Globally Asynchronous, Locally Synchronous (GALS) design style. The novel Synchronization Modules proposed in this article are implemented in the DAE. The effectiveness of these new structures is validated through simulation and laboratorial test. Simulation and test results are presented.     

FPGA signal processing using sigma-delta modulation

FPGA devices maintain the flexibility of software-based solutions, while providing levels of performance that match, and often exceed ASIC solutions. There is a rich and expanding body of literature devoted to the efficient and effective implementation of digital signal processors using FPGA-based hardware. More often than not, the most successful of these techniques involves a paradigm shift away from the methods that provide good solutions in software programmable DSP systems. This article reports on the rich set of design opportunities that are available to the signal processing system designer through innovative combinations of ΣΔ modulation techniques and FPGA signal processing hardware. The applications considered include narrow-band filters, both single-rate and multi-rate; DC canceller; and ΣΔ modulation hybrid digital-analog control loops for simplifying carrier recovery, timing recovery, automatic gain control (AGC) loops in a digital communication receiver     

Configurable logic for digital communications: some signalprocessing perspectives

For the past two decades software programmable digital signal processors and ASICs have provided hardware solutions for signal processing system designers. A new option has become available: field programmable gate arrays. FPGA-based DSP platforms allow the designer to realize a data path that exactly matches the required processing, while at the same time maintaining the flexibility of a software approach. This article presents an overview of some FPGA DSP applications. Several filter designs are presented, and the use of CORDIC arithmetic for constructing an FPGA carrier recovery loop is outlined. In addition to presenting design examples that can be realized using present-generation devices and tools, we take a brief look at how the dynamic reconfiguration aspect of certain FPGAs could be exploited in future-generation communication technologies     

基于TotalRecall技术ASIC的FPGA原型验证

芯片设计中一个非常重要的环节是验证.随着FPGA技术的迅速发展使基于FPGA的原型验证被广泛的用于ASIC的开发过程,FPGA原型验证是ASIC有效的验证途径,但传统FPGA原型验证的可视性非常差.为了解决传统FPGA原型验证可视性的问题,验证工程师采用了结合TotalRecall技术的FPGA原型验证方法对一款鼠标芯片进行验证.获得该方法不仅能提供100％的可视性,还确保FPGA原型验证以实时硬件速度运行.该方法创新了ASIC的验证方法学.     

Constant Coefficient Multiplication Using Look-Up Tables

Multiplication is an important but expensive operation in most FPGA-based signal processing systems. Many techniques have been introduced for reducing the size and improving the speed of FPGA-based multipliers. Constant-coefficient multipliers are an important class of such multipliers that reduce FPGA resource requirements by exploiting constant-specific optimizations. This paper reviews and analyzes a constant coefficient multiplier that exploits the fine-grain memory resources of FPGAs by performing table look-up. Several optimizations to this multiplier are introduced and analyzed. This paper will also introduce several techniques for reducing the resources of this multiplier by exploiting modern FPGA architectural enhancements.     

应用TEXTIO和MATLAB进行复杂数字系统仿真

在基于FPGA的复杂数字系统的仿真测试中,设计者常常面临各种挑战.以数字图像处理系统的仿真为例,如果采用完备性仿真测试方法,那么测试矢量的数量将是非常巨大的;如果采用常规方法,不仅效率不高,而且可能无法达到仿真测试的目的.针对这个难题,提出一种进行仿真测试的新方法,该方法应用TEXTIO和MATLAB来辅助仿真测试过程,使问题得到较好的解决.以电视图像实时多目标捕获单元的仿真测试为例,全面、细致地讨论这种新方法.     

用于现代雷达系统的光波导

介绍了用于现代雷达系统的光波导的基本特性和设计考虑，包括其物理和传输性能。简介光波导的种类，讨论几种常用的光耦合技术和波导材料。指出光波导在现代雷达系统中应用的未来发展方向。     

DCT域数字水印算法的FPGA实现

提出一种基于DCT域的数字水印算法,并用FPGA硬件实现其中关键部分DCT变换。采用VHDL语言有效设计和实现DCT变换,分析与仿真结果表明:与软件实现相比,用FPGA实现水印算法具有高速实时处理的优点。因此,该设计是一种很有吸引力的硬件实现解决方案。