Air-gap-based RF coaxial TSV and its characteristic analysis

Many 3D IC applications such as MEMS and RF systems require Through-Silicon Via （TSV） with operations for high-speed vertical communication. In this paper, we introduce a novel air-gap coaxial TSV that is suiTab, for such RF applications. Firstly, the detailed fabrication process is described to explain how to acquire such a structure. Then, an Resistor Inductance Conductance Capacitance （RLGC） model is developed to profile the transverse electromagnetic field effect of the proposed air-gap TSV. The model is further verified by a 3D field solver program through the S-parameter comparison. With reference to the numerically simulated results, this analytical model delivers a maximum deviation of less than 6%0, on the conditions of varying diameters, outer to inner radius ratios, and SU-8 central angles, etc. Taking advantages of scalability of the model, a number of air-gap-based TSV designs are simulated, providing 1.6-4.0 times higher bandwidth than the con- ventional coaxial TSVs and leading to an efficient high frequency vertical RF interconnection solution for 3D ICs.     

An anisotropic thermal-stress model for through-silicon via

A two-dimensional thermal-stress model of through-silicon via (TSV) is proposed considering the anisotropic elastic property of the silicon substrate.By using the complex variable approach,the distribution of thermalstress in the substrate can be characterized more accurately.TCAD 3-D simulations are used to verify the model accuracy and well agree with analytical results (＜ ±5％).The proposed thermal-stress model can be integrated into stress-driven design flow for 3-D IC,leading to the more accurate timing analysis considering the thermal-stress effect.     

Small-signal model parameter extraction of E-mode N-polar GaN MOS-HEMT using optimization algorithms and its comparison

An improved small-signal parameter extraction technique for short channel enhancement-mode N-polar GaN MOS-HEMT is proposed,which is a combination of a conventional analytical method and optimization techniques.The extrinsic parameters such as parasitic capacitance,inductance and resistance are extracted under the pinch-off condition.The intrinsic parameters of the small-signal equivalent circuit (SSEC) have been extracted including gate forward and backward conductance.Different optimization algorithms such as PSO,Quasi Newton and Firefly optimization algorithm is applied to the extracted parameters to minimize the error between modeled and measured S-parameters.The different optimized SSEC models have been validated by comparing the S-parameters and unity current-gain with TCAD simulations and available experimental data from the literature.It is observed that the Firefly algorithm based optimization approach accurately extracts the small-signal model parameters as compared to other optimization algorithm techniques with a minimum error percentage of 1.3％.     

Gate Current Modeling and Optimal Design of Nanoscale Non-Overlapped Gate to Source/Drain MOSFET

In this paper, novel nanoscale MOSFET with Source/Drain-to-Gate Non-overlapped and high-k spacer structure has been demonstrated to reduce the gate leakage current for the first time. The gate leakage behaviour of novel MOSFET structure has been investigated with help of compact analytical model and Sentaurus Simulation. Fringing gate electric field through the dielectric spacer induces inversion layer in the non-overlap region to act as extended S/D region. It is found that optimal Source/Drain-to-Gate Non-overlapped and high-k spacer structure has reduced the gate leakage current to great extent as compared to those of an overlapped structure. Further, the proposed structure had improved off current, subthreshold slope and DIBL characteristic. It is concluded that this structure solves the problem of high leakage current without introducing the extra series resistance.     

Gate current modeling and optimal design of nanoscale non-overlapped gate to source/drain MOSFET

A novel nanoscale MOSFET with a source/drain-to-gate non-overlapped and high-k spacer structure has been demonstrated to reduce the gate leakage current for the first time.The gate leakage behaviour of the novel MOSFET structure has been investigated with the help of a compact analytical model and Sentaurus simulation. A fringing gate electric field through the dielectric spacer induces an inversion layer in the non-overlap region to act as an extended S/D(source/drain) region.It is found that an optimal source/drain-to-gate non-overlapped and high-A:spacer structure has reduced the gate leakage current to a great extent as compared to those of an overlapped structure.Further,the proposed structure had improved off current,subthreshold slope and drain induced barrier lowering(DIBL) characteristics.It is concluded that this structure solves the problem of high leakage current without introducing extra series resistance.     

一种考虑自热效应的互连线缓冲器插入优化模型

Considering the self-heating effect,an accurate expression for the global interconnection resistance per unit length in terms of interconnection wire width and spacing is presented.Based on the proposed resistance model and according to the trade-off theory,a novel optimization analytical model of delay,power dissipation and bandwidth is derived.The proposed optimal model is verified and compared based on 90 nm,65 nm and 40 nm CMOS technologies.It can be found that more optimum results can be easily obtained by the proposed model.This optimization model is more accurate and realistic than the conventional optimization models,and can be integrated into the global interconnection design of nano-scale integrated circuits.     

Modeling and Measurement of 3D Solenoid Inductor Based on Through-Silicon Vias

Through-silicon via(TSV) provides vertical interconnectivity among the stacked dies in three-dimensional integrated circuits(3D ICs) and is a promising option to minimize 3D solenoid inductors for on-chip radio-frequency applications. In this paper, a rigorous analytical inductance model of 3D solenoid inductor is proposed based on the concept of loop and partial inductance. And a series of 3D samples are fabricated on 12-in high-resistivity silicon wafer using low-cost standard CMOS-compatible ...     

Two-dimensional threshold voltage analytical model of DMG strained-silicon-on-insulator MOSFETs

For the first time,a simple and accurate two-dimensional analytical model for the surface potential variation along the channel in fully depleted dual-material gate strained-Si-on-insulator(DMG SSOI) MOSFETs is developed.We investigate the improved short channel effect(SCE),hot carrier effect(HCE),drain-induced barrier-lowering(DIBL) and carrier transport efficiency for the novel structure MOSFET.The analytical model takes into account the effects of different metal gate lengths,work functions,the drain ...     

Study of fiber laser micro-nano sensor based on colloidal crystal

A fiber laser micro-nano sensor based on colloidal crystal structure is proposed in this paper.The fiber laser has stable frequency and narrow linewidth.It is realized by using an unpumped erbium-doped fiber（EDF）as the saturable absorber.The saturable absorber possesses the shape of taper.The laser threshold can be effectively reduced by the tapered saturable absorber.The tapered fiber coated with colloidal crystal as sensing unit is studied.The concentration of ethanol can be obtained from the detection of the output laser wavelength.It can be extensively used in chemical,medical and biological detections.     

Performance Analysis of RF Spiral Inductor with Gradually Changed Metal Width and Space

To decrease the metal losses of RF spiral inductor,a novel layout structure with gradually reduced metal line width and space from outside to inside is presented.This gradual changed inductor has less eddy-current effect than the conventional inductor of fixed metal width and space.So the series resistance can be reduced and the quality (Q) factor of the inductor relating to metal losses is increased.The obtained experimental results corroborate the validity of the proposed method.For a 6nH inductor on high-resistivity silicon at 2.46GHz,Q factor of 14.25 is 11.3% higher than the conventional inductor with the same layout size.This inductor can be integrated with radio frequency integrated circuits to gain better performance in RF front end of a wireless communication system.     

一种考虑MOS效应及频变特性的类传输线型锥形TSV通孔电学模型

为准确描述锥形TSV通孔寄生电阻、电容、电感高频下MOS效应及其频变特性,本文首先推导出了锥形TSV通孔压控MOS电容的解析模型。其次基于修正后的双传输线寄生参数提取公式对锥形TSV通孔内寄生参数进行了提取。最终建立了一种考虑MOS效应及频变特性的类传输线型锥形TSV通孔电学模型。通过仿真工具验证模型精度,结果显示：在100GHz频带内模型与仿真结果吻合度较高,可以准确描述高频下锥形TSV通孔内寄生参数的半导体物理特性及频变特性,可用来预测锥形TSV通孔的电学特性,对优化三维集成电路电学性能有一定指导意义。     

使用传输线理论的硅通孔电参数提取方法

针对三维集成电路中的关键技术硅通孔的电特性,使用传输线理论提取了其单位长度RL-GC参数。将硅通孔等效为传输线,利用HFSS仿真结果并结合传输线理论给出了具体的参数提取方法。计算结果表明,硅通孔单位长度RLGC 参数呈现较强的频变特性,当频率从1 MHz增加到20 GHz时,单位长度的电阻和导纳分别从0.45 mΩ/μm和2.5μS/μm增加到2.5 mΩ/μm和17μS/μm,而单位长度电感和电容分别从8.7 pH/μm和8.8 fF/μm减小至7.5 pH/μm和0.2 fF/μm。与传统的阻抗矩阵和导纳矩阵提取方法相比,该方法具有结果绝对收敛和适用频率高等诸多优点,可进一步应用于三维集成电路的仿真设计。     

Improved transmission line model for high-frequency modelling of through silicon vias

Accurate and reliable models can support Through Silicon Via (TSV) testing methods and improve the quality of 3D ICs. A model for expressing resistance and inductance of TSVs at frequencies up to 50 GHz is proposed. It is based on the two-parallel transmission cylindrical wires model, known also as the Transmission Line Model and improved through the fitting to ANSYS Q3D simulation results. The proximity effect between neighbouring TSVs that alters the paths through which current flows is empowered at high frequencies. The consideration of the dependence of the proximity effect on frequency for calculating TSV resistance and inductance is the main contribution of this work. Additionally, the modelling of resistance is extended to accurately correspond to a TSV in an array. The proposed models are in good agreement with the simulator results with an average error below 2% and 5.4% for the resistance and the inductance, respectively. The maximum error is 3% and 9.1%, respectively. In the case of the resistance of a TSV in an array, the maximum error is 4.7%. As long as the coefficients of the proposed equations have been extracted, the time for resistance and inductance calculation based on the presented models is negligible, compared to the time-consuming EM simulation.     

Simulation of lossy package transmission lines using extracted data from one-port TDR measurements and nonphysical RLGC models

In this paper, the frequency-dependent characteristic impedance and propagation constant of lossy transmission lines have been extracted from one-port time-domain reflectometry (TDR) measurements. Nonphysical resistance (R), inductance (L), conductance (G) and capacitance (C) (RLGC) models have been developed for simulating lossy transmission lines using the extracted data. The extraction method has been demonstrated for transmission lines on an organic substrate such as coplanar lines. Using the extracted data and nonphysical RLGC models, the simulation results show good correlation with TDR measurements for coplanar lines.     

Scaling trends of power noise in 3-D ICs

Power supply noise in three-dimensional integrated circuits (3-D ICs) considering scaled CMOS and through silicon via (TSV) technologies is the focus of this paper. A TSV and inductance aware cell-based 3-D power network model is proposed and evaluated. Constant TSV aspect ratio and constant TSV area penalty scaling, as two scenarios of TSV technology scaling, are discussed. A comparison of power noise among via-first, via-middle, and via-last TSV technologies with CMOS scaling is also presented. When the TSV technology is a primary bottleneck in high performance 3-D ICs, an increasing TSV area penalty should be adopted to produce lower power noise. As a promising TSV technology, via-middle TSVs are shown to produce the lowest power noise with CMOS technology scaling.     

基于环形振荡器的TSV故障非接触测试方法

为避免传统的探针检测对硅通孔(TSV)造成损伤的风险,提出了一种非损伤的TSV测试方法.用TSV作为负载,通过环形振荡器测量振荡周期.TSV缺陷造成电阻电容参数的变化,导致振荡周期的变化.通过测量这些变化可以检测TSV故障,同时对TSV故障的不同位置引起的周期变化进行了研究与分析,利用最小二乘法拟合出通过周期来判断故障位置的曲线,同时提出预测模型推断故障电阻范围.测试结构是基于45 nm PTM COMS工艺的HSPICE进行设计与模拟,模拟结果表明,与同类方法相比,此方法在测试分辨故障的基础上对TSV不同位置的故障进行分析和判断,并能推断故障电阻范围.     

三维集成电路中硅通孔缺陷建模及自测试/修复方法研究

硅通孔(Through Silicon Via, TSV)是3维集成电路(3D IC)进行垂直互连的关键技术,而绝缘层短路缺陷和凸点开路缺陷是TSV两种常见的失效形式。该文针对以上两种典型缺陷建立了TSV缺陷模型,研究了侧壁电阻及凸点电阻与TSV尺寸之间的关系,并提出了一种基于TSV缺陷电阻端电压的检测方法。同时,设计了一种可同时检测以上两种缺陷的自测试电路验证所提方法,该自测试电路还可以级联起来完成片内修复功能。通过分析面积开销可得,自测试/修复电路在3D IC中所占比例随CMOS/TSV工艺尺寸减小而减小,随TSV阵列规模增大而减小。     

一种基于TSV和激光刻蚀辅助互连的改进型CIS封装

提出了一种基于硅通孔(TSV)和激光刻蚀辅助互连的改进型CMOS图像传感器(CIS)圆片级封装方法.对CIS芯片电极背部引出的关键工艺,如锥形TSV形成、TSV绝缘隔离、重布线(RDL)等进行了研究.采用低温电感耦合等离子体增强型化学气相淀积(ICPECVD)的方法实现TSV内绝缘隔离;采用激光刻蚀开口和RDL方法实现CIS电极的背部引出;通过采用铝电极电镀镍层的方法解决了激光刻蚀工艺中聚合物溢出影响互连的问题,提高了互连可靠性.对锥形TSV刻蚀参数进行了优化.最终在4英寸(1英寸=2.54 cm)硅/玻璃键合圆片上实现了含有276个电极的CIS圆片级封装.电性能测试结果表明,CIS圆片级封装具有良好的互连导电性,两个相邻电极间平均电阻值约为7.6Ω.     

Characterization of Co-Planar Silicon Transmission Lines With and Without Slow-Wave Effect

Co-planar lines on silicon substrates with and without slow-wave effect are characterized using time-domain reflectometry (TDR) and vector network analyzer (VNA) measurements, and simulated using a proposed nonphysical resistance-inductance-conductance-capacitance (RLGC) model. The silicon co-planar lines are characterized based on comparison to package transmission lines. Co-planar silicon lines without slow-wave mode are modeled in the same way as package transmission lines, but co-planar lines with slow-wave mode are modeled in a different way from package transmission lines. Hence, a nonphysical RLGC model including slow-wave mode is proposed along with the extraction method from VNA measurements. Simulation results correlate well with time- and frequency-domain measurements for the co-planar silicon lines.