基于LabVIEW的模拟滤波器电路测试方法的研究

介绍基于图形化编程语言LabVIEW设计的测量模拟滤波器电路的方法。相比传统的模拟滤波器电路的测试系统,本文提出的测试方法功能强、速度快,不仅可以测量滤波器电路的幅频特性,还可以测量相位信息,该系统在测试精度上可以代替传统的频谱分析仪进行模拟滤波器电路的测量。     

高频锁相环的可测性设计

边界扫描是数字电路常用的测试技术，基于IEEE1149．1标准的边界扫描技术对一款CMOS高频锁相环进行了可测性设计，该锁相环最高工作频率达GHz。详细讨论了最高输出频率、输出频率范围和锁定时间参数的测试方案，给出了详细的测试电路和测试方法。对应用该测试方案的锁相环电路增加测试电路前后的电路网表进行了Hspice仿真，仿真结果证明该方法能有效测量锁相环的参数，并且对原锁相环电路的功能影响很小。该测试方法可广泛用于高频锁相环的性能评测和生产测试。     

一种程控实现任意行选的红外焦平面读出电路

设计了一种可应用于多光谱红外光谱仪的红外焦平面读出集成电路。电路可以选择任意连续或非连续行的积分信号进行读出而无须逐行读出,从而大大增加了系统的灵活性和帧频。同时,电路采用滚动式IWR工作模式,为此根据读出单元是否有积分开关设计了两种复位积分控制模块;单元内部可采用DI,CTIA等读出结构。此电路具有明确的工程应用价值。     

EMI滤波器插入损耗的精准测量方案及实验研究

简要介绍了共模、差模及非对称的测试电路,但都无法精准测量 EMI 滤波器的插入损耗。因此提出一种基于共差模分离器的测量电路,来精准测量插入损耗,并进行了实验验证及分析。该方案弥补了GB/T 7343-2017中测试方法的不足,并为滤波器内部电路存在的漏感现象、分布参数等对插入损耗的影响提供了测量方法。     

电阻偏差的测试

介绍了一种电阻标称值与实际值的偏差测量电路。该测试方法简单,精度较高,可用于电阻器生产或应用测试。     

一种适合于SOC系统的JTAG扩展化可测性设计

随着集成电路系统复杂性的提高及基于 IP核的 SOC系统的出现 ,电路测试的难度不断增大 ,对电路可测性设计提出了更高的要求。文中在研究了现有各种可测性设计方法优劣后提出了扩展化的 JTAG可测性设计电路 ,它在稍增加电路复杂度的情况下融合各测试方法 ,并提出了利用这种测试电路的 IC系统测试方案。它克服了测试基于 IP核的 SOC系统的一些难点。     

电阻偏差的测试

介绍了一种电阻标称值与实际值的偏差测量电路。该测试方法简单,精度较高,可用于电阻器生产或应用测试。     

一种基于OTDR技术的插回损测试仪

与传统连续波(CW)测量方法相比,基于OTDR技术的回波损耗测试方法,能够准确定位反射事件,测量结果直观、准确,在一定条件下还能够一次测量多个器件以及实现免缠绕测试。介绍了基于OTDR技术的回波损耗测量原理,设计了一种基于OTDR技术的回波损耗测量和插入损耗测量一体化测试仪。     

高精度数据采集电路设计及通道交叉干扰分析

为满足多路远距离电流信号高精度采样的需求,设计了一种基于FPGA的高精度多通道数据采集存储电路。分析了测量电路各模块误差产生的原因,用电路等效理论推导了多通道采集时通道间交叉干扰引入的测量误差,从设计角度出发,提出了减小误差提高测量精度的方法。对设计的多通道采集电路进行了多次测试实验,测试结果表明,采集电路可实现对8路4~20mA电流信号高精度采集测量,测量精度优于0.1%。     

一种测量反激变压器磁损的检测方法

阐述反激变换器中的变压器磁芯损耗一直是损耗分析和测量的难点。仿真软件没有考虑到Steinmetz参数会随频率增加而变化，而理论计算难以求解磁芯内部的磁感应强度分布。提出一种基于直流法磁损测试方法的改进型测试电路结构，使其能够对反激变换器在连续模式（CCM）和断续模式(DCM)下的变压器磁损进行测量。所提出的测试电路及方法具有简单、准确度高等优点。在损耗测量中，基于等效原则，得到测试电路固有损耗，从电路工作状态和器件温度两方面验证了测试电路工作状态的一致性，从而得到准确的待测磁元件的磁性损耗。测量反激变压器磁芯在CCM和DCM工作状态的损耗，与仿真结果和iWcSE模型进行了对比与分析，分析仿真和iWcSE模型与磁芯损耗实测值的误差。     

Testing System Based on Virtual Instrument for Readout Circuit of Infrared Focal Plane Array

Readout integrated circuit（ROIC） is one of the most important components for hybrid-integrated infrared focal plane array（IRFPA）. And it should be tested to ensure the product yield before bonding. This paper presents an on-wafer testing system based on Labview for ROIC of IRFPA. The quantitative measurement can be conducted after determining whether there is row crosstalk or not in this system. This low-cost system has the benefits of easy expansion, upgrading, and flexibility, and it has been employed in the testing of several kinds of IRFPA ROICs to measure the parameters of saturated output voltage, nonuniformity, dark noise and dynamic range, etc.     

传输线参数测试方法研究

传统的传输线参数测试方法是终端开路、短路测试。对于高压输电线路,终端直接短路时,短路电流较大,对电力设备有损害。本文提出了在线路正常运行时利用全球定位系统（GPS）提供的时间为基准,对传输线两端的电压、电流进行同步采样和测量。根据牛顿—拉夫逊法对传输线方程进行迭代计算可以得到传输线参数。通过Matlab仿真计算验证了该方法是有效的。     

一种具有积分电容复用功能的红外读出电路设计

为提高长波红外探测器的电荷处理能力,提出了一种积分电容复用技术。该技术将读出电路阵列分为奇偶行两个部分,使奇偶行像素分开进行积分读出。当所有的奇行像素积分时,所有的偶行像素均不进行积分。奇行像素复用偶行像素的积分电容,奇行像素积分结束后按行列顺序依次读出。同样地,当所有偶行像素积分时,奇行像素不进行积分,偶行像素复用奇行像素的电容,积分完成后偶行像素按顺序读出。相比于使用叠层电容来提高电荷处理能力的方法,积分电容复用技术更加有效且不受工艺限制。仿真结果表明,积分电容复用技术可将像素的等效积分电容提升至原来的2倍,使读出电路的电荷处理能力从20 Me^-提升至40 Me^-。     

Fault Detection of Analog Circuits Using Network Parameters

A new method to detect component faults in analog circuits is proposed in this paper. Network parameters like driving point impedance, transfer impedance, voltage gain and current gain are used to detect component faults in analog circuits as these network parameters are sensitive to the components of the circuit. Using montecarlo simulation each component of the circuit is varied within its tolerance limit and the minimum and the maximum values of each network parameter are found for fault free circuit. At the time of testing, the network parameters are found for the injected fault and if any one or more network parameters is exceeding its predetermined bound limits then the circuit is confirmed faulty. The proposed method is validated through second order Sallenkey band pass filter and fourth order Chebyshev low pass filter circuits. Numerical results are presented to clarify the proposed method and prove its efficiency.     

A decomposition approach for testing large analog networks

This article presents an efficient method for testing large scale analog and mixed mode networks. Test equations are derived for a partitioned network from Krichhoff current law equations at the partition points. Voltages at the partition points are used to identify network parameters. The method has applications to circuit modeling, fault diagnosis, testing and calibration. The conventional testing methods for dynamic, nonlinear networks are based on the sensitivity approach, which uses incremental changes in voltages to estimate changes in network parameters. However, this conventional approach cannot handle large scale circuits because the sensitivity matrix is dense. This results in enormous requirements for memory space and computing time when the circuit size becomes large. The new method overcomes these deficiencies of the sensitivity approach. In this article, we introduce the decomposition method, describe its basic features and its algorithm, and compare this method with a conventional, sensitivity technique using testing network examples.This work was supported in part by the National Institute of Standards and Technology, U.S. Department of Commerce, Under Grant No. 70NANBGH0662.     

单片式彩色LCOS微显芯片电路设计

介绍一种单片式彩色LCOS微显芯片的电路设计。这种LCOS芯片配置合适的光机及电路系统可用于单片式LCOS彩色背投电视或其它投影产品。与传统场序彩色LCOS微显芯片类似，该芯片的主要模块由行扫描驱动器、数据驱动器和象素驱动矩阵三大部分组成。不同的是二者的行寻址方式不同，传统场序彩色LCOS采用的是逐行扫描法，而此处介绍的彩色LCOS采用的是随机寻址方式，将红、绿、蓝三种数据几乎同时写入象素矩阵，配合滚动的光照显示彩色图像。单片式LCOS系统与三片式LCOS系统相比可以节省微显芯片及配套电路系统数目，从而大大节约成本，在背投电视和其他投影产品产业中有很大的实用价值。     

一种精确测量AC-DC电源管理类芯片的方法

对于AC-DC电路测试,圆片测试(CP)一般采用开环测试的方法,测试项目较少,从而使CP的测试时间大大减少,提高了测试效率以及测试产能。CP测试的目的是测试基准电压以及输出波形等参数,并对相应参数进行工艺上的修调,使得这些参数达到中心值,保证芯片基本功能的准确;但CP测试并不是应用环境下的芯片状态,所以当AC-DC电路进行成品测试(FT)的时候,通过模拟芯片的应用环境来测试芯片在应用端的参数,从而确保芯片在工作环境中能正常应用,达到检测芯片的目的。主要介绍了AC-DC电路在闭环应用环境下各项参数的测试方法,确保电路功能的稳定性以及可靠性。     

通用数字电路板测试系统硬件设计

针对传统依靠人工使用示波器、万用表、逻辑分析仪等设备对数字电路板进行测试具有过程复杂、工作量大、可靠性低等缺点,介绍一套通用数字电路板测试系统的硬件设计方案。跟传统数字电路板测试系统相比,文中的设计性能参数更优,主要包括:测试频率最高50 MHz并可调为100 MHz的整数分频;测试电平兼容-6~+9 V且可编程步长为100 mV;测试通道32路,每通道可设为输入输出三态可选且同步工作,存储深度1 Mbit,电流驱动能力达50 mA并有过载保护。     

Application of source biasing technique for energy efficient DECODER circuit design: memory array application

Researchers have proposed many circuit techniques to reduce leakage power dissipation in memory cells.If we want to reduce the overall power in the memory system,we have to work on the input circuitry of memory architecture i.e.row and column decoder.In this research work,low leakage power with a high speed row and column decoder for memory array application is designed and four new techniques are proposed.In this work,the comparison of cluster DECODER,body bias DECODER,source bias DECODER,and source coupling DECODER are designed and analyzed for memory array application.Simulation is performed for the comparative analysis of different DECODER design parameters at 180 nm GPDK technology file using the CADENCE tool.Simulation results show that the proposed source bias DECODER circuit technique decreases the leakage current by 99.92％ and static energy by 99.92％ at a supply voltage of 1.2 V.The proposed circuit also improves dynamic power dissipation by 5.69％,dynamic PDP/EDP 65.03％ and delay 57.25％ at 1.2 V supply voltage.     

Multiple fault analog circuit testing by sensitivity analysis

Analog circuit testing is considered to be a very difficult task. This difficulty is mainly due to the lack of fault models and accessibility to internal nodes. To overcome this problem, an approach is presented for analog circuit modeling and testing. The circuit modeling is based on first-order sensitivity computation. The testability of the circuit is analyzed by the multiple-fault model and by functional testing. Component deviations are deduced by measuring a number of output parameters, and through sensitivity analysis and tolerance computation. Using this approach, adequate tests are identified for testing catastrophic and soft faults. Some experimental results are presented for simple models as well as multiple-fault models.