Generation and Detection of Terahertz Waves Using Low‐Temperature‐Grown GaAs with an Annealing Process

In this letter, we present low‐temperature grown GaAs (LTG‐GaAs)‐based photoconductive antennas for the generation and detection of terahertz (THz) waves. The growth of LTG‐GaAs and the annealing temperatures are systematically discussed based on the material characteristics and the properties of THz emission and detection. The optimum annealing temperature depends on the growth temperature, which turns out to be 540°C to 580°C for the initial excess arsenic density of to .     

Accurate Tunable‐Gain 1/x Circuit Using Capacitor Charging Scheme

This paper proposes an accurate tunable‐gain 1/x circuit. The output voltage of the 1/x circuit is generated by using a capacitor charging time that is inversely proportional to the input voltage. The output voltage is independent of the process parameters, because the output voltage depends on the ratios of the capacitors, resistors, and current mirrors. The voltage gain of the 1/x circuit is tuned by a 10‐bit digital code. The 1/x circuit was fabricated using a 0.18 μm CMOS process. Its core area is , and it consumes 278 μW at and . Its error is within 1.7% at to 1 V.     

Non‐resonant Element in Slotted Ground Plane for Multiband Antenna Operation

New ways of achieving small, multiband, multifunctional, and standard solutions for mobile handset antennas are demanded in the current wireless market. A non‐resonant element of , a matching network, and a slotted ground plane are proposed to satisfy mobile market demands that require multiband operation and small antenna solutions. The main advantage of the proposed design is that with only one non‐resonant element of considerably small size (0.015λ, 900 MHz), the handset is capable of providing operation at mobile bands.     

Design Space Exploration for NoC‐Style Bus Networks

With the number of IP cores in a multicore system‐on‐chip increasing to up to tens or hundreds, the role of on‐chip interconnection networks is vital. We propose a networks‐on‐chip‐style bus network as a compromise and redefine the exploration problem to find the best IP tiling patterns and communication path combinations. Before solving the problem, we estimate the time complexity and validate the infeasibility of the solution. To reduce the time complexity, we propose two fast exploration algorithms and develop a program to implement these algorithms. The program is executed for several experiments, and the exploration time is reduced to approximately 1/22 and 7/1,200 at the first and second steps of the exploration process, respectively. However, as a trade‐off for the time saving, the time cost (TC) of the searched architecture is increased to up to and , respectively, at each step compared with that of the architecture obtained through full‐case exploration. The reduction ratio can be decreased to 1/4,000 by simultaneously applying both the algorithms even though the resulting TC is increased to up to when compared with that obtained through full‐case exploration.     

New Time‐Domain Decoder for Correcting both Errors and Erasures of Reed‐Solomon Codes

A new time‐domain decoder for Reed‐Solomon (RS) codes is proposed. Because this decoder can correct both errors and erasures without computing the erasure locator, errata locator, or errata evaluator polynomials, the computational complexity can be substantially reduced. Herein, to demonstrate this benefit, complexity comparisons between the proposed decoder and the Truong‐Jeng‐Hung and Lin‐Costello decoders are presented. These comparisons show that the proposed decoder consistently has lower computational requirements when correcting all combinations of ν errors and μ erasures than both of the related decoders under the condition of , where d_min denotes the minimum distance of the RS code. Finally, the (255, 223) and (63, 39) RS codes are used as examples for complexity comparisons under the upper bounded condition of . To decode the two RS codes, the new decoder can save about 40% additions and multiplications when as compared with the two related decoders. Furthermore, it can also save 50% of the required inverses for .     

Supercapacitive Properties of Composite Electrode Consisting of Activated Carbon and Di(1‐aminopyrene)quinone

Di(1‐aminopyrene)quinone (DAQ) as a quinone‐containing conducting additive is synthesized from a solution reaction of 1‐aminopyrene and hydroquinone. To utilize the conductive property of DAQ and its compatibility with activated carbon, a composite electrode for a supercapacitor is also prepared by blending activated carbon and DAQ (3:1 w/w), and its supercapacitive properties are characterized based on the cyclic voltammetry and galvanostatic charge/discharge. As a result, the composite electrode adopting DAQ exhibits superior electrochemical properties, such as a higher specific capacitance of up to at , an excellent high‐rate capability of up to , and a higher cycling stability with a capacitance retention ratio of 82% for the 1,000th cycle.     

Adaptive Calibration Method in Multiport Amplifier for K‐Band Payload Applications

This letter proposes a novel calibration method for a multiport amplifier (MPA) to achieve optimum port‐to‐port isolation by correcting both the amplitude and phase of the calibration signals. The proposed architecture allows for the detection of the phase error and amplitude error in each RF signal path simultaneously and can enhance the calibrated resolution by controlling the analog phase shifters and attenuators. The designed and MPAs show isolation characteristics of 30 dB and 27 dB over a frequency range of 19.5 GHz to 22.5 GHz, respectively.     

Compact Triple‐Band Monopole Antenna for WLAN/WiMAX‐Band USB Dongle Applications

A miniaturized triple‐band antenna suitable for wireless USB dongle applications is proposed and investigated in this paper. The presented antenna, simply consisting of a circular‐arc‐shaped stub, an L‐shaped stub, a microstrip feed line, and a rectangular ground plane has a compact size of and is capable of generating three separate resonant modes with very good impedance matching. The measurement results show that the antenna has several impedance bandwidths for of 260 MHz (2.24 GHz to 2.5 GHz), 320 MHz (3.4 GHz to 3.72 GHz), and 990 MHz (5.1 GHz to 6.09 GHz), which can be applied to both 2.4/5.2/5.8 GHz WLAN bands and 3.5/5.5 GHz WiMAX bands. Moreover, nearly‐omni‐directional radiation patterns and stable gain across the operating bands can be obtained.     

Efficient Computation of Eta Pairing over Binary Field with Vandermonde Matrix

This paper provides an efficient algorithm for computing the η_T pairing on supersingular elliptic curves over fields of characteristic two. In the proposed algorithm, we deploy a modified multiplication in using the Vandermonde matrix. For , the proposed multiplication method computes β · F · G instead of F · G with some because β is eliminated by the final exponentiation of the η_T pairing computation. The proposed multiplication method asymptotically requires only 7 multiplications in as n → ∞, while the cost of the previously fastest Karatsuba method is 9 multiplications in . Consequently, the cost of the η_T pairing computation is reduced by 14.3%.     

Highly Simplified and Bandwidth‐Efficient Human Body Communications Based on IEEE 802.15.6 WBAN Standard

This paper presents a transmission method for improving human body communications in terms of spectral efficiency, and the performances of bit‐error‐rate (BER) and frame synchronization, with a highly simplified structure. Compared to the conventional frequency selective digital transmission supporting IEEE standard 802.15.6 for wireless body area networks, the proposed scheme improves the spectral efficiency from 0.25 bps/Hz to 1 bps/Hz based on the 3‐dB bandwidth of the transmit spectral mask, and the signal‐to‐noise‐ratio (SNR) by 0.51 dB at a BER of with an reduction in the detection complexity of the length of the Hamming distance computation. The proposed preamble structure using its customized detection algorithm achieves perfect frame synchronization at the SNR of a BER of by applying the proposed pre‐processing to compensate for the distortions on the preamble signals due to the band‐limit effects by transmit and receive filters.     

Real‐Time Locomotion Mode Recognition Employing Correlation Feature Analysis Using EMG Pattern

This paper presents a new locomotion mode recognition method based on a transformed correlation feature analysis using an electromyography (EMG) pattern. Each movement is recognized using six weighted subcorrelation filters, which are applied to the correlation feature analysis through the use of six time‐domain features. The proposed method has a high recognition rate because it reflects the importance of the different features according to the movements and thereby enables one to recognize real‐time EMG patterns, owing to the rapid execution of the correlation feature analysis. The experiment results show that the discriminating power of the proposed method is 85.89% when walking on a level surface, 96.47% when going up stairs, and 96.37% when going down stairs for given normal movement data. This makes its accuracy and stability better than that found for the principal component analysis and linear discriminant analysis methods.     

Simplified Bilayer White Phosphorescent Organic Light‐Emitting Diodes

We report on highly efficient blue, orange, and white phosphorescent organic light‐emitting diodes consisting only two organic layers. Hole transporting 4, 4,’ 4”‐tris (N‐carbazolyl)triphenylamine (TcTa) and electron transporting 2‐(diphenylphosphoryl) spirofluorene (SPPO1) are used as an emitting host for orange light‐emitting bis(3‐benzothiazol‐2‐yl‐9‐ethyl‐9H‐carbazolato) (acetoacetonate) iridium ((btc)2(acac)Ir) and blue light‐emitting iridium(III)bis(4,6‐difluorophenyl‐pyridinato‐N,C2’) picolinate (FIrpic) dopant, respectively. Combining these two orange and blue light‐emitting layers, we successfully demonstrate highly efficient white PHOLEDs while maintaining Commission internationale de l'éclairage coordinates of (, ). Accordingly, we achieve a maximum external quantum, current, and power efficiencies of 12.9%, 30.3 cd/A, and 30.0 lm/W without out‐coupling enhancement.     

Design of Multi‐time Programmable Memory for PMICs

In this paper, a multi‐time programmable (MTP) cell based on a 0.18 μm bipolar‐CMOS‐DMOS backbone process that can be written into by using dual pumping voltages — VPP (boosted voltage) and VNN (negative voltage) — is used to design MTP memories without high voltage devices. The used MTP cell consists of a control gate (CG) capacitor, a TG_SENSE transistor, and a select transistor. To reduce the MTP cell size, the tunnel gate (TG) oxide and sense transistor are merged into a single TG_SENSE transistor; only two p‐wells are used — one for the TG_SENSE and sense transistors and the other for the CG capacitor; moreover, only one deep n‐well is used for the 256‐bit MTP cell array. In addition, a three‐stage voltage level translator, a VNN charge pump, and a VNN precharge circuit are newly proposed to secure the reliability of 5 V devices. Also, a dual memory structure, which is separated into a designer memory area of and a user memory area of , is newly proposed in this paper.     

Surface Micromachined Pressure Sensor with Internal Substrate Vacuum Cavity

A surface micromachined piezoresistive pressure sensor with a novel internal substrate vacuum cavity was developed. The proposed internal substrate vacuum cavity is formed by selectively etching the silicon substrate under the sensing diaphragm. For the proposed cavity, a new fabrication process including a cavity side‐wall formation, dry isotropic cavity etching, and cavity vacuum sealing was developed that is fully CMOS‐compatible, low in cost, and reliable. The sensitivity of the fabricated pressure sensors is 2.80 mV/V/bar and 3.46 mV/V/bar for a rectangular and circular diaphragm, respectively, and the linearity is and for these two diaphragms. The temperature coefficient of the resistances of the polysilicon piezoresistor is to per degree of Celsius according to the sensor design. The temperature coefficient of the offset voltage at 1 atm is 0.0019 mV and 0.0051 mV per degree of Celsius for a rectangular and circular diaphragm, respectively. The measurement results demonstrate the feasibility of the proposed pressure sensor as a highly sensitive circuit‐integrated pressure sensor.     

Pseudo Optical PAM‐N Signal Using Externally Modulated Lasers

We propose a pseudo optical N‐level pulse‐amplitude modulation (PO PAM‐N) signal using a few externally‐modulated lasers (EMLs) operating at different wavelengths, which is suitable for upgrading the transmission speed over an optical link of ＜ 10 km single‐mode fiber with low‐cost components. To compare a PO PAM‐N signal with that of a standard optical PAM‐N signal, we perform experiments for evaluating the performance of a 51.56‐Gb/s PO PAM‐4 signal and standard 51.56‐Gb/s optical PAM‐4 signal. The receiver sensitivity (at ) of the PO PAM‐4 signal is 1.5 dB better than the receiver sensitivity of a standard optical PAM‐4 signal. We also investigate the feasibility of PO PAM‐N signals operating at 103.12 Gb/s, considering relative intensity noise, timing jitter, extinction ratio (ER) of EMLs, and dispersion. From the results, a PO PAM‐8 signal performs better than PO PAM‐4 and PO PAM‐16 signals at 103.12 Gb/s. Finally, we suggest a timing control method to suppress the effect of dispersion in a PO PAM‐N signal. We show that the tolerance to dispersion of a 103.12‐Gb/s PO PAM‐8 signal can be improved to ±40 ps/nm by applying a proposed scheme.     

Implementation of Real‐Time Post‐Processing for High‐Quality Stereo Vision

We propose a novel post‐processing algorithm and its very‐large‐scale integration architecture that simultaneously uses the passive and active stereo vision information to improve the reliability of the three‐dimensional disparity in a hybrid stereo vision system. The proposed architecture consists of four steps — left‐right consistency checking, semi‐2D hole filling, a tiny adaptive variance checking, and a 2D weighted median filter. The experimental results show that the error rate of the proposed algorithm (5.77%) is less than that of a raw disparity (10.12%) for a real‐world camera image having a resolution and maximum disparity of 256. Moreover, for the famous Middlebury stereo image sets, the proposed algorithm's error rate (8.30%) is also less than that of the raw disparity (13.7%). The proposed architecture is implemented on a single commercial field‐programmable gate array using only 13.01% of slice resources, which achieves a rate of 60 fps for stereo images with a disparity range of 256.     

Low‐Power Channel‐Adaptive Reconfigurable 4×4 QRM‐MLD MIMO Detector

This paper presents a low‐complexity channel‐adaptive reconfigurable QR‐decomposition and M‐algorithm‐based maximum likelihood detection (QRM‐MLD) multiple‐input and multiple‐output (MIMO) detector. Two novel design approaches for low‐power QRM‐MLD hardware are proposed in this work. First, an approximate survivor metric (ASM) generation technique is presented to achieve considerable computational complexity reduction with minor BER degradation. A reconfigurable QRM‐MLD MIMO detector (where the M‐value represents the number of survival branches in a stage) for dynamically adapting to time‐varying channels is also proposed in this work. The proposed reconfigurable QRM‐MLD MIMO detector is implemented using a Samsung 65 nm CMOS process. The experimental results show that our ASM‐based QRM‐MLD MIMO detector shows a maximum throughput of 288 Mbps with a normalized power efficiency of 10.18 Mbps/mW in the case of MIMO with 64‐QAM. Under time‐varying channel conditions, the proposed reconfigurable MIMO detector also achieves average power savings of up to 35% while maintaining a required BER performance.     

Constructions and Properties of General (k,n) Block‐Based Progressive Visual Cryptography

Recently, Hou and others introduced a (2, n) block‐based progressive visual cryptographic scheme (BPVCS) in which image blocks can be gradually recovered step by step. In Hou and others’ (2, n)‐BPVCS, a secret image is subdivided into n non‐overlapping image blocks. When participants stack their shadow images, all the image blocks associated with these t participants will be recovered. However, Hou and others’ scheme is only a simple 2‐out‐of‐n case. In this paper, we discuss a general (k, n)‐BPVCS for any k and n. Our main contribution is to give two constructions (Construction 1 and Construction 2) of this general (k, n)‐BPVCS. Also, we theoretically prove that both constructions satisfy a threshold property and progressive recovery of the proposed (k, n)‐BPVCS. For , Construction 1 is reduced to Hou and others’ (2, n)‐BPVCS.]     

Transparent OLED Lighting Panel Design Using Two‐Dimensional OLED Circuit Modeling

In this work, we develop a simulation method to predict a two‐dimensional luminance distribution method using a circuitry simulation. Based on the simulation results, we successfully fabricate large area transparent organic light‐emitting diode panels with high luminance uniformity.     

Design of SCR‐Based ESD Protection Circuit for 3.3 V I/O and 20 V Power Clamp

In this paper, MOS‐triggered silicon‐controlled rectifier (SCR)–based electrostatic discharge (ESD) protection circuits for mobile application in 3.3 V I/O and SCR‐based ESD protection circuits with floating diffusion regions for inverter and light‐emitting diode driver applications in 20 V power clamps were designed. The breakdown voltage is induced by a grounded‐gate NMOS (ggNMOS) in the MOS‐triggered SCR‐based ESD protection circuit for 3.3 V I/O. This lowers the breakdown voltage of the SCR by providing a trigger current to the P‐well of the SCR. However, the operation resistance is increased compared to SCR, because additional diffusion regions increase the overall resistance of the protection circuit. To overcome this problem, the number of ggNMOS fingers was increased. The ESD protection circuit for the power clamp application at 20 V had a breakdown voltage of 23 V; the product of a high holding voltage by the floating diffusion region. The trigger voltage was improved by the partial insertion of a P‐body to narrow the gap between the trigger and holding voltages. The ESD protection circuits for low‐ and high‐voltage applications were designed using 0.18 µm Bipolar‐CMOS‐DMOS technology, with 100 µm width. Electrical characteristics and robustness are analyzed by a transmission line pulse measurement and an ESD pulse generator (ESS‐6008).