28 nm超薄体FD-SOI高温特性研究

研究了低阈值电压(LVT)结构的28 nm超薄体全耗尽绝缘体上硅(FD-SOI)MOSFET的高温下特性。在300 ℃下对器件进行测试,将FD-SOI与部分耗尽(PD)SOI进行参数对比。结合理论分析,证明了高温下超薄体FD-SOI具有比PD-SOI更低的阈值电压漂移率和亚阈值摆幅。在300 ℃高温下工作时,SOI MOSFET的参数发生退化,阈值电压减小,泄漏电流增加,栅极对沟道电流的控制能力大大减小。超薄体FD-SOI的设计可使器件的高温性能更加稳定,将电路的工作温度提高到300 ℃。     

不同偏置条件下CMOS SRAM的总剂量辐射效应

对1Mb静态随机存取存储器(SRAM)进行了不同偏置条件下的总剂量辐照效应研究.结果表明,试验选取的CMOS SRAM器件为总剂量辐射敏感器件,辐照偏置条件对器件的电参数退化和功能失效有较大影响.在三种偏置条件中,静态加电为最劣偏置,其次是工作状态,浮空状态时器件的辐射损伤最小.在工作状态和静态加电两种偏置条件下,静态功耗电流的退化与器件功能失效密切相关,可作为器件功能失效的预警量.     

体Si和SOI工艺SRAM芯片电磁敏感度的温度效应

考虑到芯片实际应用环境的复杂性,针对体硅(silicon, Si)和绝缘体上硅(silicon on insulator, SOI)两种工艺的静态随机存储器(static random-access memory, SRAM),测试研究温度效应分别对这两种不同工艺存储器芯片敏感度的影响. 依据两种工艺下金属氧化物半导体(metal oxide semiconductor, MOS)器件结构的异同,对两种工艺下MOS器件的温度效应进行了对比分析;结合温箱和直接功率注入法(direct power injection, DPI)的测试设备,搭建了一个可用于评估温度和电磁干扰(electromagnetic interference, EMI)共同作用到SRAM的测试平台. 通过理论与试验研究发现随着温度的升高,两款不同工艺的SRAM存储器芯片敏感度阈值都会增加,且在100 MHz之后SOI工艺的敏感度阈值增加普遍大于体Si工艺,这对于SOI和体Si工艺集成电路在高低温环境下电磁兼容性的研究具有一定意义.     

静态随机存取存储器漏电流功耗降低技术

分析了静态随机存取存储器 (SRAM) 的漏电流,总结了目前业界所用的各种降低漏电流的技术,包括衬底偏压、源极偏压、双电源电压、字线电压反偏和位线电压浮动结构.它们都是通过改变SRAM各个端点的电压来实现的,在降低漏电流的同时,对SRAM器件性能也有一定的影响.基于UMC 55 nm CMOS工艺,对几种方案进行了仿真,并在理论分析的基础上,指出未来发展的趋势.     

65nm SRAM传统静态指标的测试方案及研究

65 nm及其以下工艺,工艺波动对SRAM性能影响越来越大.SRAM读写噪声容限能够反映SRAM性能的好坏,对于预测SRAM良率有着重要的作用.采用一种新型测试结构测量SRAM读写噪声容限(即SRAM传统静态指标),该测试结构能够测量65 nm SRAM在保持、读、写三种操作下的指标:Hold SNM,RSNM,N-c...     

SRAM存储器动态参数测试向量分析

半导体存储器一般由存储体、地址译码驱动器、读/写放大器和控制电路组成,是一种能存储大量信息的器件,它是由许多存储单元组成的。半导体存储器的测试有功能测试、直流参数测试、交流参数测试,而功能测试和交流参数测试对存储器来说是至关重要的。SRAM(静态随机存储器)的功能测试是通过算法图形发生器产生不同的测试图形,对被测器件各个不同存储单位进行读写操作,以检查其功能。主要讲述了SRAM交流参数测试原理及其测试关键技术,介绍了SRAM交流参数测试的故障模型。通过研究SRAM交流参数测试图形向量,给出了SRAM交流参数测试图形向量的优化方法。     

基于FPGA的COTS器件辐射效应测试系统

为了满足航天商业现货(COTS)器件辐射效应评估的高效率、低成本、批量测试需求,通过分析典型COTS器件不同辐射效应测试的异同,设计了COTS器件通用辐射效应测试系统。测试系统由面向仪器系统的外围组件互连(PCI)扩展(PXI)系统和基于现场可编程门阵列(FPGA)的监测主板组成,适用于FPGA、模数转换器(ADC)、静态随机存储器(SRAM)、运算放大器、电源芯片等典型COTS器件单粒子和总剂量效应地面模拟试验,能够在线实时测量被测器件的功耗电流、逻辑功能、输出信号等参数,可对被测器件的输入电压、输入电流、输出电压等需要高精度测量的功能性能参数进行离线测量。通过典型器件的单粒子与总剂量效应试验,对测试系统的在线与离线测试功能进行了验证,结果表明该测试系统能够满足测试需求。     

东芝开发出可以使低功耗微控制器从深度休眠模式快速唤醒的极低泄漏SRAM

正东芝公司近日宣布,该公司已经开发出适用于低功耗微控制器备用RAM的极低泄漏65纳米静态随机存储器(SRAM),它可以实现从深度休眠模式快速唤醒。东芝已经开发了一种泄漏率低于传统SRAM千分之一的极低泄漏SRAM,当采用65纳米工艺时每比特泄露电流为27fA。这一水平低于采用65纳米以上技术制造的SRAM的已发布数据。这种新的SRAM充电一次便可以在备用存储器(容     

PDSOI静态随机存储器的总剂量辐照加固

对PDSOI CMOS 器件及电路进行总剂量辐照的加固势必会引起其性能下降,这就需要在器件及电路加固和其性能之间进行折中.从工艺集成的角度,对PDSOI CMOS器件和电路的总剂量辐照敏感区域:正栅氧化层、场区氧化层及埋氧层提出了折中的方法.采用此种方法研制了抗总剂量辐照PDSOI SRAM ,进行总剂量为2×105 rad(Si)的辐照后SRAM的各项功能测试均通过,静态电流的变化满足设计要求,取数时间:辐照前为26.3 ns;辐照后仅为26.7 ns.     

不同规模SRAM辐射损伤效应的研究

通过对ETC公司的商用256 kb和1 Mb CMOS SRAM器件在不同偏置条件(包括静态偏置和动态读写偏置)下进行电离辐射效应的研究,获得了SRAM器件电气参数和功能出错数随总剂量的响应关系.实验结果表明,功耗电流随累积剂量的增加变化明显,可以作为表征SRAM辐射损伤的敏感参数,但功能出错数与功耗电流的变化不同步,与功耗电流没有必然联系,原因是功能出错主要由栅氧阈值电压负漂引起,而功耗电流的增加主要由栅氧和场氧阈值电压负漂造成的漏电引起.     

Area efficient layout design of CMOS circuit for high-density ICs

Efficient layouts have been an active area of research to accommodate the greater number of devices fabricated on a given chip area. In this work a new layout of CMOS circuit is proposed, with an aim to improve its electrical performance and reduce the chip area consumed. The study shows that the design of CMOS circuit and SRAM cells comprising tapered body reduced source fully depleted silicon on insulator (TBRS FD-SOI)-based n- and p-type MOS devices. The proposed TBRS FD-SOI n- and p-MOSFET exhibits lower sub-threshold slope and higher I_on to I_off ratio when compared with FD-SOI MOSFET and FinFET technology. Other parameters like power dissipation, delay time and signal-to-noise margin of CMOS inverter circuits show improvement when compared with available inverter designs. The above device design is used in 6-T SRAM cell so as to see the effect of proposed layout on high density integrated circuits (ICs). The SNM obtained from the proposed SRAM cell is 565 mV which is much better than any other SRAM cell designed at 50 nm gate length MOS device. The Sentaurus TCAD device simulator is used to design the proposed MOS structure.     

High-speed reduced-leakage SRAM memory cell design techniques for low-power 65 nm FD-SOI/SON CMOS technology

The paper presents a detailed study on the sub-1 V high speed operation with reduced leakage design techniques for conventional 6T Static Random Access Memory (SRAM) on fully depleted Silicon-on Insulator (FD-SOI) and fully depleted Silicon-on-Nothing (FD-SON) technology. Performance of SON MOSFET is found to be significantly better both in terms of power and speed from its equivalent SOI device. Future devices with advanced technology are promising for low-power application. The most promising high-speed, low-power operation techniques are introduced, analyzed and compared into 65 nm low-power FD-SOI/SON technology. Hspice simulations conclude Drive Source Line (DSL) architecture as the best option for high speed operation in sub 100 nm technology without affecting the Static Noise Margin (SNM) of the cells.     

Reliability of the doping concentration in an ultra-thin body and buried oxide silicon on insulator (SOI) and comparison with a partially depleted SOI

This study compares the reliability of nMOSFETs with low- and high-doped ultra-thin body and buried oxide (UTBB) with fully depleted (FD) and partially depleted (PD) silicon on insulator (SOI). The high-doped devices display lower off-current leakage performance but more degradation in both hot-carrier stress (HCS) and positive bias temperature instability (PBTI) test at both room temperature and elevated temperature compared with the low-doped devices. The PBTI test indicates that the high-doped devices induce high tunneling leakage and that the degradation is highly associated with temperature. The degradation stabilizes with an increase in stress time. The thinner PD-SOI demonstrates low variation at the threshold voltage and low drive current under HCS. The FD-SOI has better drain leakage control than the PD-SOI.     

辐照加固SRAM型FPGA总剂量辐射效应研究

在航天辐射环境中,电离辐射产生的辐射效应会对电子元器件性能产生影响。文章对自主研发的SRAM型FPGA芯片在60Co-γ源辐照下的总剂量辐射效应进行了研究。实验表明:(1)总剂量累积到一定程度后功耗电流线性增大,但只要功耗电流在极限范围内,FPGA仍能正常工作;(2)SRAM型FPGA在配置过程中需要瞬间大电流,故辐照后不能立即配置;(3)总剂量辐照实验时,功耗电流能直观反映器件随总剂量的变化关系,可作为判断器件失效的一个敏感参数。该研究为FPGA的设计提供了基础。     

Linearity and low-noise performance of SOI MOSFETs for RFapplications

The MOSFET parameters important for RF application at GHz frequencies: a) transition frequency, b) noise figure, and c) linearity are analyzed and correlated with substrate type. This work demonstrates that, without process changes, high-resistivity silicon-on-insulator (high-ρ SOI) substrates can successfully enhance the RF performance of on-chip inductors and fully depleted (FD)-SOI devices in terms of reducing substrate losses and parasitics. The linearity limitations of the SOI low-breakdown voltage and "kink" effect are addressed by judicious device and circuit design. Criteria for device optimization are derived. A NF = 1.7 dB at 2.5 GHz for a 0.25 μm FD-SOI low-noise amplifier (LNA) on high-ρ SOI substrate obtained the lowest noise figure for applications in the L and S-bands     

A forward body-biased low-leakage SRAM cache: device, circuit and architecture considerations

This paper presents a forward body-biasing (FBB) technique for active and standby leakage power reduction in cache memories. Unlike previous low-leakage SRAM approaches, we include device level optimization into the design. We utilize super high Vt (threshold voltage) devices to suppress the cache leakage power, while dynamically FBB only the selected SRAM cells for fast operation. In order to build a super high Vt device, the two-dimensional (2-D) halo doping profile was optimized considering various nanoscale leakage mechanisms. The transition latency and energy overhead associated with FBB was minimized by waking up the SRAM cells ahead of the access and exploiting the general cache access pattern. The combined device-circuit-architecture level techniques offer 64% total leakage reduction and 7.3% improvement in bit line delay compared to a previous state-of-the-art low-leakage SRAM technique. Static noise margin of the proposed SRAM cell is comparable to conventional SRAM cells.     

SiC电力电子器件对电力系统的影响

宽禁带SiC材料被认为是高性能电力电子器件的理想材料,比较了Si和SiC材料的电力电子器件在击穿电场强度、稳定性和开关速度等方面的区别,着重分析了以SiC器件为功率开关的电力电子装置对电力系统中柔性交流输电系统(FACTS)、高压直流输电(HVDC)装置、新能源技术和微电网技术领域的影响。分析表明,SiC电力电子器件具有耐高压、耐高温、开关频率高、损耗小、动态性能优良等特点,在较高电压等级(高于3 kV)或对电力电子装置性能有更高要求的场合,具有良好的应用前景。     

Temperature dependent study of carbon-doped InP/InGaAs HBT's

We report on a temperature dependent study of the dc and the microwave performance of carbon-doped InP/In_0.53Ga_0.47 As heterojunction bipolar transistors (HBT's). The turn on voltage increased 114% and the dc current gain decreased 25% as the temperature was reduced from 300 K to 33 K. Under high-current injection, there was a 29% increase in the current gain cutoff frequency of these devices as the temperature was lowered from 300 K to 77 K. By investigating the operation of HBT's at cryogenic temperatures, increased understanding of the mechanisms of carrier transport in these devices can be obtained, and this may lead to improvements in device performance     

总剂量辐照加固的PDSOI CMOS 64k静态随机存储器

在国内首次使得1.2μm部分耗尽SOI 64k静态随机存储器的抗总剂量能力达到了1×106 rad(Si),其使用了SIMOX晶圆. 在-55～125℃范围内,该存储器的数据读取时间几乎不变.在经过剂量为1×106 rad(Si)的总剂量辐照后,该存储器的数据读取时间也几乎不变,静态功耗仅从辐照前的0.65μA变化为辐照后的0.8mA,远远低于规定的10mA指标;动态功耗仅从辐照前的33mA变化为辐照后的38.1mA,远远低于规定的100mA指标.