Hybrid Nanoparticle/Organic Devices with Strong Resonant Tunneling Behaviors

A hybrid nanoparticle/organic device consisting of small molecule organic semiconductors and Ag nanoparticles is reported. The single device exhibits unusual properties of organic resonant tunneling diode (ORTD) at low driving voltage region and offers light emission at high voltage. For ORTD, a strong negative differential resistance behavior is demonstrated at room temperature. The current resonance with the peak‐to‐valley current ratio of over 4.6 and narrow linewidth of only ～1.4 V is achieved. A detailed operating mechanism of the charging and emission modes is proposed, which can be discussed in terms of the strong charge‐trapping effect of Ag nanoparticles. The repeatable operations of hybrid device show the mutual influences between two modes and the light emission properties of the ORTD are also discussed.     

700-V asymmetrical 4H-SiC gate turn-off thyristors (GTO's)

Silicon Carbide (4H-SiC), asymmetrical gate turn-off thyristors (GTO's) were fabricated and tested with respect to forward voltage drop (V_F), forward blocking voltage, and turn-off characteristics. Devices were tested from room temperature to 350°C in the dc mode. Forward blocking voltages ranged from 600-800 V at room temperature for the devices tested. V_F of a typical device at 350°C was 4.8 V at a current density of 500 A/cm². Turn-off time was less than 1 μs. Although no beveling or advanced edge termination techniques were used, the blocking voltage represented approximately 50% of the theoretical value when tested in an air ambient. Also, four GTO cells were connected in parallel to demonstrate 600-V, 1.4 A (800 A/cm ²) performance     

Vertical organic-inorganic hybrid transparent oxide TFTs gated by biodegradable electric-double-layer biopolymer

Vertical organic-inorganic hybrid oxide-based electric-double-layer (EDL) thin-film transistors (TFTs) are successfully demonstrated. Low-cost biodegradable chitosan biopolymer is proposed as an efficient EDL electrolyte dielectric in such vertical transparent TFTs. The device is completely transparent in the range of visible light and the whole fabrication process is completed at room temperature. It exhibits a good performance with a large output current of ∼8 mA/cm², a large current on/off ratio of ∼10⁵, a small subthreshold swing of 0.33 V/dec, and a low operation voltage of only 2 V, respectively. Moreover, an energy band diagram based on vertical EDL modulation is proposed to understand the device mechanism. Such vertical organic-inorganic hybrid transistor with a vertical channel may be very promising for some important applications in the state-of-the-art low-cost portable transparent flexible electronics.     

Memory performance of a thin-film device based on a conjugated copolymer containing fluorene and chelated europium complex

A memory device based on the sandwiched structure of a conjugated copolymer (PF8Eu), containing fluorene and chelated europium complex, has been fabricated. An electrical bistability phenomenon was observed on this device: low conductivity state for the as-fabricated device and high conductivity state after device transition by applying a voltage of /spl sim/3 V. At the low conductivity state, the device showed a charge injection controlled current and at the high conductivity state, the device showed a space charge limited current. At the same applied voltage, the device exhibited two distinguishable conductivities with an ON/OFF current ratio as high as 10/sup 6/ at room temperature. After transition to the high conductivity state, the device tended to remain in the high conductivity state even when the applied voltage was removed. Thus, the device is a potential write-once-read-many-times memory device.     

高频4H-SiC双极晶体管的研制

研制出国内第一个高频4H-SiC双极晶体管.该器件采用了双台面结构和叉指结构,室温下的最大直流电流增益(β)为3.25,集电结击穿电压BVCBO达200 V.器件的β随温度的升高而降低,具有负的温度系数,这种特性使该器件容易并联,避免出现热失控现象.器件的高频特性由矢量网络分析仪测量得到,截止频率.fT为360 MHz、最高振荡频率fmax为160 MHz.     

Sub-half-micrometer width 2-D MESFET

Two-dimensional (2-D) MESFET's having sub-half-micron channel widths have been fabricated on double-δ-doped Al_0.24Ga _0.76As/In_0.18Ga_0.82As/GaAs heterostructures. The 2-D MESFET operates like a normal transistor at room temperature but uses very few electrons in the channel (about 500 at peak current and 5 at threshold). Also, the Narrow Channel Effect (NCE) and Drain-Induced Barrier Lowering (DIBL) (two effects which limit the minimum power operation in conventional devices) have been practically eliminated. The 0.4 micron wide device had an ON/OFF current ratio of 10⁵, a peak transconductance of 100 mS/mm, a threshold voltage of 0.3 V, a saturation voltage of 0.2 V, and a subthreshold ideality factor of 1.1. The 2-D MESFET DCFL inverter had a switching voltage and noise margin of 0.35 V and 0.26 V, respectively, at 0.8 V supply. These room temperature results suggest that the 2-D MESFET is an excellent candidate for future low power digital electronics applications     

1200V大容量SiC MOSFET器件研制

采用平面栅MOSFET器件结构,结合优化终端场限环设计、栅极bus-bar设计、JFET注入设计以及栅氧工艺技术,基于自主碳化硅工艺加工平台,研制了1200V大容量SiC MOSFET器件.测试结果表明,器件栅极击穿电压大于55V,并且实现了较低的栅氧界面态密度.室温下,器件阈值电压为2.7V,单芯片电流输出能力达到50A,器件最大击穿电压达到1600V.在175℃下,器件阈值电压漂移量小于0.8V;栅极偏置20V下,泄漏电流小于45nA.研制器件显示出优良的电学特性,具备高温大电流SiC芯片领域的应用潜力.     

2700V4H-SiC结势垒肖特基二极管

在76.2 mm 4H-SiC晶圆上采用厚外延技术和器件制作工艺研制的结势垒肖特基二极管(JBS).在室温下,器件反向耐压达到2700 V.正向开启电压为0.8V,在VF=2V时正向电流密度122 A/cm2,比导通电阻Ron=8.8 mΩ·cm2.得到肖特基接触势垒qφв=1.24 eV,理想因子n=1.     

Substrate current measurements in thin SOI MOSFET's at 300 and 77 K

Measurements of impact-ionized hole current in fully depleted SOI (silicon-on-insulator) MOSFETs at room temperature and liquid nitrogen temperature are reported. The measured current exhibits properties similar to those of the substrate current in bulk transistors, except for higher drain biases when the parasitic bipolar in the device is significant. Since the body contact is effective in collecting only a small fraction of the total generated hole current, the body contact cannot be used to eliminate the bipolar action in thin SOI, at least for channel widths on the order of 10 μm     

Hot-electron-induced interface state generation in n-channel MOSFET's at 77 K

Hot-electron-induced degradation in n-channel Si MOSFET's as a result of stress voltages applied at 77 K was studied. The devices were stressed at 77 K for 48 h with a drain voltage of 5 V and a gate voltage corresponding to that at which maximum substrate current was measured. Comparison of pre-stress and post-stress electrical characteristics for forward and for inverse mode operation at room temperature and at 77 K indicate that the observed degradation was due to the generation of hot-electron-induced acceptor interface states at the drain end of the device approximately 0.09 eV below the Si conduction band edge. No trapped charge resulting from hot-electron injection into the gate oxide was observed. The charge associated with the filled interface states had no observable effect on effective channel electron mobility at room temperature, and reduced that at 77 K by no more than 25 percent of the pre-stress value. Operation of CMOS inverters in either logic state (OFF, ON) resulted in no degradation of either device. Operation in a switching mode at 77 K did result in degradation of the n-channel device but not the p-channel FET. The observed degradation is thought to be correlated with the substrate current generated during the switching transient.     

1000-V, 30-A 4H-SiC BJTs with high current gain

This paper presents the development of 1000 V, 30A bipolar junction transistor (BJT) with high dc current gain in 4H-SiC. BJT devices with an active area of 3/spl times/3 mm/sup 2/ showed a forward on-current of 30 A, which corresponds to a current density of 333 A/cm/sup 2/, at a forward voltage drop of 2 V. A common-emitter current gain of 40, along with a low specific on-resistance of 6.0m/spl Omega//spl middot/cm/sup 2/ was observed at room temperature. These results show significant improvement over state-of-the-art. High temperature current-voltage characteristics were also performed on the large-area bipolar junction transistor device. A collector current of 10A is observed at V/sub CE/=2 V and I/sub B/=600 mA at 225/spl deg/C. The on-resistance increases to 22.5 m/spl Omega//spl middot/cm/sup 2/ at higher temperatures, while the dc current gain decreases to 30 at 275/spl deg/C. A sharp avalanche behavior was observed at a collector voltage of 1000 V. Inductive switching measurements at room temperature with a power supply voltage of 500 V show fast switching with a turn-off time of about 60 ns and a turn-on time of 32 ns, which is a result of the low resistance in the base.     

A new "mixed-mode" reliability degradation mechanism in advanced Si and SiGe bipolar transistors

A new mixed-mode base current degradation mechanism is identified in bipolar transistors for the first time, which, at room temperature, induces a large I/sub B/ leakage current only after simultaneous application of both high J/sub C/ and high V/sub CB/. This new mechanism differs fundamentally from well-known I/sub B/ degradation mechanisms such as the reverse EB voltage stress, high forward current stress and damage due to ionizing radiation. Extensive measurements and two-dimensional (2-D) simulations have been used to help understand the device physics associated with this new degradation mechanism.     

Optoelectronic devices based on lateral p-n junctions fabricated bymolecular-beam epitaxy growth of silicon-doped GaAs on patterned(311)A-oriented substrates

We demonstrate light-emitting diodes, a vertical-cavity surface-emitting laser (VCSEL), and a photodiode fabricated using a lateral p-n junction. The lateral p-n junction is formed in a GaAs-silicon doped layer grown by molecular-beam epitaxy on a patterned GaAs (311)A-oriented substrate. Lateral p-n junctions have particular properties (i.e., small junction area, coplanar contact geometry, can be clad between electrically insulating layers, allow carrier transport in the plane of multilayer structures, etc.) that are promising for application in new devices. Light-emitting diodes exhibit good electroluminescence at room temperature for both GaAs single layers and GaAs-AlGaAs multiple-quantum-well structures. The VCSEL has electrically insulating distributed Bragg reflectors and coplanar contacts which simplify the device fabrication process. Pulsed-mode operation at room temperature was obtained with a threshold current of 2.3 mA. The light-emission spectrum has a single peak at 942 nm with a full-width at half-maximum of 0.15 nm. The photodiode design allows a reduction of the junction capacitance and an increase of the response speed. A nonoptimized device exhibited a time constant of 10 ps     

A nonvolatile semiconductor memory device in 6H-SiC for harsh environment applications

An electrically erasable programmable read-only memory (EEPROM) cell fabricated on a 6H-SiC substrate is reported. It is the first fully functional SiC EEPROM device. This device uses a generic double-polysilicon-gate configuration. It has been tested at both room temperature and elevated temperatures, up to 200/spl deg/C, to demonstrate full programmability. The threshold voltage shifts between programmed and erased states, at all tested temperatures, are larger than 4.5 V. In both states, the device functions satisfactorily as an n-type MOSFET. Charge retention time is more than 24 h at room temperature.     

Monolithic integrated resonant tunneling diode and heterostructure junction field effect transistor circuits

We have developed a simple technology for monolithic integration of resonant tunneling diodes (RTDs) and heterostructure junction-modulated field effect transistors (HJFETs). We have achieved good device performance with this technology: HJFETs had transconductances of 290 mS/mm and current densities of 310 mA/mm for a 1.5 μm gate length; RTDs had room temperature peak to valley ratios greater than 20:1 with current densities of 42 kA/cm². With this technology, we have demonstrated a monolithically integrated RTD + HJFET state holding circuit that can serve as a building block circuit for self-timed logic units. This circuit is resistor-free and operates at room temperature. The state holding circuit showed large noise margins of 1.21 V and 0.71 V, respectively, for input low and input high, for a 1.7 V input voltage swing. We have examined the transient response of the circuit and investigated the effect of circuit design parameters on propagation delay. We identify the RTD valley current as the limiting factor on propagation delay. We discuss the suitability of RTD + HJFET circuits such as our state holding circuit for highly dense integrated circuits.     

Properties of selectively doped heterostructure transistors incorporating a superlattice donor layer

We report on some salient features of an improved structure of selectively doped heterostructure transistor (SDHT) incorporating a short-period (30 Å) Al0.6Ga0.4As/n-GaAs superlattice donor layer. We show that this superlattice-SDHT (S²DHT) structure is a good candidate for both low-temperature packaged operation and room temperature applications. In addition to eliminating drain I-V distortion at low temperature, the device shows a threshold voltage shift from 300 K to 77 K of only ∼50 mV. The device also has high transconductance (∼250 mS/mm for 1-µm gate lengths at room temperature), larger voltage swing, and higher current driving capability than conventional SDHT's.     

Linear Cascade GaN-Based Green Light-Emitting Diodes With Invariant High-Speed/Power Performance Under High-Temperature Operation

We demonstrate the performance of linear cascade green light-emitting diode (LED) arrays suited for use in plastic optical fiber (POF) communications in automobiles or harsh environments. With this three-LED array, driven by the constant voltage bias of an in-car battery output (12 V) we obtain high-speed ($sim$100-Mb/s eye-opening), high-coupling power (0.9 mW), and a very small variation of coupled power versus temperature [$-$ 0.12%$^{circ}hbox{C}^{-1}$ at room temperature (RT)] for the whole measured temperature range (i.e., RT to 120 $^{circ}$ C). Even under high bias current (100 mA) operation, our device can sustain a clear 150-Mb/s eye-opening from RT to 120 $^{circ}$C. The static and dynamic measurement results indicate that the speed and power performance of this device are less sensitive to variations in ambient temperature than are those of the red resonant-cavity LEDs utilized for POF communication.      

Three-terminal silicon surface junction tunneling device for roomtemperature operation

This letter reports excellent negative differential conductance (NDC) characteristics at room temperature in a three-terminal silicon surface junction tunneling (Si SJT) device, with the peak-to-valley current ratio of more than two. The tunneling device was fabricated on a SIMOX wafer to achieve an extremely small bulk leakage current together with a sharp drain impurity profile. In addition, a ring-shaped gate structure was employed to eliminate the effect of the field oxide corner, resulting in the significant reduction of an excess tunneling current at the tunneling junction. As a simple circuit demonstration, gate-controlled latch characteristics are also shown, which cannot be easily achieved by a two-terminal tunneling device     

A 40 nm gate length n-MOSFET

Forty nm gate length n-MOSFETs with ultra-shallow source and drain junctions of around 10 nm are fabricated for the first time. In order to fabricate such small geometry MOSFETs, two special techniques have been adopted. One is a resist thinning technique using isotropic oxygen plasma ashing for the fabrication of 40 nm gate electrodes. The other is a solid phase diffusion technique from phosphorus doped silicated glass (PSG) for the fabrication of 10 nm source and drain junctions. The resulting 40 mm gate length n-MOSFETs operate quite normally at room temperature. Using these n-MOSFETs, we investigated short channel effects and current drivability in the 40 nm region at room temperature. We have also investigated hot-carrier related phenomena in the 40-nm region. Results indicate that the impact ionization rate increases slightly as the gate length is reduced to around 40 nm, and that both impact ionization rate and substrate current fall significantly as V/sub d/ falls below 1.5 V. This demonstrates that reliability as regards degradation due to hot carriers is not a serious problem even in the 40 mm region if V/sub d/ is less than or equal to 1.5 V.<>     

1 µm MOSFET VLSI technology: Part IV—Hot-electron design constraints

An approach is described for determining the hot-electron-limited voltages for silicon MOSFET's of small dimensions. The approach was followed in determining the room-temperature and the 77 K hot-electron-limited voltages for a device designed to have a minimum channel length of 1 µm. The substrate hot-electron limits were determined empirically from measurements of the emission probabilities as a function of voltage using devices of reentrant geometry. The channel hot-electron limits were determined empirically from measurements of the injection current as a function of voltage and from long-term stress experiments. For the 1 µm design considered, the channel hot-electron limits are lower than the substrate hot-electron limits. The maximum voltage,V_{DS} = V_{GS}, is 4.75 V at room temperature (25°C) and 3.5 V at 77 K. More details of the voltage limits as well as the approach for determining them are discussed. Examples of circuits designed with these devices to operate within these hot-electron voltage limits are also discussed.