SystemQ: Bridging the gap between queuing-based performance evaluation and SystemC

During early design phases performance evaluation becomes increasingly important since major system-level decisions, such as the allocation of hardware resources and the partitioning of functionality onto architecture building blocks, affect the quality of the design significantly. Quantitative analysis is hard to achieve due to growing complexities, heterogeneity, and concurrency of modern embedded systems. We propose the use of multiclass queuing networks during the specification phase of the design flow for modeling data-flow oriented systems. Starting from an executable high-level queuing model our evaluation framework SystemQ¹ enables successive and systematic refinement of behavior and structure towards established TLM and RTL models based on SystemC. We demonstrate why SystemQ’s multiclass queuing networks are a natural and feasible abstraction for evaluating network processing platforms. In particular we reveal the impact of scheduling policies on the Quality-of-Service, such as the residence time of network traffic in the system. In our case study, we show how stepwise refinement can reduce memory and latency bounds by up to two orders of magnitude and how the choice of only one queuing discipline can affect these properties. The investigated simulation models run in the range of 1 : 100 to 1 : 1 of real-time on a common off-the-shelf Linux PC.     

基于SystemC的时钟周期精确交易级建模及通信细化

交易级建模通过提高建模抽象层次,加快了系统建模和仿真的速度。针对AMBA AHB协议,采用Sys-temC语言,进行了交易级建模及通信细化。结果表明,由于抽象层次部分结合了BCA(bus cycle-accurate)级描述,使得到的交易级模型包含了更多时间/协议信息,同时保留了速度优势,有利于前期验证和系统开发。而之后进行的通信细化,将抽象通道转化为模块实体和端口,对于最终RTL级实现具有重要意义。     

RTL DFT Techniques to Enhance Defect Coverage for Functional Test Sequences

Functional test sequences are often used in manufacturing testing to target defects that are not detected by structural test. However, they suffer from low defect coverage since they are mostly derived in practice from existing design-verification test sequences. Therefore, there is a need to increase their effectiveness using design-for-testability (DFT) techniques. We present a DFT method that uses the register-transfer level (RTL) output deviations metric to select observation points for an RTL design and a given functional test sequence. Simulation results for six ITC′99 circuits show that the proposed method outperforms two baseline methods for several gate-level coverage metrics, including stuck-at, transition, bridging, and gate-equivalent fault coverage. Moreover, by inserting a small subset of all possible observation points using the proposed method, significant fault coverage increase is obtained for all benchmark circuits.     

Fault simulation of linear analog circuits

Research in the areas of analog circuit fault simulation and test generation has not achieved the same degree of success as its digital counterpart owing to the difficulty in modeling the more complex analog behavior. This article presents a novel approach to this problem by mapping the good and faulty circuits to thediscrete Z-domain. An efficient fault simulation is then performed on this discretized circuit for the given input test wave form. This simulator provides an order of magnitude speedup over traditional circuit simulators. An efficient fault simulator and the formulation of analog fault models opens up the ground for analog automatic test generation.     

Defect Simulation Methodology for iDDT Testing

The International Technology Roadmap for Semiconductors (ITRS) identifies two main challenges associated with the testing of manufactured ICs. First, the increase in complexity of semiconductor manufacturing process, physical properties of new materials, and the constraints imposed by resolution of lithography techniques etc., give rise to more complex failure mechanisms and hard-to-model defects that can no longer be abstracted using traditional fault models. Majority of defects, in today's technology, include resistive bridging and open defects with diverse electrical characteristics. Consequently, conventional fault models, and tools based on these models are becoming inadequate in addressing defects resulting from new failure mechanisms. Second, the defect detection resolution of main-stream I_DDQ testing is challenged by significant elevation in off-state quiescent current and process variability in newer technologies. Overcoming these challenges demands innovative test solutions that are based on realistic fault models capable of targeting real defects and thus, providing high defect coverage. In prior works power supply transient current or i_DDT testing has been shown to detect resistive bridging and open defects. The ability of transient currents to detect resistive opens and their insensitivity (virtually) to increase in static leakage current make i_DDT testing all the more attractive. However, in order to integrate i_DDT based methods into production test flows, it is necessary to develop a fault simulation strategy to assess the defect detection capability of test patterns and facilitate the ATPG process. The analog nature of the test observable, i.e., i_DDT signals, entail compute intensive transient simulations that are prohibitive. In this work, we propose a practical fault simulation model that partitions the task of simulating the DUT (device under test) into linear and non-linear components, comprising of power/ground-grid and core-logic, respectively. Using divide-and-conquer strategy, this model replaces the transient simulations of power/ground-grid with simple convolution operations utilizing its impulse response characteristics. We propose a path isolation strategy for core-logic as a means of reducing the computational complexity involved in deriving i_DDT signals in the non-linear portion. The methodology based on impulse response functions and isolated path simulation, can enable i_DDT fault simulation without having to simulate the entire DUT. To our knowledge, no practical technique exists to perform fault simulation for i_DDT based methods. The proposed fault simulation model offers two main advantages, first, it allows fault induction at geometric or layout level, thus providing a realistic representation of physical defects, and second, the current/voltage profile of power/ground-grid, derived for i_DDT fault simulation, can be used to perform accurate timing verification of logic circuit, thus facilitating design verification. In summary, the proposed fault simulation framework not only enables the assessment of defect detection capabilities of i_DDT test methodologies, but also establishes a platform for performing defect-based testing on practical designs.     

Wishbone总线交易级建模

交易级建模在系统功能建模和验证方面可以增快速度,也可以加速仿真的速度并允许在高层次抽象中研究和确认设计中可供选择的模块.针对Wishbone片上总线协议,依据SystemC中接口方法调用的基本原理和交易级建模的方法,完成了Wishbone总线中共享总线的交易级建模,结果表明SystemC适合在交易级建模系统的行为和通信,交易级建模在仿真速度方面具有优势.     

Test generation for data-path logic: the F-path method

Tests for data-path logic can be generated with the aid of high-level methods that utilize the presence of special forms of sensitized paths. These paths, called fault paths (F-paths), are defined so that they transmit fault information with certainty. Their presence can be determined from the functional definition of a block, and when, exceptionally, they are absent, a minimum hardware addition usually suffices to provide them. They permit use of powerful, computer-aided test generation methods that have permitted routine targeting of 100% coverage of an expanded fault set (more than just stuck-ats), verification of success by simple postprocessing of RTL (resistor-transistor logic)-level good-logic simulation     

Automatic Generation of System Level Assertions from Transaction Level Models

We automatically generate assertions from Transaction Level Model (TLM) simulation traces. The generated assertions express design specifications in the form of linear temporal logic with quantitative temporal constraints [4]. We first generate the assertions without regard to the quantitative time constraints. They are mined in the form of frequent patterns in the simulation traces. We mine simulation traces using episode mining to identify frequent episodes comprising function calls and events. We then annotate the episodes with real time parameters to express quantitative time constraints among the function calls or events in the episode. When mining such TLM assertions, we employ symbolic execution to generalize the parameters and return values of function calls in the traces to help the mining engine generate high quality assertions. We have constructed a realistic AXI-based interconnection network platform that we demonstrate experimental results on. We show that our technique efficiently generates high quality performance and functional assertions on the AXI-based platform as well as a transaction level AMBA-based DMA controller. We demonstrate that episode mining is more scalable and able to generate a more compact set of high quality TLM assertions than previous efforts using sequential pattern mining. The number of generated assertions using episode mining can be reduced by up to 228 times, and the time interval between two events/function calls in each assertion is smaller than 50 time units.     

Study, comparison and application of different VHDL-based fault injection techniques for the experimental validation of a fault-tolerant system

In this work different VHDL-based fault injection techniques (simulator commands, saboteurs and mutants) have been compared and applied in the validation of a fault-tolerant system. Some extensions and implementation designs of these techniques have been introduced. As a complement of these injection techniques, a wide set of fault models (including several non-usual models) have been implemented. We have injected both transient and permanent faults on the system model, using two different workloads, with the help of a fault injection tool that we have developed. We have studied the pathology of the propagated errors, measured their latencies, and calculated both detection and recovery coverages. Results show that coverages for transient faults can be obtained quite accurately with any of the three techniques. This enables the use of different abstraction level models for the same system. We have also verified significant differences in implementation and simulation cost between the studied injection techniques.     

Exploiting UML based validation for compliance checking of TLM 2 based models

SoC system designers commonly employ SystemC based Transaction level modeling (TLM) for its early software development usage and its analysis capabilities. TLM helps in realizing a SoC using virtual prototyping by integration of SoC components at different abstraction levels. The TLM 2 standard introduces interoperability rules for the models that may have been developed independently. However, neither SystemC compiler nor TLM library supports checking of such rules and manually debugging interoperability errors in such models could be a major problem. This provides motivation for developing automatic compliance checking techniques which can detect and report such errors. As the models are refined to incorporate detailed intercommunication protocols among the system components, the need for compliance checking extends to these protocols as well. In this paper, we present an efficient UML based compliance checking technique for TLM 2 models which supports static, dynamic and protocol-specific rule checking.     

Calibration of Abstract Performance Models for System-Level Design Space Exploration

High-level performance modeling and simulation have become a key ingredient of system-level design as they facilitate early architectural design space exploration. An important precondition for such high-level modeling and simulation methods is that they should yield trustworthy performance estimations. This requires validation (if possible) and calibration of the simulation models, which are two aspects that have not yet been widely addressed in the system-level community. This article presents a number of mechanisms for both calibrating isolated model components as well as a system-level performance model as a whole. We discuss these model calibration mechanisms in the context of our Sesame system-level simulation framework. Two illustrative case studies will also be presented to indicate the merits of model calibration.

An FPGA-based dynamically reconfigurable platform for emulation of permanent faults in ASICs

FPGA-based emulation of permanent faults in ASICs can considerably improve the fault simulation time compared to traditional software-based approaches. Moreover, a hardware-based solution provides realistic behavior during fault emulation which is often required in safety-critical systems' validation. Previous emulation approaches not only suffers from considerable area (for instrumentation) and reconfiguration (for fault injection) overheads but also provides limited coverage of the target faults (and fault sites). The latter is due to difficulties in establishing a fault model equivalence when the ASIC structural netlist is passed through the design automation phases of an FPGA. This paper presents a novel approach for fast emulation of permanent faults in ASICs on state-of-the-art dynamically reconfigurable SRAM-based FPGAs while achieving fault model equivalence. Our proposed approach leverages localized run-time in-place Look Up Table (LUT) reconfigurations to avoid the time-consuming bitstream generation process for every ASIC fault. Moreover, the speed of fault injection is enhanced by direct LUT configuration data modification inside a bitstream frame. This results in 17 and 4 times improvements in fault injection speeds over vendor-provided LUT modification libraries and existing partial bitstream based approaches respectively. However, this improvement is achieved at an average 1.2 and 1.1 times degradation in area and delay metrics for the considered mapped circuits which is affordable considering the benefits in terms of the emulation speed.