非规则栅结构PD CMOS/SOI器件SPICE模型参数分析

针对抗辐照设计中特殊非规则条栅栅结构的CMOS/SOI器件,分析其SPICE模型参数,对源漏电阻、电容、体接触电阻等其他模型参数作出调整,建立非标准器件的完整精确模型.设计制作了多种不同非标准栅结构的PD CMOS/SOI 晶体管,并采用新的SPICE模型参数来模拟这些器件.模拟数据和试验数据具有很好的一致性,证明所建立的模型具有较高精度,适合抗辐照电路设计应用.     

采用CoSi2 SALICIDE结构CMOS/SOI器件辐照特性的实验研究

讨论了CoSi2SALICIDE结构对CMOS/SOI器件和电路抗γ射线总剂量辐照特性的影响.通过与多晶硅栅器件对比进行的大量辐照实验表明,CoSi2SALICIDE结构不仅可以降低CMOS/SOI电路的源漏寄生串联电阻和局域互连电阻,而且对SOI器件的抗辐照特性也有明显的改进作用.与多晶硅栅器件相比,采用CoSi2 SALICIDE结构的器件经过辐照以后,器件的阈值电压特性、亚阈值斜率、泄漏电流、环振的门延迟时间等均有明显改善.由此可见,CoSi2SALICIDE技术是抗辐照加固集成电路工艺的理想技术之一.     

采用CoSi_2SALICIDE结构CMOS/SOI器件辐照特性的实验研究

讨论了CoSi2SALICIDE结构对CMOS/SOI器件和电路抗γ射线总剂量辐照特性的影响.通过与多晶硅栅器件对比进行的大量辐照实验表明,CoSi2SALICIDE结构不仅可以降低CMOS/SOI电路的源漏寄生串联电阻和局域互连电阻,而且对SOI器件的抗辐照特性也有明显的改进作用.与多晶硅栅器件相比,采用CoSi2SALICIDE结构的器件经过辐照以后,器件的阈值电压特性、亚阈值斜率、泄漏电流、环振的门延迟时间等均有明显改善.由此可见,CoSi2SALICIDE技术是抗辐照加固集成电路工艺的理想技术之一.     

0.1μmSOI槽栅CMOS特性仿真

基于SOI技术对器件特性的良好改善和槽栅MOS器件在深亚微米领域抑制短沟道效应和抗热载流子效应方面的显著优势,对SOI槽栅CMOS器件在0.1 μm尺寸下的电学特性进行了模拟仿真,仿真结果表明,基于SOI衬底的槽栅CMOS器件除了拥有槽栅器件独特优势之外,还很好地抑制了栅极漏电和阈值偏高等体硅槽栅MOS所具有的特性缺陷,得到了更加理想的实验结果.     

部分耗尽PD CMOS/SOI器件SEU模型分析

通过计算机模拟分析CMOS/SOI器件中单粒子效应的影响,采用二维模拟软件MEDICE,建立了器件发生单粒子效应时内部电荷的分布模型.利用电荷分布模型建立了CMOS/SOI器件在入射不同LET值时的离子与器件中瞬态电流的关系曲线;并建立了离子入射点的不同位置与瞬态电流的关系曲线.从理论上提供了一种分析器件SEU的手段.     

SOI器件中瞬态浮体效应的模拟与分析

针对 SOI器件中的瞬态浮体效应进行了一系列的数值模拟 ,通过改变器件参数 ,比较系统地考察了 SOI器件中瞬态浮体效应 ,同时也研究和分析了瞬态浮体效应对 CMOS/SOI电路 (以环振电路为例 )的影响 ,并提出了抑制器件浮体效应的器件结构和参数优化设计 .     

SOI器件中瞬态浮体效应的模拟与分析

针对SOI器件中的瞬态浮体效应进行了一系列的数值模拟,通过改变器件参数,比较系统地考察了SOI器件中瞬态浮体效应,同时也研究和分析了瞬态浮体效应对CMOS/SOI电路(以环振电路为例)的影响,并提出了抑制器件浮体效应的器件结构和参数优化设计.     

超深亚微米SOI总剂量效应泄漏电流模型

总剂量辐射效应会导致绝缘体上硅金属氧化物半导体场效应晶体管(SOI MOSFET)器件的阈值电压漂移、泄漏电流增大等退化特性。浅沟槽隔离(STI)漏电是器件退化的主要因素,会形成漏极到源极的寄生晶体管。针对130 nm部分耗尽(PD) SOI NMOSFET器件的总剂量辐射退化特性,建立了一个包含总剂量辐射效应的通用模拟电路仿真器(SPICE)模型。在BSIM SOI标准工艺集约模型的基础上,增加了STI寄生晶体管泄漏电流模型,并考虑了辐射陷阱电荷引起寄生晶体管的等效栅宽和栅氧厚度的变化。通过与不同漏压下、不同宽长比的器件退化特性的实验结果对比,该模型能够准确反映器件辐射前后的漏电流特性变化,为器件的抗辐射设计提供参考依据。     

一维0.18μm CMOS光电二极管量子效率的研究与模拟

为了建立更精确的CMOS光电二极管SPICE模型,使之在像素电路模拟中能够更好地反映实际的光电转换物理现象.使用连续性方程和不同的边界条件对CMOS光电二极管建立了一维物理模型,然后代入普通 CMOS 0.18工艺参数在温度为300 K、反偏电压为2.2 V时,对N-diff/P-epi, N-well/P-epi两种结构的二极管量子效率进行了模拟.其中考虑了表面复合速率、外延层厚度、P 衬底与P外延同质结等因素对模拟结果的影响.在此基础上,还对CMOS光栅二极管的量子效率进行了计算. 模拟结果符合这些器件已知的特性.     

体硅衬底上的CMOS FinFET

介绍了一种制作在普通体硅上的CMOS FinFET.除了拥有和原来SOI上FinFET类似的FinFET结构,器件本身在硅衬底中还存在一个凹槽平面MOSFET,同时该器件结构与传统的CMOS工艺完全相容,并应用了自对准硅化物工艺.实验中制作了多种应用该结构的CMOS单管以及CMOS反相器、环振电路,并包括常规的多晶硅和W/TiN金属两种栅电极.分析了实际栅长为110nm的硅基CMOS FinFET的驱动电流和亚阈值特性.反相器能正常工作并且在Vd=3V下201级CMOS环振的最小延迟为146ps/门.研究结果表明在未来VLSI制作中应用该结构的可行性.     

薄膜SOI／CMOS的SPICE电路模拟

鉴于ＳＰＩＣＥ是目前世界上广泛采用的通用电路模拟程序，具具有可扩展模型的灵活性，我们通过修改ＳＰＩＣＥ源程序把新器件模型－－ＳＯＩＭＯＳＦＥＴ模型移植入ＳＰＩＣＥ中，通过我们的模拟工作，证实了我们模型的正确性和电路实用性，分析了器件参数对ＳＯＩ／ＣＭＯＳ电路速率的影响，这些结论可以很好地指导电路设计和工艺实践。     

A 440-ps 64-bit adder in 1.5-V/0.18-μm partially depleted SOItechnology

A 64-bit adder in 1.5-V/0.18-μm partially depleted SOI technology, CMOS8S, and techniques to maintain performance are described. CMOS7S SOI, a 1.8-V/0.22-μm partially depleted SOI technology, achieves a 28% speed increase over bulk CMOS7S, and CMOS8S SOI delivers an additional 21%. In a 660-MHz CMOS8S SOI processor, the adder compensates for floating body effects in SOI devices which cause history effects, bipolar currents, and lower noise margins on dynamic circuits     

CMOS／SOI电路模拟与参数提取

ＳＯＩ－ＭＯＳＦＥＴ主要模型参数得一致的提取，因而该模型嵌入ＳＰＩＣＥ后能保证ＣＭＯＳ／ＳＯＩ电路的正确模拟工作，从ＣＭＯＳ／ＳＯＩ器件和环振电路的模拟结果和实验结果看，两者符合得较好，说明我们所采用的ＳＯＩ ＭＯＳＦＥＴ器件模型及其参数提取都是成功的。     

Computer-aided performance assessment of fully depleted SOI CMOSVLSI circuits

A physical model for the fully depleted submicrometer SOI MOSFET is described and used to assess the performance of SOI CMOS VLSI digital circuits. The computer-aided analysis is focused on both problematic and beneficial effects of the parasitic bipolar junction transistor (BJT) in the floating-body device. The study shows that the bipolar problems overwhelm the benefits, and hence must be alleviated by controlling the activation of the BJT via device design tradeoffs. A feasible approach to the needed design optimization is demonstrated by veritable device/circuit simulations, which also predict significant speed superiority of SOI over bulk-silicon CMOS circuits in scaled, submicrometer technologies     

Fault detection in CMOS/SOI mixed-signal circuits using the quiescent current test

Main stream bulk CMOS and the variants of silicon-on-insulator (SOI) CMOS technologies are discussed with respect to testing for the quiescent current of mixed-signal integrated SOI circuits. The 2–3 times lower static power consumption in fully depleted CMOS/SOI compared to bulk CMOS allows quiescent current testing also for high performance analogue circuits at an acceptable defect resolutions. From first simulations and technological considerations, it turned out that quiescent current tests are able to detect not only commonly known defects, but also SOI specific defects such as self-heating, kink-effect or the parasitic bipolar behaviour. It is further shown that in partially depleted thick-film SOI, the kink-effect and parasitic bipolar transistor support the quiescent current test for some specific defects as they elevate the defective quiescent current level. In fully depleted kink-free SOI circuits, the kink-effect may occur due to process failures but then can be detected by quiescent current tests. A special fault simulation model for the kink-effect is presented. The I_ccq test technique is studied for a CMOS/SOI Miller operational amplifier. Normal 6-σ variation of the aspect ratio and the threshold voltage do not jeopardise the defect detection in the quiescent current. First, results confirm the good detection capabilities of the quiescent current test, in particular, of failures which are not visible in the output voltage.     

Total dose radiation effects of hybrid bulk/SOI CMOS active pixel with buried channel SOI source follower

A CMOS active pixel with pinned photodiode which used in-pixel buried-channel (BC) transistor has been reported, and the characteristic of CMOS image sensor with in-pixel buried-channel transistor was carried out. In this paper, we have a research on a hybrid bulk/silicon-on-insulator (SOI) CMOS active pixel with pinned photodiode which use buried channel SOI NMOS Source Flower (SF) by simulation. We study the basic characteristics of buried-channel SOI NMOS and the characteristics of CMOS active pixel optimized by using in-pixel buried-channel SOI transistor under radiation. The results show that, compared to the conventional active pixel with the standard surface-channel (SC) SOI NMOS SF, the dark random noise of the pixel which uses in-pixel buried channel SOI NMOS SF can be reduced under the radiation and the output swing is improved.     

Radiation-Induced Fault Simulation of SOI/SOS CMOS LSI’s Using Universal Rad-SPICE MOSFET Model

The methodology of modeling and simulation of environmentally induced faults in radiation hardened SOI/SOS CMOS IC’s is presented. It is realized at three levels: CMOS devices – typical analog or digital circuit fragments – complete IC’s. For this purpose, a universal compact SOI/SOS MOSFET model for SPICE simulation software with account for TID, dose rate and single event effects is developed. The model parameters extraction procedure is described in great depth taking into consideration radiation effects and peculiarities of novel radiation-hardened (RH) SOI/SOS MOS structures. Examples of radiation-induced fault simulation in analog and digital SOI/SOS CMOS LSI’s are presented for different types of radiation influence. The simulation results show the difference with experimental data not larger than 10–20% for all types of radiation.     

CMOS on local SOI using SIMOX technology

CMOS on local SOI, in which n-MOS/bulk and p-MOS/SOI can be selectively implemented on the same chip, has been developed. SOI regions are formed by SIMOX technology, while bulk regions are prepared by etching of the buried SiO2. A CMOS inverter fabricated on local SOI shows good transfer characteristics.     

一种二维SOI CMOS门级瞬态数值模型

本文给出一种SOI CMOS门级二维集成数值模型.该模型直接将端点电流、端点电压与内部载流子的输运过程联系在一起,可准确地模拟亚微米SOI CMOS反相器的瞬态特性、并给出清晰的内部物理图象.模型采用一种新的数值方法──交替方向法,将二维瞬态方程转化为两个相邻时间层的一维问题解,并提出动态二步迭代法以确保瞬态模拟的快速、稳定收敛.本文简要讨论了SOI CMOS器件中少子的累积对电路瞬态特性的影响.本模型还可用于计算辐射对SOI器件的影响以及研究漏电机理,它为高可靠亚微米SOI器件及电路的研制提供了方便的CAD工具.     

Modeling of the bulk versus SOI CMOS performances for the optimal design of APS circuits in low-power low-voltage applications

In this paper, we present the top-down design of an active pixel sensor (APS) circuit using an analytical model of its architecture. The model is applied to compare the performances of bulk versus silicon-on-insulator (SOI) CMOS processes and devices on the designs and performance of several 50-frames/s imagers in 2-/spl mu/m and 0.25-/spl mu/m CMOS with different pixels array sizes. For 2-/spl mu/m SOI, results show a reduction by two of the power consumption and a dynamic range increase of 0.85 V under a 3-V supply. This results in an SNR of 79 dB instead of 76. Fixed pattern noise (FPN) is also reduced from 2.7 to 1.8 mV which represents 0.26% and 0.08% of the dynamic range, respectively. For 0.25-/spl mu/m CMOS SOI, results show a reduction by 6.5 of the power consumption, FPN more than five time better, and a dynamic range increase of 0.29 V under a 1.5-V supply. However, because of the increase of the thermal noise due to the particular design choice, an SNR of 60.3 dB is achieved compared to 63 in bulk. A better SNR in SOI than in bulk can be achieved but at the expense of power consumption and FPN. However, this could be combined with an increase in pixels number in SOI compared to bulk. Potential results achievable in SOI have to our knowledge never been reached by bulk APS imagers up to now.