Aladin: A Layout Synthesys Tool for Analog Integrated Circuits

This paper presents a layout synthesis tool called ALADIN for analog integrated circuits. It is developed especially for analog circuit designers who can bring their special knowledge and experience into the synthesis process to create high quality layouts. The layout generation is based on relatively complex sub-circuits rather than non-optimal single devices. A flexible module generator environment is developed for designers to write and maintain technology and application independent module generators of sub-circuits. Based on the thorough study of simulated annealing and genetic algorithm applications in the analog module placement, a genetic placement approach with simulated annealing and a very fast simulated re-annealing placement approach have been developed. A two-stage placement technique is proposed. Analog module routing consists of two phases including global routing and detailed routing. The minimum-Steiner-tree based global routing can be integrated into the placement procedure to improve the routability of placement solutions. The compaction based constructive detailed routing finally realizes the layout of the whole circuit. This tool is integrated into commercial software with convenient interfaces provided. The benefit of ALADIN providing layouts comparable to expert manual ones is demonstrated with several circuits showing its competition compared to other existing tools.     

ALGA: Automated layout generator for analog CMOS circuits

A computer-aided design (CAD) system called ALGA for an analog circuit layout is presented. The main contribution of this paper is to construct a weight graph that represents the topological connectivity of a given analog circuit. By using the weight graph, some efficient techniques can be designed to avoid devices mismatch and place all devices according to the device size constraints. Moreover, an algorithm is presented to perform the device placement step and propose an effective approach to reduce noise coupling in the routing step. A design method has been implemented in several Complementary Metal Oxide Semiconductor (CMOS) analog circuits. It is seen that the proposed system can generate good analog circuit design.     

Automatic layout synthesis of analog ICs using circuit recognition and constraint analysis techniques

A systematic method for automatic layout synthesis of analog integrated circuit modules is presented. This method uses analog circuit recognition and critical net analysis techniques to derive proper layout constraints for analog circuit performance optimization. These layout constraints are analyzed and prioritized according to the recognized analog circuit topologies and classified net sensitivities. The weighted constraints are then used to drive the physical layout generation process to obtain a high-quality custom circuit layout. An efficient, constraint-driven analog floorplanning technique based on a zone-sensitivity partitioning algorithm is specially developed to generate a slicing floorplan incorporating the layout constraints. This layout synthesis approach has three key advantages. First, it can produce a satisfactory analog circuit performance with negligible degradation due to the layout-introduced parasitic effects. Second, it allows a complete automation for netlist-to-layout synthesis so that the layout tool can be used by VLSI system designers. Finally, this method is quite general and can be applied to handle a wide variety of analog circuits. Experimental results in CMOS operational amplifiers and a comparator are presented.     

布图CAD—模拟ASIC发展的关键

本文强调布图CAD技术对发展模拟ASIC的重要性和必要性。简述通用电路布图CAD各阶段内容及其算法。着重讨论模拟ASIC布图的特殊性及其典型模式。     

CMOS PLA自动版图设计系统

ＰＬＡ自动版图设计系统可以使设计者快速地得到时宏单元，从电路盒物理版图的细节中解放出来。由于ＰＬＡ较低的设计费用和可编程的特点，设计系统对于实现电路中的控制部分十分有效。     

Directly performance-constrained template-based layout retargeting and optimization for analog integrated circuits

Due to intrinsic intricacy, layout parasitics exhibit a significant impact on the performance of analog integrated circuits. In this paper a directly performance-constrained parasitic-aware automatic layout retargeting and optimization algorithm is presented. Unlike the conventional sensitivity analysis, a general central-difference based scheme using any simulator for sensitivity computation is deployed. We propose a piecewise sensitivity model to enforce more accurate sensitivity computation during parasitic optimization. Moreover, mixed-integer performance constraints due to parasitics are included in the formulated mixed integer nonlinear programming problem rather than through either indirect parasitic-bound constraints or inaccurate worst-case sensitivities. A graph technique and mixed-integer nonlinear programming are effectively combined to solve the formulated parasitic optimization problem. The automatically generated target layouts can satisfy performance constraints to ensure the desired specifications. The experimental results show that the proposed algorithm can achieve effective retargeting of analog circuits with less layout area and significant reduction in execution time.     

A performance-driven placement tool for analog integrated circuits

This paper presents a new approach toward performance-driven placement of analog integrated circuits. The freedom in placing the devices is used to control the layout-induced performance degradation within the margins imposed by the designer's specifications. This guarantees that the resulting layout will meet all specifications by construction. During each iteration of the simulated annealing algorithm, the layout-induced performance degradation is calculated from the geometrical properties of the intermediate solution. The placement tool inherently handles symmetry constraints, circuit loading effects and device mismatches. The feasibility of the approach is demonstrated with practical circuit examples     

可编程逻辑阵列（PLA）自动版图生成器

可编程逻辑阵列ＰＬＡ自动版图生成器可以使设计者快速地得到宏单元，从电路盒物理版图的细节中解放出来，因ＰＬＡ较低的设计费用和可编程的特点，生成器对于实现电路中的控制部分十分有效，ＰＬＡ自动版图生成器在国内首次实现了ＰＬＡ由逻辑输入到版图生成的自动设计。     

New layout strategies with improved matching performance

In this paper, the systematic mismatch error in integrated circuits due to gradient effects is modeled and analyzed. Three layout strategies with improved matching performance are reviewed and summarized. The hexagonal tessellation pattern can cancel quadratic gradient errors with only 3 units for each device and has high area-efficiency when extended. Both the Nth-order circular symmetry patterns and Nth-order central symmetry patterns can cancel up to Nth-order gradient effects between two devices using 2^N unit cells for each one. Among these three techniques, the central symmetry patterns have the best-reported matching performance for Manhattan structures; the circular-symmetry patterns have the best theoretical matching performance; and the hexagonal tessellation pattern has high density and high structural stability. The Nth-order central symmetry technique is compatible to all IC fabrication processes requiring no special design rules. Simulation results of these proposed techniques show better matching characteristics than other existing layout techniques under nonlinear gradient effects. Specifically, two pairs of P-poly resistors using 2nd and 3rd-order central symmetry patterns were fabricated and tested. Less than 0.04% mismatch and less than 0.002% mismatch were achieved for the 2nd and the 3rd-order structures, respectively. Chengming He was born in YiWu, China in 1976. He received his B.S. in 1999 in Electronic Engineering department and his M.S. degree in the institute of Microelectronics in 2001 at Tsinghua University, Beijing. He started to work toward his PhD in Iowa State University since August 2001. Since June 2004 he started to work as a design engineer in Silicon Laboratories, Inc., Austin, TX. He studied and designed LNA, band-pass filter and on-chip power management blocks as well as matching-enhanced layout patterns. He is interested in designing high gain low voltage amplifier, high speed power-efficient ADC and high speed high linear DAC as well as other mixed-signal circuits. He is also interested in the application of nonlinear system dynamical theory in mixed-signal design and yield-enhancement by improving layout matching. He has published more than 10 technical papers. He was a student member of IEEE from 01--04 and now is a member. He is a member of Tau Beta Pi. Xin Dai was born in Shanghai, China on March 11, 1981. She received the B.Eng. in 2003 from Shanghai Jiao Tong University, Shanghai, China. She is currently a graduate student in Department of Electrical and Computer Engineering at Iowa State University, Ames, IA. Her research has been connected to data converter design and calibrations, layout techniques and build-in-self-test. Xin Dai is now taking a summer-intern in Broadcom Corp., CA. Hanqing Xing was born in Dalian, China, in 1978. He received the B.S. and M.S. degrees with honors in Electronic Engineering from Tsinghua University, Beijing, China, in 2000 and 2003, respectively. He is currently a PhD student at Iowa State University working in analog and mixed signal design group. His research interests include analog, mixed-signal, and data-conversion integrated circuits design and test. Degang Chen received his B.S. degree in 1984 in Instrumentation and Automation from Tsinghua University, Beijing, China and his M.S. and Ph.D. degrees in 1988 and 1992, respectively, both in Electrical and Computer Engineering, from the University of California, Santa Barbara. From 1984 to 1986, he was with the Beijing Institute of Control Engineering, a space industry R/D institute. From March 1992 to August 1992, he was the John R. Pierce Instructor of Electrical Engineering at California Institute of Technology. After that, he joined Iowa State University where he is currently an Associate Professor. He was with the Boeing Company in summer of 1999 and was with Dallas Semiconductor-Maxim in summer of 2001. His research experience include particulate contamination in microelectronic processing systems, vacuum robotics in microelectronics, adaptive and nonlinear control of electromechanical systems, and dynamics and control of atomic force microscopes. His current teaching and research interests are in the area of analog and mixed-signal VLSI integrated circuit design and testing. In particular, he is interested in low-cost high-accuracy testing and built-in-self-test of analog and mixed-signal and RF circuits, and in self-calibration and adaptive reconfiguration/repair strategies for performance and yield enhancement. Dr. Chen is the recipient of the Best Paper Award at the 1990 IEEE Conference on Decision and Control and the Best Transaction Paper Award from the ASME Journal of Dynamic Systems, Measurement, and Control in 1995. He was selected an A.D. Welliver Faculty Fellow with the Boeing Company in 1999.     

Targeted layout modifications for semiconductor yield/reliability enhancement

A new layout modification tool for the automation of layout modifications to improve the yield and reliability of semiconductor IC layout is reported. The Peye tool combines a polygon library with the practical extraction and reporting language (Perl). This new tool permits complex layout modification operations to be defined using the powerful language features of Perl. The Peye tool has been interfaced with a sampling-based yield prediction system to enable the measurement of the layout modifications and yield predictions based on these modifications. This enables the usefulness of a modification to a particular design to be assessed by sampling before use. Both the sampled measurement and the final modifications to the whole chip database can be farmed out to a number of networked computers, enabling the system to assess and apply layout modifications to large industrial ICs in a reasonable time. The results of layout modifications are presented.     

模拟集成电路版图中的对称检测与提取方法

新一代模拟集成电路版图自动化系统在重用原有版图时,迫切需要提取其中的匹配设计信息,以保证其输出版图的质量.在角勾链数据结构的基础上,提出了新的对称检测、提取算法及数据结构.该算法检测出器件之间的对称关系,进一步提取出模块之间的对称关系,并将器件级和模块级对称关系及底层的角勾链结构以独特的数据结构统一存储.结果表明,该算法与数据结构能够有效地提取并表示设计者在版图中渗透的匹配设计思想,为版图的生成提供多级对称约束条件,从而有力地保证重用系统所输出的模拟版图的性能.     

A comprehensive analysis on differential cross-coupled CMOS LC oscillators via multi-objective optimization

CMOS differential cross-coupled LC oscillators are widely used due to their superior phase noise performance. Even though the number of circuit elements is small, the design process is not trivial due to the complicated trade-off between the phase noise and power consumption. Conventionally, cross-coupled oscillators can be constructed by using only PMOS or only NMOS devices or using both (CMOS). The topology selection is mostly based on either theoretical calculations or experimental (measurement/simulation) results on specific solution points reported in the literature; however, there is no comprehensive analysis on comparison of these topologies in the literature. Also, there are several efforts on improving the phase noise response such as conventional tail noise filtering (using a tail capacitor or LC filter) and sinusoidal tail shaping. Yet, the cost-performance effectiveness of such techniques has not been well-discussed in the literature. In this study, performances of different differential cross-coupled LC oscillators are examined using a parasitic-aware multi-objective RF circuit synthesis tool. PMOS, NMOS, and CMOS types of oscillators were synthesized and performances of those circuits were thoroughly demonstrated. The synthesis results were validated by performing post-layout simulations for different solutions located on the Pareto optimal front (POF). To observe the effect of the other layout parasitics, the CMOS oscillator was also optimized including a parasitic netlist of a drawn layout. The effect of using LC tank with centre-tapped inductor on oscillator performance was also investigated. Furthermore, effectiveness of several phase noise reduction techniques; tail capacitor filtering, tail LC filtering, and sinusoidal noise shaping were demonstrated and discussed in detail.     

Methods for automated detection of plagiarism in integrated-circuit layouts

Student projects have always been plagued by plagiarism. Integrated-circuit (IC) design courses are no exception. Since layout is considered the most laborious part of circuit design, it is common for students to reuse their colleagues? work with some minor modifications intended to make the cheating harder to detect. While software detecting plagiarism in text or computer code is commonly used these days, no counterpart exists for IC layouts. This paper proposes several criteria of IC-layout dissimilarity that can be used for computer-aided layout matching. A program based on these criteria is shown to successfully identify similar layouts in a pool of designs.     

模拟集成电路设计自动化技术

随着对数模系统集成技术的迫切需求,模拟集成电路综合技术的研究正受到越来越广泛的注视。本文评述了现有模拟集成电路设计自动化技术的主要方法:拓扑综合,器件尺寸优化和版图综合技术。     

Recent developments and trends in bipolar analog arrays

Recent developments in bipolar analog arrays are reviewed. The use of tiles, their characteristics, and impact on design is evaluated. The progression from breadboarding to computer-aided simulation of array circuits with sophisticated transistor models is discussed. Design layout tools and functional libraries for the user are also reviewed in terms of their importance to analog array design. The increased use of arrays has revealed new problems and responses to them are discussed. Limitations of analog arrays with respect to full custom IC design are delineated. The paper concludes with a short discussion of future trends.     

计算机辅助激光切割布局系统的研发

针对激光切割机切割板材的特点,开发了计算机辅助激光切割布局系统。论文介绍了计算机辅助优化布局的相关基本知识,阐述了计算机辅助系统的优化算法,描述了系统的界面,输入方式,使用方法;并利用开发的系统做了8组随机仿真布局试验,给出了两组布局方案图。试验结果表明:利用开发的系统可以快速生成材料利用率高的优化布局图。按照布局图对板材进行布局设计,可以大大提高材料的利用率,降低生产成本,提高企业利润。     

探讨在版面分析中的聚类稳定性问题

版面分析过程可以理解为同模式类对象间聚类(合并)的过程,而这种聚类存在的风险(hazard)是伴随整个聚类过程中的。而且越是在后期,该风险值越高,即一旦出现聚类错误则将导致前期正确的聚类结果付诸东流。该文将就此问题展开关于版面分析中的聚类稳定性问题的探讨,并提出相应的逻辑规则——逻辑判别函数(logic differentiation function)用来指导聚类和其在聚类算法中的应用;实验结果表明,建立在定性分析基础上的该规则能解决聚类过程的稳定性问题,同时该规则可以应用在存在若干模式类对象聚类的场合中。