如何确定功率MOSFET的适用性

功率金属氧化半导体场效应晶体管（Power MOSFET）是当今电源中广泛使用的开关器件。功率MOSFET的工作频率不断提高，以减小器件尺寸和提高功率密度。这样就会增加电流变化率（di／dt），增强了寄生电感的负面作用，导致功率MOSFET源极和漏极之间产生很高的电压尖峰。这种尖峰电压在器件上电时更为严重，因为在上电瞬间变压器的初级电感几乎达到漏感的水平，同时器件的体电容还未完成充电且电感较小。幸好功率MOSFET具有一定的抗过压能力，因此无需外加成本高昂的保护电路。     

功率母线

高速开关和现代封装技术要求变革电子产品的功率分配的传统方法——电缆线束,铜片总线和印刷电路板上的电源线与地线,期望功率分配线的电感小、电阻低,电容大和占用空间小。 图1[a]所示的叠层结构的功率母线(Bus Bars)已应用于大型计算机系统,通信和航空电子学等的功率分配子系统,新型通用功率器件已显著地提高了开关速率,在传     

功率模块是低感应系统设计的关键因素

在高频开关电源应用上寄生电感经常会导致开关装置产生过电压并增加半导体器件的判断损耗。通过引入智能功率模块的设计概念，可以减小系统的总电感、电压应力以及开关损耗。本文介绍了新型功率模块的概念以及其在PCB级电路上的应用，还介绍了新型功率模块所带来的寄生电感，关断过电压以及开关损耗的改进效应。     

功率驱动芯片高速开关引起的电源振荡现象研究

以等离子显示驱动为例,详细分析了功率驱动芯片在高速开关状态下所引起的电源振荡机理。考虑板级与芯片中驱动器件的主要寄生参数,建立了振荡电路的数学分析模型,基于所建模型,重点研究了环路电阻、芯片寄生电感和负载电容对振荡的影响,提出了减小电源振荡的优化方法,并得到了试验验证。     

PWM整流的电机试验变频电源系统的研究

介绍了一种新型电机试验变频电源,可以满足电压等级在1200V以下,功率等级在100k W以下的异步电机、变频电机等电机的出厂试验、型式试验的需求。采用PWM整流,母线电压可调的直流环节,逆变环节采用两套PWM逆变器对被试电机及陪试电机进行控制,由于后级未使用变压器,可大大节省空间,减小体积,同时电机做叠频试验时,能保持直流母线电压的稳定,再生能量及时回馈电网,减少电容的使用量。     

一种两象限零电压开关准谐振DC-DC转换器设计(英文)

传统的DC-DC转换器由电感、电容构成,通常电感和电容的面积很大,而且在开关导通和关断时的损耗严重。开关电感的两象限DC-DC转换器同时具有高功率密度和高转换效率,但是其开关导通和关断时的功率损耗仍然很严重。软开关技术可以实现开关导通和关断时的零功率损耗,从而大大减小了转换器的功率损耗。文章设计了一种新型的两象限零电压开关DC-DC转换器(ZVS-QRC),有效减小了功率损耗,并提高了功率密度和转换效率。     

一种具有能量回馈功能的级联型高压变频器的仿真研究

本文采用成熟的三相PWM整流技术,通过改造级联型高压变频器单个功率单元的整流部分,对直流母线电容电压进行闭环控制来稳定功率单元直流母线电容上的电压,实现能量回馈。这种方法不仅解决了一般的级联型高压变频器能量不能回馈,单个功率单元直流母线电容电压不稳的问题,而且还能使网侧的功率因数为1,使级联型高压变频器成为真正的绿色变频器。     

一种具有能量回馈功能的级联型高压变频器的仿真研究

本文采用成熟的三相四象限PWM整流技术,通过改造级联型高压变频器单个功率单元的整流部分,对直流母线电容电压进行闭环控制来稳定功率单元直流母线电容上的电压,实现能量回馈。这种方法不仅解决了一般的级联型高压变频器能量不能回馈,单个功率单元直流母线电容电压不稳的问题,而且还能、使网侧的功率因素为1,使级联型高压变频器成为真正的绿包变频器。     

迭层功率母线

1 前言高速开关和现代封装技术要求变革电子产品传统的功率分配方法——电缆线束、铜片总线和印刷电路板上的电源线与地线,期望功率分配线的电感小,电阻低,电容大,占用空间小。图1b给出的迭层结构功率母线(Bus Bars)已应用于大型计算机系统、通信和航空电子学等的功率分配子系统,新型通用功     

一种采用频率变换的自供电电源管理电路

 在低频率条件下,采用直接阻抗匹配的原理,设计的压电材料换能器电源管理电路,匹配电感值很大.本文采用频率变换,设计了一种自供电电源管理电路.分析了频率变换的原理.将低频信号变换至较高频率,匹配电感值很小,有利于电路的小型化.该管理电路还可以在宽频带内对于压电换能器实现匹配.实验结果表明,电路实现了频率变换,匹配电感值和电路体积都大大减小.电源管理电路的最大采集功率为181.6mW,能量采集效率可以达到44.8%.当0.47法拉的储能电容电压为1.13V时,该电路最大放电功率可达110mW,放电时间持续620ms,能够驱动无线传感器在一个周期内正常工作.     

寄生电感对碳化硅MOSFET开关特性的影响

相比于传统的Si IGBT功率器件而言,碳化硅MOSFET可达到更高的开关频率、更高的工作温度以及更低的功率损耗.然而,快速的暂态过程使开关性能对回路的寄生参数更加敏感.因此,为了评估寄生电感对碳化硅MOSFET开关性能的影响,基于回路电感的概念,将栅极回路寄生电感、功率回路寄生电感以及共源极寄生电感等效成3个集总电感,并且从关断过电压、开通过电流及开关损耗等3个方面,对这3个电感对SiC MOSFET开关性能的影响进行了系统的对比研究.研究表明:共源极寄生电感对开关的影响最大,功率回路寄生电感次之,而栅极回路寄生电感影响最小.最后,基于实验分析结果,为高速开关电路的布局提出了一些值得借鉴的意见.     

碳化硅功率器件高密度互连技术研究进展

相比于硅,SiC材料因具有宽禁带、高导热率、高击穿电压、高电子饱和漂移速率等优点而在耐高温、耐高压、耐大电流的高频大功率器件中得到了广泛应用。传统的引线键合是功率器件最常用的互连形式之一。然而,引线键合固有的寄生电感和散热问题严重限制了SiC功率器件的性能。文章首先介绍了硅功率器件的低寄生电感和高效冷却互连技术,然后对SiC功率器件互连技术的研究进行了综述。最后,总结了SiC功率器件互连技术面临的挑战。     

寄生电感对低压增强型GaN HEMT开关行为的影响

寄生电感是影响功率管开关特性的重要因素之一,开关频率越高,寄生电感对低压增强型氮化镓高电子迁移率晶体管(GaN HEMT)的开关行为影响越深,使其无法发挥高速开关的性能优势。通过建立数学模型,理论分析了考虑各部分寄生电感后增强型GaN HEMT的开关过程,并推导了各阶段的持续时间和影响因素,然后通过建立双脉冲测试平台,对各部分寄生电感对开关特性的具体影响进行了实验验证。实验结果表明,寄生电感会使开关过程中的电流、电压出现振荡,影响开关速度和可靠性,并且各部分寄生电感对增强型GaN HEMT的开关过程影响程度不同,在实际PCB布局受到物理限制时,需要根据设计目标优化布局,合理分配各部分寄生电感以获得最优的开关性能。     

Design of a novel receiving structure for wireless power transfer with the enhancement of magnetic coupling

In a wireless power transfer (WPT) system, the transfer performance is related to the mutual inductance between coils. However, the mutual inductance decreases with the increase of transfer distance. In this work, the relationship between the output voltage and the mutual inductance for WPT systems with air core and with ferrite core are analyzed. In order to improve the mutual inductance, a novel configuration of receiving resonator with a strong magnetic coupling is proposed. The mutual inductance and magnetic field distribution for coils with a cylindrical core and with the novel configuration are compared. Experiments are carried out for validation. The results indicate that the proposed WPT system is superior to the system with the cylindrical ferrite core in increasing the output voltage and power transfer efficiency.     

Minimum current magnitude control of surface PM synchronous machines during constant power operation

The dual-mode inverter control (DMIC) was initially developed to provide broad constant power speed range (CPSR) operation for a surface mounted permanent magnet machine (PMSM) having low inductance. The DMIC interfaces the output of a common voltage source inverter (VSI) to the PMSM through an ac voltage controller. The ac voltage controller consists of three pairs of anti-parallel silicon controlled rectifiers (SCRs), one anti-parallel SCR pair in series with each winding of the motor. In a recent paper a fundamental frequency model of DMIC type controllers was developed using an equivalent reactance interpretation of the in-line SCRs. In this work, the same fundamental frequency model is used to show that the DMIC may have considerable loss reduction benefits even if the motor winding inductance is large. Specifically, it is shown that the SCRs enable maximum watts per rms amp control during constant power operation. The rms motor current can be minimized for any given power level and sufficiently large speed with DMIC. A fixed winding inductance and a conventional inverter can only be optimized for a single speed and power level. The performance predicted by the fundamental frequency model of the DMIC is compared to that of a conventional PMSM drive where the motor has sufficiently large inductance to achieve an infinite CPSR. It is shown that the SCRs can reduce motor current by a factor of 0.7071 at high speed and rated power. This would reduce the motor copper losses by 50% and reduce the conduction losses in the VSI by 29.3%. At less than rated power the percentage of motor/VSI loss reduction enabled by the SCRs is seen to be even larger.     

Conduction power loss in MOSFET synchronous rectifier withparallel-connected Schottky barrier diode

The conduction power loss in an MOSFET synchronous rectifier with a parallel-connected Schottky barrier diode (SBD) was investigated. It was found that the parasitic inductance between the MOSFET and SBD has a large effect on the conduction power loss. This parasitic inductance creates a current that is shared by the two devices for a certain period and increases the conduction power loss. If conventional devices are used for under 1 MHz switching, the advantage of the low on-resistance MOSFET will almost be lost. To reduce the conduction loss for 10 MHz switching, the parasitic inductance must be a subnanohenley     

New high power DC-DC converter with loss limited switching and lossless secondary clamp

A new isolated high frequency high power DC-DC converter full bridge topology employing one resonant "soft" switching pole that is zero voltage switched and one phase-shifted hard switching pole with loss limited switching for primary switching is presented. The devices in the loss limited pole do not have resonant capacitors across them, but exhibit significantly lower losses than conventional hard switching as the energy dissipation is limited by the finite energy stored in the leakage inductance. This unique combination of zero voltage switching and loss limited switching reduces the switching loss in all primary devices to lower levels. Isolation is achieved by a coaxially wound high frequency transformer with ultra low leakage which increases throughput and efficiency. A novel nondissipative secondary rectifier clamp allows excellent control of reverse recovery energy. Converters that produce 128 kW at 25 kHz have been developed and are commercially available. As this topology exhibits complete control of all parasitic loss mechanisms, it can be easily scaled to higher power levels.     

Thin-film quasi-SOI power MOSFET fabricated by reversed siliconwafer direct bonding

A quasi-SOI power MOSFET has been fabricated by reversed silicon wafer direct bonding. In this power MOSFET, the buried oxide under the channel and source regions is removed and the channel region is directly connected to the source body contact electrode to reduce the base resistance of the parasitic npn bipolar transistor. The quasi-SOI power MOSFET can suppress the parasitic bipolar action and shows lower specific on-resistance than that of the conventional SOI power MOSFET. The fabricated chip level quasi-SOI power MOSFET shows the specific on-resistance of 86 mΩ·mm² and on-state breakdown voltage of 30 V     

A high-PSR transient-enhanced output-capacitorless CMOS low-dropout regulator for SoC applications

A transient-enhanced output-capacitorless CMOS low-dropout voltage regulator (LDO) with high power supply rejection (PSR) is introduced for system-on-chip applications. In order to reduce external pin count and device area and be amenable to full integration, the large external capacitor used in the classical LDO design is eliminated and replaced with a much smaller 5.7?pF on-chip capacitor. High-gain folded-cascode stage, wideband common source stage, voltage subtractor stage and transient-enhanced circuit are designed altogether to realise circuit compensation and achieve good frequency and transient performances. A current-sensing and transient-enhanced circuit is utilised to reduce transient voltage dips effectively and efficiently drive different kinds of load capacitances. The active chip area of the proposed regulator is only 200?×?280?µm². The simulation results under mixed-signal 0.18?µm 1P6M process show that this novel LDO's output voltage can recover within 1.7?µs (rising) and 2.41?µs (falling) under full load-current changes. The input voltage is ranged from 2 to 5?V for a load current 50?mA and an output voltage of 1.8?V. This novel LDO has wide unity-gain frequency stability and is stable for estimated equivalent parasitic capacitive loads from 0 to 100?pF. Moreover, it can achieve a PSR of ?78.5 and ?73?dB at 1 and 10?kHz, respectively.     

Effect of bipolar turn-on on the static current-voltagecharacteristics of scaled vertical power DMOSFET's

The parasitic bipolar transistor inherent in the power vertical Double Diffused MOSFET (DMOSFET) structure can have a significant impact on its performance and reliability. Selectively formed TiSi₂ films on source contacts were used to reduce the contact resistance to n ⁺ source diffusion. These devices exhibit “kinks” in the output I-V characteristics. High contact resistance of TiSi₂ to moderately doped p-body diffusion causes high output conductance. Detailed two-dimensional numerical simulations are used to investigate the effect of the parasitic bipolar transistor on the static characteristics of scaled silicided DMOSFET's. The high contact resistance of TiSi₂-p-body interface leads to a floating potential and causes significant reduction in the MOS gate threshold voltage and results in a premature bipolar turn-on. It is shown that the parasitic bipolar turn-on places an important constraint on the scalability of the device into the submicron regime. A novel self-aligned DMOSFET structure with a shallow diffused p⁺ region is shown to eliminate this effect. Numerical simulations are shown to be in excellent agreement with the measured data at various temperatures