一种可编程的高抗干扰AGC的设计

在射频接收系统中,自动增益控制(AGC)电路能够有效改善接收机的动态范围。文中设计了一种可编程的高抗干扰AGC电路,采用“窄带滤波+对数放大+模数转换+单片机”的负反馈方式实现自动增益控制功能。经过实际测试,该电路在初始信噪比、信噪比分别恶化30 dB、60 dB和85 dB共4种情况下,增益动态范围达到32 dB,输出信号的功率误差<0.5 dB,表明该电路结构在恶劣的信噪比环境中仍然能够正常工作,具有良好的抗干扰能力。     

双环AGC电路的起控点参数分析与设计

文中提出一种新的双环AGC控制电路设计思路，并对设计过程进行详细阐述。从单环到双环AGC设计，通过搭建两级自动增益控制电路，叠加控制量之和，从而增大控制范围，实现大动态范围信号处理能力。基于双环AGC电路的实例应用，分析双环AGC电路起控参数的设计思路和影响。另外，提出参数设计既要考虑因为射频AGC起控太早而恶化接收通道的噪声系数，又要避免射频AGC起控太晚造成接收通道饱和或是互调指标恶化的遵循原则。     

ETC.RSU收发前端模块设计

设计并实现了一种用于ETC系统的收发前端模块,提出了一种新型ASK调制电路,较之传统收发模块性能有较大提高。该模块发射路采用数字模拟双重衰减器设计,接收路采用双AGC电路设计,可实现发射的ASK信号调制度30%～100%连续可调,接收动态范围-5～-85dBm,发射功率-4.5～27dBm,步进0.5dB可调,发射频率5 700～5 900MHz,步进1MHz可调。     

一种高灵敏接收机前端电路的研究

接收机前端电路是接收机重要组成部分,天线把接收到的微弱信号通过接收机前端电路进行滤波、放大、下变频,把信号从高频转换成中频,经过处理后的信号更容易被接收机接收识别,从而提高了接收系统的灵活性和通用性。电路采用超外差式结构设计前端电路,通过自动增益控制来调整电路增益,使其信号稳定输出。通过实测本地振荡器信号和经过前端电路处理后的信号幅频特性,验证该电路设计的合理性,证明该电路可广泛用于高灵敏接收机前端。     

一种带有自适应增益控制的激光雷达模拟前端

为了处理宽动态范围的激光脉冲回波信号,设计了一种带有自适应增益控制技术的模拟前端。通过分段调节跨阻放大器的跨阻增益,实现了在1 μA~1 mA范围内输入电流与输出电压近似线性的关系。提出了自触发使能方法,可以在没有外部清零信号的情况下连续接收回波信号。提出了一种新型差分移位时刻鉴别电路,能有效减小行走误差。电路采用0.11 μm CMOS工艺设计,后仿真结果表明,-3 dB带宽为530 MHz,最大跨阻增益为103 dBΩ,等效输入噪声电流谱密度为6.47 pA·Hz-1/2@350 MHz,输入动态范围为60 dB,功耗小于100 mW。该模拟前端电路设计适用于飞行时间脉冲激光雷达。     

高灵敏度大动态范围EAS射频接收前端设计

由于EAS电子标签信号变化范围很大,同时为了提高EAS系统对电子标签的检测距离,EAS射频接收前端必须具备很高的接收灵敏度和足够大的动态范围。本文首先对射频前端接收灵敏度和动态范围的理论进行了讨论,在此基础上,采用低噪声放大器RFMD3827和自动增益控制芯片AD8325设计了一款适用于7.7~8.7 MHz的射频EAS接收机系统的射频前端部分。经过实验测试,该系统在较强的电磁环境下通过AGC的实时动态调整可以使系统的实现零误报,同时可以使软标签的检测范围提高5~10cm。     

一种零中频通用射频前端的设计及实现

摘要：本文采用零中频结构针对800～2400MHz工作频段设计了一种通用射频前端,该射频前端在一款高性能解调器的基础上,加入宽带低噪声放大器、程控射频AGC电路、电调谐预选滤波器等电路,从而实现灵敏度优于-100dBm/5MHz,动态范围大于100dB的设计指标要求。     

应用于TD-LTE接收机射频前端的一种AGC电路

基于可变增益放大器AD8367,结合线性检波器AD8361和误差放大器AD820,为TD-LTE接收机射频前端设计了一个自动增益控制(AGC)电路,实物测试显示该AGC电路能在输入信号频率为240MHz,输入信号功率为-40dBm到-10dBm时,输出信号功率能稳定在0dBm处,分析了该AGC电路噪声对接收机整体噪声的影响,满足系统指标的要求。设计思维简洁,电路结构简单,可以方便地调节输出电平值,确保接收机正常工作。     

60 dB动态范围的自动增益控制电路设计

设计了一种工作频率在15.42 MHz应用于GPS射频接收芯片中的自动增益控制(AGC)电路,该电路与传统AGC结构相比,不需要峰值检测电路,也不需要环路滤波器,大大简化了设计复杂度,同时也使电路性能受工艺及温度变化的影响大大减小了,因此适用于低功耗、高集成的GPS射频通信系统中.电路设计采用TSMC 0.25 μm CMOS工艺,电源电压2.5 V,经过流片验证,其动态范围可达60 dB,工作频率范围为[3.8 MHz,40 MHz],总功耗5 mW     

基于非谐振线圈的磁共振接收前端设计与实现

文中介绍了一种基于非谐振线圈的磁共振接收前端的设计原理和电路实现,将商用谱仪上的多通道谐振探头改造为非谐振线圈结构,并设计了一款与非谐振线圈匹配的低噪声放大器(Low Noise Amplifier,LNA),不但能够较好地放大非谐振线圈接收的信号,还可以与后级的商用谱仪系统匹配使用,将信号传输到控制台进行数字化处理。在商用300MHz Bruker AVANCE III谱仪上,通过接收前端成功探测到了重水样品的NMR(Nuclear Magnetic Resonance)信号,与谐振电路相比,文中接收前端具有无需重新调谐的优势,实验结果初步验证了该接收前端宽频探测的可行性。     

VHF／UHF波段接收机动态范围问题研究

针对VHF-HF波段接收机射频模拟前端（RFAF）对动态范围的影响问题,在多射频接收链路模型中添加中频自动增益控制（IFAGC）电路模块,仿真结果表明使用IFAGC电路进行二次增益调节,可保证接收机稳定工作,同时能够减小由RFAGC电路引起的瞬时动态范围的波动变化。     

基于SAW 技术的高精度频率测量仪设计与实现

设计了一种基于现场可编程门阵列(FPGA)等精度测频与自动增益控制(AGC)电路的高精度声表面波测量仪,该测量仪通过声表面波传感器采集声波并转化为电信号,通过AGC电路与施密特触发器对信号限幅、整形,将其转化为可测频率的方波,最后利用FPGA测频电路实现对频率的测量,并将结果传送至单片机显示。测试结果表明,该测量仪能测量频率100 Hz~100 kHz的信号,系统的最大测量误差为1.2%,测频范围广,精度高,稳定性好。     

基于0.18μm CMOS工艺2.5Gb/s宽动态范围光接收机前端放大电路设计

基于0.18μm CMOS工艺设计了适用于2.5Gb/s传输速率的宽动态范围光接收机前端放大电路（包括前置放大器和限幅放大器）.前置放大器采用了RGC输入级的跨阻放大器,并且应用了消直流电路和自动增益控制电路扩展输入动态范围.限幅放大器采用了按比例缩小尺寸、并联峰化和带有有源负反馈的Cherry-Hooper放大器等方法扩展带宽.仿真结果表明：前端放大电路的中频增益为116dBΩ,-3dB带宽为2.13GHz,输入信号动态范围为40dB（0.01～1mA）.     

An RF front-end with an automatic gain control technique for a U/V band CMMB receiver

This paper presents a fully integrated RF front-end with an automatic gain control(AGC) scheme and a digitally controlled radio frequency varied gain amplifier(RFVGA) for a U/V band China Mobile Multimedia Broadcasting(CMMB) direct conversion receiver.The RFVGA provides a gain range of 50 dB with a 1.6 dB step. The adopted AGC strategy could improve immunity to adjacent channel signal,which is of importance for CMMB application.The front-end,composed of a low noise amplifier(LNA),an RFVGA,a mixer and AGC,achieves an input referred 3rd order intercept point(IIP3) of 4.9 dBm with the LNA in low gain mode and the RFVGA in medium gain mode,and a less than 4 dB double side band noise figure with both the LNA and the RFVGA in high gain mode.The proposed RF front-end is fabricated in a 0.35μm SiGe BiCMOS technology and consumes 25.6 mA from a 3.0 V power supply.     

A 1.4-V 48-μW current-mode front-end circuit for analog hearing aids with frequency compensation

正A current-mode front-end circuit with low voltage and low power for analog hearing aids is presented. The circuit consists of a current-mode AGC(automatic gain control) and a current-mode adaptive filter.Compared with its conventional voltage-mode counterparts,the proposed front-end circuit has the identified features of frequency compensation based on the state space theory and continuous gain with an exponential characteristic.The frequency compensation which appears only in the DSP unit of the digital hearing aid can upgrade the performance of the analog hearing aid in the field of low-frequency hearing loss.The continuous gain should meet the requirement of any input amplitude level,while its exponential characteristic leads to a large input dynamic range in accordance with the dB SPL(sound pressure level).Furthermore,the front-end circuit also provides a discrete knee point and discrete compression ratio to allow for high calibration flexibility.These features can accommodate users whose ears have different pain thresholds.Taking advantage of the current-mode technique,the MOS transistors work in the subthreshold region so that the quiescent current is small.Moreover,the input current can be compressed to a low voltage signal for processing according to the compression principle from the current-domain to the voltage-domain.Therefore,the objective of low voltage and low power(48μW at 1.4 V) can be easily achieved in a high threshold-voltage CMOS process of 0.35μm(V_(TON) + |V_(TOP)|≈1.35 V).The THD is below -45 dB.The fabricated chip only occupies the area of 1×0.5 mm~2 and 1×1 mm~2.     

A robust analog interface system for submicron CMOS video DSP

This paper describes the front-end architecture for a fully integrated low-voltage CMOS video DSP function, including AGC, equalization, clamping, sync, and A/D conversion. With multiple clock domains and many high-activity pads, the large digital section of the IC generates high levels of substrate and power line noise, which cannot be avoided with quiet period sampling. The analog section is therefore designed to minimize the injected noise by other circuit techniques. The system maximizes the available dynamic range in the 3.3-V supply, with several high-bandwidth rail-to-rail functions. A novel arrangement with high noise immunity level estimators is used to clamp the video in the middle of the dynamic range of the input amplifier, hence reducing amplification of unwanted dc components. Extensive mixed signal test facilities are also included in the design. The chip is fabricated in 0.5-μm CMOS, and operates from a single 3.3-V supply     

A single-chip NMOS analog front-end LSI for modems

Presents a fully integrated analog front-end LSI chip which is an interface system between digital signal processors and existing analog telecommunication networks. The developed analog LSI chip includes many high level function blocks such as A/D and D/A converters with 11 bit resolution, various kinds of SCFs, an AGC circuit, an external control level adjuster, a carrier detector, and a zero crossing detector. Design techniques employed are mainly directed toward circuit size reductions. The LSI chip is fabricated in a 5 /spl mu/m line double polysilicon gate NMOS process. Chip size is 7.14/spl times/6.51 mm. The circuit operates on /spl plusmn/5 V power supplies. Typical power consumption is 270 mW. By using this analog front-end LSI chip and a digital signal processor, modern systems can be successfully constructed in a compact size.     

大动态范围抗干扰导航接收机AGC 电路性能分析与优化设计

导航接收机的特点是信号比较微弱,通常淹没于噪声以下,其入口电平的波动几乎都由干扰引起。针对这一特点,存在干扰情况下,要求接收机的噪声系数不能显著恶化。射频通道的噪声系数是制约接收机噪声系数的因素之一,本文在给定射频通道噪声系数恶化容限的条件下,以射频通道能实现最大动态范围为优化目标,分析了动态范围及各级电路增益的求解方法;进一步,针对特殊的纯电阻网络AGC 电路,得到了更为简洁的求解方法;最后,本文给出了该类AGC 电路动态范围的设计实例并进行了测试,设计预期与测试结果得到较好的吻合。本文虽然针对导航接收机设计,但可推广应用于指导各类接收机的设计。     

某型伪码测距雷达的数字AGC设计

论述了某航天器伪码测距雷达接收机外部AGC的设计原理和具体实现,并重点讨论了如何根据射频前端的输出来设计全数字AGC,来扩展接收机的动态范围.该文的讨论对于DS-SS（扩展频谱数字）接收机和伪码测距雷达接收机的数字AGC设计有参考意义.