通过FLIX指令结构提高可配置处理器计算性能

Xtensa LX处理器采用了Tensilica独创的可变长度指令扩展FLIX(Flexible Length Instruction eXtensions)体系结构,该体系结构是Xtensa指令集体系结构ISA的高效实现,它给设计人员以更多的选择去对系统设计的成本和性能进行折衷。FLIX技术为设计人员提供了灵活的方法,将单操作RISC指令、简单和复合操作TIE指令以及多操作FLIX指令自由地结合在一起。通过将多个操作封装在一个32位或者64位的宽指令字中,FLIX技术可以允许设计人员加速执行嵌入式应用程序中比较主要的“热点”代码,同时消除了超长指令字VLIW处理器体系结构中指令代码和系统性能方面的缺陷。     

基于触点及线圈指令的顺序功能图设计法

任何顺序控制问题都可用功能图来表示,当系统的功能图绘制好后,就可以使用PLC的有关指令将其转化为梯形图程序,通常可采用触点、线圈指令,置位复位指令,移位指令及专用的步进指令来实现将功能图转化为梯形图。本文介绍采用触点、线圈指令将顺序功能图转换成梯形图的方法。     

基于FPGA器件的高速数据适配器设计与实现

介绍了一种基于现场可编程门阵列(FPGA)器件设计高速数据适配器的方法，完成了4位高速数据流到8位较低速数据流的转换缓冲功能。给出基于仿真工具Modelsim的测试平台的建立方法，提供功能分析所用的仿真图，可以较快地发现设计中的缺陷和问题，给出了数据适配器的仿真图，经分析设计能够完成要求。     

数据流图在信息处理中的应用

简要介绍数据流图的基本成分及画图步骤,叙述了在信息处理系统中用数据流图分层进行软件分析的过程,阐述了应用数据流图的必要性．在信息处理系统中应用数据流图可提高软件分析的可见性和可控性,有助于软件缺陷在软件开发阶段早期被及时发现和消除．     

满足军用条件的集成CPU

与美国军用标准-1750A指令组的需要相适应的L64500CPU芯片为一个32位结构,能控制16,24和32位操作。除了注意各种整数形式外,这种芯片还能用16或32位方式或一个扩展的48位方式进行定点和浮点的数学运算。该器件由标准单元所组成,兼有数据,指令和I/O处理功能。一块姊妹电路MBU(L64550存贮控制和程序块保护单元)合并了1750A技术要求中的存贮控制、程序块保护、总线判断和几个任选功能。这两种芯片是采用1.5μm、两层金属CMOS工艺来制造的,其工作频率为15到25MHz。目前这种元件采用144脚、管脚     

GISEES:面向嵌入式系统的扩展指令集自动产生方法

 面向应用的指令集处理器通过增加扩展指令可有效提升处理器的性能,满足上市时间要求.然而为嵌入式系统定制扩展指令需解决以下3个问题:设计空间随应用复杂度的增加指数增加,有限的片上资源限制了扩展指令的数量和复杂度,现有指令集扩展算法复杂度高难以在嵌入式系统上运行.本文提出了一种快速的指令集扩展方法GISEES.该方法以应用的典型操作为中心产生扩展指令以裁剪了设计空间,并采用基于最大公共等价子串的资源共享策略减少资源开销和插入的多路选择器的数量.实验结果表明,该方法具有线性复杂度,可产生效率更高的扩展指令,更适合为嵌入式系统定制高效的扩展指令.     

基于四位嵌入式MCU的数字调谐系统DTS0614

介绍了一种基于４位微控制器的数字调谐系统－ＤＴＳ０６１４的功能框图及特点，并对其内核部分的结构、指令系统、微操作及指令数据流等作了分析。     

串行数据转换器接口

问:我现在需要安装节省空间的数据转换器,认为串行式转换器比较适合.为了选择和使用这种转换器,请问我尊要了解些什么?答:首先我们看一下串行接口的工作原理,然后再将它与并行接口相比较,从而可以消除对串行接口数据转换的神秘感.图1示出了一种8通道多路转换12位串行式模数转换器(ADC)AD7890与一种带串行接口的数字信号处理器(DSP)ADSP-2105接线图.图中还示出了使用DSP与ADC通信的时序图.通过一根线以串行数据流的形式传输12位转换结果.串行数据流还包括3位地址,用来表示AD7890当前被选中的多路转换器     

面向具有VLIW结构DSP的汇编级翻译的方法

为了简化不同体系结构间代码迁移工作,提出一种面向具有超长指令字架构的数字信号处理器的汇编级翻译的方法.前端分析将汇编代码中的指令信息同语义映射为机器无关的中间表示.采用路径探测法移除分支指令延迟槽构建指令流图,并重构源程序控制流图.基于各条指令的时间戳分配和指令间的数据依赖关系分析,移动代码和修改时间戳来线性化并行代码.实验证明,该方法能够正确翻译汇编程序.     

基于XCFG的BPEL数据流属性分析与验证

 BPEL组合服务实现了Web服务的复用和增值,但其复杂性带来了一定的挑战.例如,BPEL流程中正确的数据流对确保服务组合的正确性是十分重要的,然而现有的研究很少关注这类问题.本文提出一种基于扩展控制流图(XCFG)的BPEL流程数据流属性验证方法,利用XCFG对BPEL流程进行形式建模,设计相应的算法来分析和验证典型的数据流属性,如定义-使用一致性,无死锁和可达性.理论分析和实验均表明该方法是有效的.     

Determining the minimum iteration period of an algorithm

Digital signal processing algorithms are repetitive in nature. These algorithms are described by iterative data-flow graphs where nodes represent computations and edges represent communications. For all data-flow graphs, there exists a fundamental lower bound on the iteration period referred to as theiteration bound. Determining the iteration bound for signal processing algorithms described by iterative data-flow graphs is an important problem. In this paper we review two existing algorithms for determination of the iteration bound. Then we propose another novel method based on theminimum cycle mean algorithm to determine the iteration bound with a lower polynomial time complexity than the two existing techniques. It is convenient to represent many multi-rate signal processing algorithms by multi-rate data-flow graphs. The iteration bound of a multi-rate data-flow graph (MRDFG) can be determined by considering the single-rate data-flow graph (SRDFG) equivalent of the MRDFG. However, the equivalent single-rate data-flow graph contains many redundant nodes and edges. The iteration bound of the MRDFG can be determined faster if these redundancies in the equivalent SRDFG are first removed. A previous approach has considered elimination of edge redundancy. In this paper we present an approach to eliminatenode redundancy in the MRDFG. We combine elimination of node and edge redundancies to propose a novel algorithm for faster determination of the iteration bound of the MRDFG.This research was supported by the Advanced Research Projects Agency and monitored by Wright—Patterson AFB under contract number F33615-93-C-1309.     

Synthesis of control circuits in folded pipelined DSP architectures

A systematic folding transformation technique to fold any arbitrary signal processing algorithm data-flow graph to a hardware data-flow architecture, for a specified folding set and specified technology constraints, is presented. The folding set specifies the processor and the time partition at which the task is executed and is typically obtained by performing scheduling and resource allocation for the algorithm data-flow graph and the specified iteration period. The constraints imposed on the hardware architecture are also assumed to be known. The technique is used to derive the control circuitry of the hardware architecture. The authors derive conditions for the validity of a specified folding set, and present approaches to generate the dedicated architecture using systematic folding of tasks to operators. They propose automatic retiming and pipelining of algorithms described by data-flow graphs for folding. The folding algorithm is applied after preprocessing the data-flow graph for automated pipelining and retiming     

基于种类-位置模型的可重构资源指派方法

在基于指令集动态可扩展技术的可重构指令集处理器研究中,如何有效使用系统的可重构资源,将很大程度上影响扩展得到的定制指令的功能实现,进而影响系统性能的优化效果.本文针对可重构资源的利用问题,首先设计了一种可重构资源模型,该模型弱化了可重构资源的功能和数量属性,主要提供其种类和位置属性,并能够以此计算资源使用的时间属性.基于此模型,本文将图论中的图着色问题进行扩展,引入多遍着色的思想,提出了一种针对粗粒度可重构资源的资源指派算法,该算法将可重构资源的指派等价为一个图多遍着色问题,通过模型提供的属性参数和限制条件完成指派过程.实验结果验证了算法的有效性,并揭示了资源使用中的规律性,对提高资源利用率和系统性能具有一定的指导意义.     

Register Allocation—A Hierarchical Reduction Approach

A new approach to the problem of register allocation in high-level synthesis is presented. The algorithm employs a bottom-up transformational approach—sets of mutually exclusive variables in conditional branches are transformed into an equivalent set of nonmutually exclusive variables. The transformational approach is extended to the case of data-flow graphs with loops. A new register allocation algorithm is then used to produce an allocation for the nonmutually exclusive variables. From such an allocation, a corresponding allocation for the original set of mutually exclusive variables is derived. Our approach is particularly effective when there is a large number of nested conditional branches and loops in a data-flow graph.     

Compilation Methods for the Address Calculation Units of Embedded Processor Systems

An essential component of today's embedded system is an instruction-set processor running real-time software. All variations of these core components contain at least the minimum data-flow processing capabilities, while a certain class contain specialized units for highly data-intensive operations for Digital Signal Processing (DSP). For the required level of memory interaction, the parallel executing Address Calculation Unit (ACU) is often used to tune the architecture to the memory access characteristics of the application. The design of the ACU is performance critical. In today's typical design flow, this design task is somewhat driven by intuition as the transformation from application algorithm to architecture is complex and the exploration space is immense. Automatic utilities to aid the designer are essential; however, the key compilation techniques which map high-level language constructs onto addressing units have lagged far behind the emergence of these units. This paper presents a new retargetable approach and prototype tool for the analysis of array references and traversals for efficient use of ACUs. In addition to being an enhancement to existing compiler systems, the ArrSyn utility may be used as an aid to architecture exploration. A simple specification of the addressing resources and basic operations drives the available transformations and allows the designer to quickly evaluate the effects on speed and code size of his/her algorithm. Thus, the designer can tune the design of the ACU toward the application constraints. ArrSyn has been successfully used together with a C compiler developed for a VLIW architecture for an MPEG audio decoding application. The combination of these methods with the C compiler showed on average a 39% speedup and 29% code size reduction for a representative set of DSP benchmarks.     

Properties and Algorithms for Unfolding of Probabilistic Data-Flow Graphs

It is known that any selection statement (e.g. if and switch-case statements) in an application is associated with a probability which could either be predetermined by user input or chosen at runtime. Such a statement can be regarded as a computation node whose computation time is represented by a random variable. This paper focuses on iterative applications (containing loops) reflecting those uncertainties. Such an application can then be transformed to a probabilistic data-flow graph.Two timing models, the time-invariant and time-variant models, are introduced to characterize the nature of these applications. Since there can be many unfolding factors associated with each of the possible graph outcomes, for the time-invariant model, we propose a means of selecting a constant minimum rate-optimal unfolding factor for unfolding the probabilistic graph. We demonstrate that this factor guarantees the best schedule length.We also suggest a good estimate for choosing an unfolding factor for a graph under the time-variant model. Experiments show that using our selection scheme results in an iteration period close to the theoretical iteration bound of the experimental graph. Furthermore, this paper discusses an alternative approach which selects a few optimal schedules (with respect to the graph outcomes) to be stored in the system. The other possibilities will be represented by a modified template graph.     

Component selection for high-performance pipelines

The use of a realistic component library with multiple implementations of operators results in cost-efficient designs; slow components can then be used on noncritical paths and the more expensive components on only the critical paths. This paper presents a cost-optimized algorithm for selecting components and pipelining a data-flow graph, given such a library, and throughput and latency constraints. Experimental results on several large examples indicate the importance of component selection as a parameter in design exploration     

Bayes analysis for fault location in distributed systems

The authors propose a simple and practical probabilistic model, using multiple incomplete test concepts, for fault location in distributed systems using a Bayes analysis procedure. Since it is easier to compare test results among processing units, their model is comparison-based. This approach is realistic and complete in the sense that it does not assume conditions such as permanently faulty units, complete tests, and perfect or nonmalicious environments. It can handle, without any overhead, fault-free systems so that the test procedure can be used to monitor a functioning system. Given a system S with a specific test graph, the corresponding conditional distribution between the comparison test results (syndrome) and the fault patterns of S can be generated. To avoid the complex global Bayes estimation process, the authors develop a simple bitwise Bayes algorithm for fault location of S, which locates system failures with linear complexity, making it suitable for hard real-time systems. Hence, their approach is appealing both from the practical and theoretical points of view     

Background memory area estimation for multidimensional signalprocessing systems

Memory cost is responsible for a large amount of the chip and/or board area of customized video and image processing system realizations. In this paper, we present a novel technique-founded on data-flow analysis which allows one to address the problem of background memory size evaluation for a given nonprocedural algorithm specification, operating on multidimensional signals with affine indexes. Most of the target applications are characterized by a huge number of signals, so a new polyhedral data-flow model operating on groups of scalar signals is proposed. These groups are obtained by a novel analytical partitioning technique, allowing to select a desired granularity, depending on the application complexity. The method incorporates a way to tradeoff memory size with computational and controller complexity     

Resource-constrained loop list scheduler for DSP algorithms

We present a new algorithm for resource-constrained scheduling for digital signal processing (DSP) applications when the number of processors is fixed and the objective is to obtain a schedule with the minimum iteration period. This type of scheduling is best suited for moderate speed applications where conservation of area and power is more important than speed. We define and make use of newgraph dependent constraints to obtain a lower bound estimate on the iteration period for any data-flow graph. By satisfying these constraints before performing the scheduling task, we can restrict the design space and can generate valid schedules in less time than previously reported. The graph dependent constraints provide a more accurate lower bound estimate on the iteration period than previously published results. This new scheduling algorithm exploits the iterative nature of DSP algorithms and uses aniterative-loop based scheduling approach. This resource scheduling algorithm has been incorporated in the Minnesota ARchitecture Synthesis (MARS) system. Our approach exploits inter-iteration and intra-iteration precedence constraints and incorporates implicit retiming and pipelining to generate optimal and near optimal schedules.This research was supported by the Advanced Research Projects Agency under grant number F33615-93-C-1309 and the office of Naval Research under contract number N00014-91-J-1008.