钟控准静态能量回收逻辑电路

钟控准静态能量回收逻辑(clocked quasi-static energy recovery logic,CQSERL)只在输入信号导致输出状态发生变化的情况下才对电路节点充电(或者回收),不需要在每个功率时钟周期循环充电和回收操作;CQSERL是单端输入输出逻辑,减小了电路实现代价.设计了4位QSERL串行进位加法器(RCA)电路,和相应的CMOS电路进行了功耗比较.功率时钟为10MHz时,CQSERL电路功耗是对应CMOS电路的35%.流片实现了一个简单结构的正弦功率时钟产生电路,功率时钟的频率和相位与外接系统时钟相同.     

能量回收阈值逻辑及其功率时钟产生电路

提出了能量回收阈值逻辑电路(ERTL).该电路把阈值逻辑应用到绝热电路中,降低能耗的同时也降低了电路的门复杂度.并且提出了一种高效率的功率时钟产生电路.该功率时钟电路能够根据逻辑的复杂度和工作频率,调整电路中MOS开关的开启时间,以取得最优的能量效率.为了便于功率时钟的优化设计,推导出了闭式结果.基于0.35μm的工艺参数,设计并且仿真了ERTL可编程逻辑阵列(PLA)和普通结构PLA.在20～100MHz的工作频率范围内,提出的功率时钟电路的能量效率可以达到77%～85%.仿真结果还显示,ERTL是一个低能耗的逻辑.ERTL PLA与普通结构的PLA相比,包括功率时钟电路的功耗在内,ERTL PLA仍节省65%～77%的功耗.     

准静态单相能量回收逻辑

提出了一种新的准静态单相能量回收逻辑,其不同于以往的能量回收逻辑,真正实现了单相功率时钟,且不需要任何额外的辅助控制时钟,不但降低了能耗,更大大简化了时钟树的设计.该逻辑还可以达到两相能量回收逻辑所具有的速度.设计了一个8位对数超前进位加法器,并分别用传统的静态CMOS逻辑、钟控CMOS绝热逻辑(典型的单相能量回收逻辑)和准静态单相能量回收逻辑实现.采用128组随机产生的输入测试向量的仿真结果表明:输入频率为10MHz时,准静态能量回收逻辑的能耗仅仅是传统静态CMOS逻辑的45%;当输入频率大于2MHz时,可以获得比时钟控CMOS绝热逻辑更低的能耗.     

准静态单相能量回收逻辑

提出了一种新的准静态单相能量回收逻辑,其不同于以往的能量回收逻辑,真正实现了单相功率时钟,且不需要任何额外的辅助控制时钟,不但降低了能耗,更大大简化了时钟树的设计.该逻辑还可以达到两相能量回收逻辑所具有的速度.设计了一个8位对数超前进位加法器,并分别用传统的静态CMOS逻辑、钟控CMOS绝热逻辑(典型的单相能量回收逻辑)和准静态单相能量回收逻辑实现.采用128组随机产生的输入测试向量的仿真结果表明:输入频率为10MHz时,准静态能量回收逻辑的能耗仅仅是传统静态CMOS逻辑的45%;当输入频率大于2MHz时,可以获得比时钟控CMOS绝热逻辑更低的能耗.     

用于能量回收逻辑的正弦功率时钟电路

分析了功率时钟对电容负载充电与回收的物理过程，研完了正弦功率时钟产生电路的基本结构，考虑了功率时钟的频率与相位的稳定性。在此基础上，提出了稳定功率时钟频率与相位的功率时钟产生电路，即接入外部参考时钟，使振荡电路与参考时钟同步。用0．8μm DPDM CMOS工艺实现了一个简化的两相正弦功率时钟产生电路，通过物理测试，验证了电路的工作原理。     

150Ms/s、6bit CMOS数字工艺折叠、电流插值A/D转换器

在1.2μm SPDM标准数字CMOS工艺条件下,实现6bit CMOS折叠、电流插值A/D转换器;提出高速度再生型电流比较器的改进结构,使A/D转换器(ADC)总功耗下降近30%;提出一种逻辑简单易于扩展的解码电路,以多米诺(Domino)逻辑实现.整个ADC电路中只使用单一时钟.在5V电压条件下,仿真结果为采样频率150-Ms/s时功耗小于185mW,输入模拟信号和二进制输出码之间延迟小于2个时钟周期.     

150Ms/s、6bit CMOS数字工艺折叠、电流插值A/D转换器

在1.2μm SPDM标准数字CMOS工艺条件下,实现6bit CMOS折叠、电流插值A/D转换器;提出高速度再生型电流比较器的改进结构,使A/D转换器(ADC)总功耗下降近30%;提出一种逻辑简单易于扩展的解码电路,以多米诺(Domino)逻辑实现.整个ADC电路中只使用单一时钟.在5V电压条件下,仿真结果为采样频率150-Ms/s时功耗小于185mW,输入模拟信号和二进制输出码之间延迟小于2个时钟周期.     

基于绝热逻辑的低功耗乘法器电路设计

基于绝热开关理论的能量回收逻辑与传统的静态CMOS逻辑相比,能够大大减少电路的功率消耗。这里介绍了一种使用单相正弦电源时钟的能量回收逻辑,分别用静态CMOS逻辑和这种能量回收逻辑设计,并仿真了一个两位乘法器电路,比较了这两种电路的性能。研究表明,采用能量回收逻辑设计的乘法器显著降低了电路的功率消耗。     

二种EPAL绝热开关电路

研究和设计了两种低功耗的EPAL(efficient PAL)绝热开关电路.这两种电路均采用逐级相位落后90°的四相正弦功率时钟.讨论了EPAL电路的设计方法,并在不同时钟频率和不同的负载条件下用1.2μm的CMOS工艺参数对所设计的电路进行PSPICE模拟.模拟结果表明这两类电路均能完成正确的逻辑功能.两种EPAL的五级反相器/缓冲器电路在功率时钟频率为10MHz时都比相应的PAL-2N电路节省80%以上的功耗,在400MHz时功耗节省也分别可达23%和50%.EPAL电路可以工作于更高的时钟频率,有更强的驱动负载能力和更低的输出波形畸变.     

二种EPAL绝热开关电路

研究和设计了两种低功耗的EPAL(efficientPAL)绝热开关电路.这两种电路均采用逐级相位落后90°的四相正弦功率时钟.讨论了EPAL电路的设计方法,并在不同时钟频率和不同的负载条件下用1.2μm的CMOS工艺参数对所设计的电路进行PSPICE模拟.模拟结果表明这两类电路均能完成正确的逻辑功能.两种EPAL的五级反相器/缓冲器电路在功率时钟频率为10MHz时都比相应的PAL-2N电路节省80%以上的功耗,在400MHz时功耗节省也分别可达23%和50%.EPAL电路可以工作于更高的时钟频率,有更强的驱动负载能力和更低的输出波形畸变     

QSERL: quasi-static energy recovery logic

A new quasi-static energy recovery logic family (QSERL) using the principle of adiabatic switching is proposed in this paper. Most of the previously proposed adiabatic logic styles are dynamic and require complex clocking schemes. The proposed QSERL uses two complementary sinusoidal supply clocks and resembles the behavior of static CMOS. Thus, switching activity is significantly lower than dynamic logic. In addition, QSERL circuits can be directly derived from static CMOS circuits. A high-efficiency clock generation circuitry, which generates two complementary sinusoidal clocks compatible to QSERL, is also presented in this paper. The adiabatic clock circuitry locks the frequency of clock signals, which makes it possible to integrate adiabatic modules into a VLSI system. We have designed an 8×8 carry-save multiplier using QSERL logic and two phase sinusoidal clocks. SPICE simulation shows that the QSERL multiplier can save 34% of energy over static CMOS multiplier at 100 MHz     

Performance analysis of a complete adiabatic logic system driven by the proposed power clock generator

We analyze the energy performance of a complete adiabatic circuit/system including the Power Clock Generator （PCG） at the 90 nm CMOS technology node. The energy performance in terms of the conversion efficiency of the PCG is extensively carried out under the variations of supply voltage, process comer and the driver transistor＇s width. We propose an energy-efficient singe cycle control circuit based on the two-stage comparator for the synchronous charge recovery sinusoidal power clock generator （PCG）. The proposed PCG is used to drive the 4-bit adiabatic Ripple Carry Adder （RCA） and their simulation results are compared with the adiabatic RCA driven by the reported PCG. We have also simulated the logically equivalent static CMOS RCA circuit to compare the energy saving of adiabatic and non-adiabatic logic circuits. In the clock frequency range from 25 MHz to 1GHz, the proposed PCG gives a maximum conversion efficiency of 56.48%. This research work shows how the design of an efficient PCG increases the energy saving of adiabatic logic.     

Analysis and Design of an Efficient Irreversible Energy Recovery Logic in 0.18-$mu$m CMOS

This paper presents the design and experimental evaluation of a new type of irreversible energy recovery logic (ERL) families called complementary energy path adiabatic logic (CEPAL). It inherits the advantages of quasi-static ERL (QSERL) family, but is with improved driving ability and circuit robustness. The proposed logic style features no hold phase compared to its QSERL counterpart under the same operation conditions; thereupon no feedback keeper is required so that considerable improvements in area and power overheads can be achieved. Moreover, its throughput becomes twice as high as that of QSERL when their frequencies of power clocks (PCs) are identical. Results on the impact of variation on CEPAL are provided. Comparison between CEPAL and other known low-power logic style achieving iso-performance, namely, subthreshold logic is also given. In order to demonstrate workability of the newly developed circuit, an 8-bit shift register, designed in the proposed techniques, has been fabricated in a TSMC 0.18- $mu$m CMOS process. Both simulation and measurement results verify the functionality of such a logic, making it suitable for implementing energy-aware and performance-efficient very-large scale integration (VLSI) circuitry.      

A Low Power 16‐Bit RISC Microprocessor Using ECRL Circuits

This paper presents a low power 16‐bit adiabatic reduced instruction set computer (RISC) microprocessor with efficient charge recovery logic (ECRL) registers. The processor consists of registers, a control block, a register file, a program counter, and an arithmetic and logical unit (ALU). Adiabatic circuits based on ECRL are designed using a 0.35 µm CMOS technology. An adiabatic latch based on ECRL is proposed for signal interfaces for the first time, and an efficient four‐phase supply clock generator is designed to provide power for the adiabatic processor. A static CMOS processor with the same architecture is designed to compare the energy consumption of adiabatic and non‐adiabatic microprocessors. Simulation results show that the power consumption of the adiabatic microprocessor is about 1/3 compared to that of the static CMOS microprocessor.     

A CMOS mixed-signal clock and data recovery circuit for OIF CEI-6G+ backplane transceiver

A CMOS low-power mixed-signal clock and data recovery circuit is presented in this paper. It is designed for OIF CEI-6G+ LR backplane transceiver, and consists of a phase detector, loop filter, phase control logic, and phase interpolator. A unique subsampled architecture makes it possible for a low-power mixed-signal clock recovery loop running at a rate of 6 Gb/s. The proposed architecture has data pattern independent loop bandwidth. Fabricated in a 0.13-/spl mu/m CMOS technology in an area of 280/spl times/100 /spl mu/m/sup 2/, the clock and data recovery loop exhibits a frequency tracking range up to 2000 ppm. The bit error rate is less than 10/sup -12/ with a pseudorandom bit sequence of length 2/sup 31/-1. The power dissipation is 24 mW for clock and data recovery circuits from a single 1.2-V supply.     

一种用于DSCRL绝热电路的新型功率时钟

提出了一种用于DSCRL(双摆幅电荷恢复逻辑)绝热电路的新型四相功率时钟,该功率时钟采用了非对称的方法来优化其时序,比已提出的采用对称技术来优化时序的六相功率时钟更简洁.这种新型的功率时钟用于DSCRL绝热电路后,该电路仍然保持了其能量恢复的高效性,同时还降低了电路设计的复杂性,这一结论已被文中的HSPICE 模拟结果证明.     

一种用于DSCRL绝热电路的新型功率时钟

提出了一种用于DSCRL(双摆幅电荷恢复逻辑)绝热电路的新型四相功率时钟,该功率时钟采用了非对称的方法来优化其时序,比已提出的采用对称技术来优化时序的六相功率时钟更简洁.这种新型的功率时钟用于DSCRL绝热电路后,该电路仍然保持了其能量恢复的高效性,同时还降低了电路设计的复杂性,这一结论已被文中的HSPICE 模拟结果证明.