静态时序分析在高速FPGA设计中的应用

介绍了采用STA(静态时序分析)对FPGA(现场可编程门阵列)设计进行时序验证的基本原理,并介绍了几种与STA相关联的时序约束.针对时序不满足的情况,提出了几种常用的促进时序收敛的方法.结合设计实例,阐明了STA在高速、大规模FPGA开发中的应用.实践表明,随着数字设计复杂度的增加,在后端的时序验证环节,与传统的动态门级时序仿真相比,采用STA方法的优势在于可以全面、高效地完成验证任务.     

深亚微米ASIC设计中的时序约束与静态时序分析

在现代深亚微米专用集成电路(ASIC)设计流程中,为使电路性能达到设计者的预期目标,并满足电路工作环境的要求,必须对一个电路设计进行诸如时序、面积、负载等多方面的约束,并自始至终使用这些约束条件来驱动电路设计软件的工作.文中介绍了设计中所需考虑的各种时序约束,并以同步数字系列(SDH)传输系统中8路VC12-VC4 E1映射电路设计为例,详细说明了设计中所采用的时序约束,并通过静态时序分析(STA)方法使电路时序收敛得到了很好的验证.     

Path-Based静态时序分析方法

随着半导体特征工艺尺寸的缩小,IC芯片的物理参数和电学参数的波动越来越明显,特别是在高速芯片的设计中,那些满足简单功能性验证的芯片,就有可能由于时序的不满足导致厂商莫大的损失.重点在于给芯片设计者一个简要的静态时序分析(Static Timing Analysis简称STA)的概况.通过一个简单的例子,主要阐述了:面对伴随着半导体工艺特征尺寸缩小而来的时序问题,STA各自不同的分析算法及其对分析结果的影响;以及真正设计过程中如何借助EDA工具与约束文件实现这样的算法.期望给予所有的IC设计者关于STA的一个大致了解.使得其在整个设计过程中都能够考虑到时序问题.并且使用合适的分析算法,从而有效提高芯片的良率.     

统计学在数字电路后端时序分析中的应用

随着半导体工艺技术的不断进步,芯片制造中的工艺变量,越来越难以控制。于是,数字电路后端设计对时序分析提出了更多的要求。越来越多的进程、电源电压、温度（PVT）等工艺角（corner）传统的静态时序分析方法（STA）变得越来越难以精确地估计制程变异（variation）对于设计性能的影响。在本文中,将会介绍一种新的基于统计学的时序分析方法：Statistical Static Timing Analysis （SSTA）。通过一组附加的数据：精确的制程变异描述文件、统计学标准的库文件,SSTA有望在未来取代传统的静态时序分析方法,从而更好的驾驭越来越先进的半导体工艺技术,以及千万门级高速芯片的设计要求。     

基于MCMM技术快速实现IC时序收敛

如今的集成电路(Integrated Circuit,IC)设计往往要求芯片包含多个工作模式,并且在不同工艺角(corner)下能正常工作。工艺角和工作模式的增加,无疑使时序收敛面临极大挑战。本文介绍了一种在多工艺角多工作模式下快速实现时序收敛的技术——MCMM(Multicorner-Multimode)技术,该技术将工艺角和模式进行组合,对时序同时进行分析和优化,到达快速实现时序收敛的目的。该技术应用于一个80万门基于TSMC 0.152μm logic工艺的电力网载波通信(PLC)芯片设计,设计实例表明,利用MCMM技术不但可以解决时序难以收敛的问题,而且大大降低了芯片设计周期。     

基于FPGA的高速AD采集设计

基于FPGA和一款高速模/数(A/D)转换芯片AD7356设计一种高速数据采集方法,给出AD7356的时序并基于PFGA程序开发软件Xilinx公司的ISE来控制AD的时序转换关系,最后通过ModelSim软件来实现对AD工作时序的仿真以及通过上位机来实现对模拟信号波形的还原,通过仿真结果证明其工作时序正确性以及硬件系统工作的正确性,能够满足高速数据采集要求。     

KAI-2093型面阵CCD多模式驱动时序设计

针对某航空相机的设计要求,提出了一种可行的多模式驱动时序设计方法。采用柯达公司的KAI-2093行间转移型面阵CCD传感器,结合它的结构特点和双通道数据传输的思想分析了传感器驱动时序关系,提出了3种驱动模式:binning、no-binning和TDI模式。以Altera公司的FPGA芯片EP1C6Q240作为时序发生器并实现数据的缓存和拼接,从而实现了时序发生器与数据处理器的一体化设计。在QUARTUSII7.0开发环境下采用VHDL语言编程,通过Modelsim AE6.1b实现数据缓存器的仿真。实测结果表明,所设计的驱动时序满足KAI-2093的时序要求,binning模式下帧频可达60帧/s,120帧/s等,满足高速跟踪要求;no-binning模式下全帧输出帧频可达30帧/s;TDI模式下能保证CCD长时间工作而不影响成像质量,该设计方法提高了系统的集成度和抗干扰能力。     

片上系统验证研究

在数字IC设计中，通常情况下，一般功能芯片验证只涉及到单方面的验证，比如功能仿真、静态时序分析(STA)等。片上系统(SOC)的验证，则是结合了各种验证，而且需要不同于一般功能芯片验证的验证方法，比如软硬件协同验证、FPGA验证、基于IP的验证，等等。文章对这三种验证方法进行了详细的论述。     

通用的全帧型面阵CCD时序发生器设计方法

介绍了面阵CCD485的内部结构、工作模式,并给出了其基本驱动电路设计。然后通过对面CCD485驱动时序图的分析,分析了全帧型大面阵CCD 的正常工作、快速擦除、图像窗口输出和像元合并的驱动时序,提出了一种基于时序细分和有限状态机的通用型全帧型面阵CCD驱动时序发生器设计方法。该方法通过对CCD 驱动时序进行分组,将每一组时序的波形划分为若干个基本输出状态,这样CCD 各个工作阶段所需的驱动时序都可以由各基本状态组合出来,使用摩尔型有限状态机来描述,将时序驱动器进行了模块化设计。给出了各个模块的具体设计,使时序发生器的设计过程更加简单,最后采用Xilinx公司的Virtex-ⅡPro系列FPGA-XC2VP20、ISE软件平台,设计了CCD驱动时序发生器,并进行了波形仿真分析。输出信号完全满足485芯片的驱动时序要求,证明了该设计方法的有效性。     

一种时序精确的集成电路网络应用系统建模与仿真环境

新型复杂的系统集成电路芯片(SOC)常常应用于网络环境中，因此需要对其所处网络环境建模与仿真，这意味着要能够对芯片同时进行网络建模和传统的系统级的建模。本论文介绍了一种时序精确的建模与仿真方法，它集成了系统建模语言(SystermC)和网络仿真环境(NS-2)，使用这种集成建模与仿真环境可以显著地加速具有网络通信需求的芯片的设计过程。     

一种基于机器学习的众工艺角延迟预测方法

在不同工艺角下,关键路径呈现显著差异,因此需要进行大量的静态时序分析,从而导致时序分析运行时间较长。与此同时,随着工艺尺寸的缩小,静态时序分析的精度问题变得不容忽视。本文提出一种基于机器学习的适用于众工艺角下的延迟预测方法,考虑工艺、电压和温度对时序的影响,利用基于自注意力Transformer模型对关键路径进行全局聚合编码,预测众工艺角下关键路径的统计延迟。在EPFL基准电路下进行验证,结果表明该方法的平均绝对误差范围为5.8%～9.4%,有良好的预测性能,可以提高时序分析的准确度和效率,进而缩短数字电路设计周期和设计成本。     

Unified Convolutional/Turbo Decoder Design Using Tile-Based Timing Analysis of VA/MAP Kernel

To satisfy the advanced forward-error-correction (FEC) standards, in which the Convolutional code and Turbo code may co-exit, a prototype design of a unified Convolutional/Turbo decoder is proposed. In this paper, we systematically analyze the timing charts of both the Viterbi algorithm and the MAP algorithm. Then, three techniques, including Distribution, Pointer, and Parallel schemes, are introduced; they can be used as flexible tools in timing-chart analysis to either reduce memory size or to increase throughput rate. Furthermore, we propose a tile-based methodology to analyze the key features of timing charts, such as computing/memory units and hardware utilization. On the basis of the timing analysis, we developed a VA/MAP timing chart that has three modes (VA mode, MAP mode, and concurrent VA/MAP mode) by complementing the idle time of both VA and MAP decoding procedures. The new combined timing analysis helps us for constructing a unified component decoder with near 100% utilization rate of the processing element (PE) in both VA/MAP decoding functions.      

A gate-delay model focusing on current fluctuation over wide range of process–voltage–temperature variations

This paper proposes a gate-delay model suitable for timing analysis that takes into consideration wide-ranging process–voltage–temperature (PVT) variations. The proposed model translates an output-current fluctuation due to PVT variations into modifications of the output load and input waveform. After translation, any conventional model can compute delay taking into account PVT variations by using the modified output load and reshaped input waveform. Experimental results with 90- and 45-nm technologies demonstrate that the average error of the fall and rise delay estimation in single- and multi-stage gates was approximately 5% on average over a wide range of input slews, output loads, and PVT variations. The proposed model can be used in Monte Carlo STA (static timing analysis) in addition to corner-based timing analysis. It can be also used in statistical STA to calculate the sensitivities of delays to variation parameters on-the-fly even when the nominal operating condition changes as well.     

Cramer–Rao lower bounds and maximum likelihood timing synchronization for dirty template UWB communications

Timing acquisition constitutes a major challenge in realizing ultra-wideband communications. In this paper, we propose the timing with dirty template (TDT) approach as a promising candidate for achieving rapid, accurate and low-complexity acquisition. We describe the dirty template (DT) technique, in order to develop and test timing algorithms in both modes: data-aided (DA) and non-data- aided (NDA) modes. First, we derive the Cramer–Rao lower bound, which is used as a fundamental performance limit for any timing estimator. Next, the TDT acquisition estimator is achieved by using the Maximum Likelihood concept. Then we propose a new method, based on Time-Hoping codes, to improve the performance estimation of the original dirty template algorithms. Simulation shows the estimation error results of the modified method in the DA and NDA modes. It confirms the high performance and fast timing acquisition of DA mode, compared with NDA mode, but with less bandwidth efficiency.     

基于合同网模型的多代理协作研究

传统的合同网模型通过招标服务代理和投标服务代理之间的招投标,可以在Internet这样的开放异构环境下实现任务的协作求解.但传统合同网模型也存在一些如协作过程中网络通信量较大以及对服务代理能力和负载变化缺乏适应性等问题.为此,本文提出了等级域和时间消耗的概念,并将其引入到传统合同网中,建立了一个基于等级域和时间消耗的合同网模型.根据服务代理的能力和协作成功率,在传统合同网功能域中划分了三个等级域,使得服务代理间的协作大量发生在第一等级,同时在选择服务代理时,考虑了其时间消耗的因素.理论分析和实验表明,这个新模型能够降低查找协作服务范围,降低协作求解过程中的通信量,而且能使系统中服务代理的负载更均衡.     

Failure physics of integrated circuits — A review

This paper is a review of the most important results on failure physics of integrated circuits, as a synthesis of what has been recently encountered in the literature concerned with these problems.In the first part of the paper systematization of failure modes in integrated circuits is accomplished so that all failure modes are divided into four groups according to their origin: (i) failure modes associated with chip; (ii) failure modes resulting from leads and bonds; (iii) failure modes associated with encapsulation; and (iv) failure modes due to external effects and overstress. Also, some typical failure mode distributions of different types of integrated circuits are given and the effects of the changeover from LSI to VLSI on failure mode distributions are discussed.In the second part of the paper the most important tests for enhancing of the failure modes are enumerated and relationship between the failure modes and the tests for their detection is given. Also, the role of electrical testing by the curve tracer and the accompanying analytical techniques (scanning electron microscopy, transmission electron microscopy, electron beam microprobe, Auger electron spectroscopy and X-ray radiograph) are discussed. Finally, the diagnostic technique is described which, using simple electrical testing by the curve tracer and some tests for enhancing of the failure modes (high temperature bake and high temperature burn-in), enables simple detection of integrated circuit failure modes.In the third part of the paper a survey of test structures for failure analysis of integrated circuits is made. Test structures are divided into three groups according to the kind of the failure mode tested by them. First, the test structures for the analysis of the failures due to the process induced defects are described. Then, the test structures for the analysis of the failures due to traps at the interface silicon-oxide and mobile alcali ions in oxide are discussed. Finally, the test structures for the analysis of the metallization failures are considered.     

一种新型的低泄漏功耗FPGAs查找表

提出了一种新型的低泄漏功耗FPGAs查找表（Look-up Tables，LUTs）结构。这种结构的LUTs可以工作在三种不同的模式：高速工作模式、省电模式以及睡眠模式。在高速工作模式时。此LUTs具有与传统的LUTs类似的性能和功耗。在省电模式下。通过牺牲电路的速度来实现降低功耗的目的，泄漏功耗与高速工作模式相比可以减小约68％-73％。而在睡眠模式下，泄渭功耗更是可以减小95％以上。     

A yield improvement technique in severe process,voltage, and temperature variations and extreme voltage scaling

Drastic yield reduction at sub/nearthreshold voltage domains, caused by the severe process, voltage, and temperature (PVT) variations in this region, is challenging characteristic of recent nanometre sensory chips. Using a variation sensitive and ultra-low-power design, this paper proposes a novel technique capable of sensing and responding to PVT variations by providing an appropriate forward body bias (FBB) so that the delay variations and timing yield of whole system as well as energy-delay product (EDP) are improved. Theoretical analysis for the error probability, confirmed by post-layout HSPICE simulations for an 8-bit Kogge–Stone adder and also two large Fast Fourier Transform (FFT) processors, shows considerable improvements in severe PVT variations and extreme voltage scaling. For this adder, for example, the proposed technique can reduce error rate from 50% to 1% at 0.4 V. In another implementation, in average ∼7× delay variation and ∼4× EDP improvement is gained after this technique is applied to an iterative 1024pt, radix 4, complex FFT while working in sub/nearthreshold voltage region of 0.3 V–0.6 V. Also, pipelined version of the FFT consumed only 412pJ/FFT at 0.4 V while processing 125 K FFT/sec.