基于约束图的版图压缩算法

本文在简评各种版图压缩方法，重点介绍了基于约束图模型的压缩算法，包括约束图建立、约束图求解以及约束图在二维压缩中的运用。     

可编程逻辑阵列（PLA）自动版图生成器

可编程逻辑阵列ＰＬＡ自动版图生成器可以使设计者快速地得到宏单元，从电路盒物理版图的细节中解放出来，因ＰＬＡ较低的设计费用和可编程的特点，生成器对于实现电路中的控制部分十分有效，ＰＬＡ自动版图生成器在国内首次实现了ＰＬＡ由逻辑输入到版图生成的自动设计。     

实用版图压缩算法

本文给出了两种基于约束图的一维版图压缩算法,即完全约束图压缩算法和精简约束图压缩算法,并对两个算法的性能做了讨论;针对版图中较常用的曼哈顿多边形图形,文中还给出了相应的解决办法。     

具有边界约束的LSI模块版图自动生成系统

本文介绍了一个具有边界约束的大规模集成电路模块版图自动生成系统（ＡＭＧＣ）。ＡＭＧＣ的输入为模块的电路网表，输出为模块的ＣＭＯＳ版图数据。由ＡＭＧＣ自动生成的版图既符合用户的设计规则，也符合模块输入输出端口位置及长宽比等用户给出的约束条件。     

LTE终端用户平面数据传输的研究与设计

LTE的用户平面包括实现用户数据传输的层2的所有子层,针对3GPP发布的LTE Release 8标准,研究了LTE空中接口协议栈用户平面的结构与设计机制。首先主要介绍了LTE用户平面的总体结构以及各层功能,然后详细阐述了终端用户平面的数据传输过程及原理。缓冲区如何设计对于系统的稳定性和高效性有很大影响,最后设计了一种开辟缓冲区的方法以及信号传输流程,并在SDL环境中生成了MSC图,验证了流程设计的可行性。     

超深亚微米数字集成电路版图验证技术

在超深亚微米工艺中,数字集成电路版图设计由以前简单的物理验证进入到复杂的版图验证阶段。版图验证包含时序验证、形式验证和物理验证。时序验证进行电压降分析和时序分析,确保时序收敛;形式验证进行两个网表的逻辑等效检查;物理验证进行可制造性、可靠性和设计规则检查,确保版图符合可制造性工艺规则和电路规则。三种验证技术共同指导并约束着数字集成电路的物理实现,灵活配置相关版图验证技术可进一步加快版图验证的进度。     

基于生成图的工作流多过程动态 时序一致性验证方法

 提出了基于生成图的多过程动态时序一致性验证方法.首先从多过程的时间工作流网构建生成图,以图形化方式表达实例可能经过的路径和时间信息.在动态检测时,依据已经完成活动对生成图进行部分更新,再利用图中节点相关信息进行时间约束的验证.该方法可以解决资源约束情况下多过程时序一致性动态验证问题,而且能定位模型中出问题的路径,指导用户进行工作流时序异常处理或优化工作流模型;另一方面,生成图可供多个时序约束进行验证使用,具有较好的可重用性.     

信号流驱动的模拟电路版图综合方法

提出了一种新的基于信号流分析的模拟电路版图综合方法.电路分析子系统采用新提出的信号流分析方法再结合已有的电路拓扑分析和电路灵敏性分析方法生成布图约束控制电路性能的衰减.由于考虑了电路中有关信号流的启发式信息,该方法的复杂性较一般的纯粹性能驱动方法小.然后分别在器件生成子系统、布图子系统和布线子系统中实现这些约束,使得这些约束在最容易实现的阶段得到满足.实际的电路例子已经证明了这一方法可以获得出色的电路性能.     

MGS—CMOS宏单元模块自动生成系统

本文介绍一个CMOS宏单元模块自动生成系统,该系统根据宏单元的电路描述,经过逻辑综合后自动完成布局、布线工作。并将布图结果转换成版图描述文件,从而实现了宏单元建库及模块生成的自动化。为了保证布通率及生成模块的正确性,系统提供了交互布图环境和模块正确性验证工具。     

局域动态一维版图压缩算法及其实现

本文给出了一种基于设计规则检查之上的一维版图压缩算法——局部的动态的一维压缩算法RDOC。这是一种特别适合于物理版图的算法,该算法建立约束图的运算时间是线性的,较以前的阴影传播法、垂直平面扫描法快,提高了压缩效率;本文还介绍了为实现该算法而开发的用于单元级版图的压缩程序,它允许用户按其需要对设计规则进行放大或缩小。最后给出了标准单元的压缩实例。     

计算机辅助激光切割布局系统的研发

针对激光切割机切割板材的特点,开发了计算机辅助激光切割布局系统。论文介绍了计算机辅助优化布局的相关基本知识,阐述了计算机辅助系统的优化算法,描述了系统的界面,输入方式,使用方法;并利用开发的系统做了8组随机仿真布局试验,给出了两组布局方案图。试验结果表明:利用开发的系统可以快速生成材料利用率高的优化布局图。按照布局图对板材进行布局设计,可以大大提高材料的利用率,降低生产成本,提高企业利润。     

Automated hierarchical CMOS analog circuit stack generation withintramodule connectivity and matching considerations

An efficient automated layout for CMOS transistors in analog circuits is described. The matching requirements are used as the primary constraint on the analog layout; however, parasitic capacitances and area considerations are also included. A designer-chosen arbitrary circuit partition from the schematic can be used to generate the corresponding layout as an optimum stack of transistors with complete intramodule connectivity. The transistor stack generation is performed by representing the circuit with a diffusion graph and recursively fragmenting the graph until the base constructs are reached. For each of the modules, the port structures are also created. These port structures are considered as part of the module area and parasitic optimization procedure. With aspect-ratio-related constraints, the procedure allows optimal floorplanning. The results are demonstrated through several examples     

On the theorem of generating Hamilton circuits and its applications

The study of the algorithm by the author for generating all the Hamilton circuits in a graph by a method of Wang algebra is continued. In order to simplify the algorithm, a theorem of the constraint of degrees in the Wang’s product is presented and for avoiding unnecessary repetitions in the algorithm some modified procedures are given. Finally, the application of the algorithm in layout design is discussed.     

RSYN: a system for automated synthesis of reliable multilevelcircuits

Conventional logic synthesis systems are targeted towards reducing the area required by a logic block, as measured by the literal count or gate count; or, improving the performance in terms of gate delays; or, improving the testability of the synthesized circuit, as measured by the irredundancy of the resultant circuit. In this paper, we address the problem of developing reliability driven logic synthesis algorithms for multilevel logic circuits, which are integrated within the MIS synthesis system. Our procedures are based on concurrent error detection techniques that have been proposed in the past for two level circuits, and adapting those techniques to multilevel logic synthesis algorithms. Three schemes for concurrent error detection in a multilevel circuit are proposed in this paper, using which all the single stuck at faults in the circuit can be detected concurrently. The first scheme uses duplication of a given multilevel circuit with the addition of a totally self-checking comparator. The second scheme proposes a procedure to generate the multilevel circuit from a two level representation under some constraint such that, the Berger code of the output vector can be used to detect any single fault inside the circuit, except at the inputs. A constrained technology mapping procedure is also presented in this paper. The third scheme is based on parity codes on the outputs. The outputs are partitioned using a novel partitioning algorithm, and each partition is implemented using a multilevel circuit. Some additional parity coded outputs are generated. In all three schemes, all the necessary checkers are generated automatically and the whole circuit is placed and routed using the Timberwolf layout package. The area overheads for several benchmark examples are reported in this paper. The entire procedure is integrated into a new system called RSYN     

关于产生哈密顿圈的定理及其应用

作者曾提出利用王氏代数产生图的全部哈密顿圈,本文继续研究了这种算法。为了简化计算,给出一个关于王积度数约束的定理,为了避免算法中的不必要的重复,提出一种改进的方法。 最后讨论了本算法在布线设计中的应用等。     

在VLSI自动布局规划产生的overlap移除算法的研究

本文介绍的是自动布局规划算法并有效的消除overlap算法的文章。该算法使用在一个增强的约束图中,在给出的固定位置,空隙以及边界约束下的宏单元消除overlap。在自动布局规划中采用模拟退火算法并采取有效措施消除摆放后的overlap。     

一种动态密度和约束的四边布线程序

本文介绍一种新的四边通道布线器(DDCR),该布线器基于启发式原则提出,并应用动态布线密度和约束图完成线网定序和连线段选择。DDCR是H/V方式布线,该程序由C语言写成,运行于VAX11/780VMS下,可与BBL2布图系统配套使用,通过对许多例子试验,其效果是满意的。     

Automatic test-generation for predicates [software testing]

The authors propose a new technique for the automatic generation of test cases for predicates. Earlier, they proposed an efficient effective test generation strategy for Boolean expressions. They now extend this strategy to predicates. Their new strategy addresses several issues, including: analysis of dependencies between relational expressions in a predicate 𝒫; generation of test constraints for 𝒫 based on the detection of Boolean and relational operator faults in 𝒫; and generation of actual tests according to the generated test constraints for 𝒫. They propose: the use of constraint logic programming (CLP) to automate test-data generation for a predicate; and an incremental approach to apply CLP techniques to solve a constraint system. Since their technique is specification-based, it can facilitate generation of anticipated outputs for actual tests