p-n结的隧道击穿模型研究

建立了抽象化的理论模型对p-n结隧道击穿机理进行定量研究,在理论模型的基础上探讨了电子势垒的形状以及势垒形状随外加电压的变化,并进行定量计算,得出隧穿电压随杂质掺杂浓度的变化规律。所得结论与硅、锗p-n结实验数据相吻合,证明了所建立的理论模型在定量研究p-n结的隧道击穿中的合理性与实用性。该理论模型对研究一般材料或器件的隧道击穿具有重要的借鉴意义。     

与标准CMOS完全兼容的硅基LED器件模拟

采用工业标准0.6μm CMOS工艺设计了以反向击穿硅p-n结为基础的光发射器件.讨论了该器件的光发射机理.利用商业模拟软件对器件的工作特性进行了模拟,包括器件的正向和反向I-V特性、p区掺杂浓度对击穿电压的影响以及门电压对器件发光强度的调制特性的影响等.结果表明该器件是一种很有前途的硅发光器件,在光互连等领域具有广阔的应用前景.     

平面P~+-N结反向电流-电压特性随时间的蠕变

当平面P-N结反向偏置,特别是反向击穿时,常常出现反向优安特性曲线随时间的蠕变,反向电流大大增加.本文给出了各种结构图形和结构参数对这种蠕变影响的实验结果,并分析讨论了其产生机构.     

平行平面穿通结击穿电压的计算及比较

本文研究平行平面穿通结击穿电压的计算.首先根据电离率积分方程得出以归一化外延层厚度为变量的穿通结击穿电压拟合表达式,然后以此为基础,比较了另两种解析方法计算穿通结击穿电压的结果.分析表明：校正临界电场法可给出与电离率积分模式一致的击穿电压,而经典临界电场法将导致较大的误差.     

低压调整二极管击穿特性分析与优化设计

介绍了采用平面结构设计与Si外延工艺制造低压调整二极管的技术。该技术论证了Si平面结型5.1 V低压调整二极管的击穿机理为隧道击穿,同时设计了一种新型Si平面结型低压调整二极管的结构,以及与此结构相匹配的工艺制程,进而实现5.1 V击穿电压特性为硬击穿。此硬击穿优化的关键是对结构设计、氧化工艺的深度研究。     

平面型InGaAs/InP APD边缘提前击穿行为的抑制

平面型雪崩光电二极管(APD)在结弯曲处具有高的电场,导致在结边缘的提前击穿.运用FEMLAB软件对不同工艺流程制备的三种不同结构平面型InP/InGaAs APD的电场分布进行了二维有限元模拟,在表面电荷密度为5×1011cm-2时分析了吸收层厚度、保护环掺杂浓度、保护环和中央结纵向及横向间距等因素对边缘提前击穿特性的抑制程度.比较了这三种结构的InP/InGaAs APD在边缘提前击穿的抑制特性的优劣.通过理论研究对平面InP/InGaAs APD进行了优化.     

InP/InGaAs 隐埋结构雪崩光电二极管

<正> 据日本富士通实验室报导,他们设计并制造了一种具有新型保护环结构的平面 InP/InGaAs 雪崩光电二极管。该二极管和 p-n 结的下面有一个隐埋的 n-InP 层和一个 n-InP 倍增区。在源区的范围内,二极管显示出均匀的倍增特性,最大的倍增因子为30,90％击穿电压下的暗电流为20nA 左右,在1GHz 以下有平坦的频率响应特性。在倍增因子17以下进行了倍增噪     

外延PbS p-n结构

研究了外延PbS p-n结构的电和光电性能。外延层中结的平面垂直于薄层面。指出,有可能利用如光电二极管类似结构制造小响应时间的红外探测器。提出,p-n结和光敏多晶薄膜的暗特性(伏-安特性和电阻随温度的变化)基本一致。证实了,多晶薄膜经敏化便形成p-n结势垒。     

CMOS工艺制作的横向多晶硅p+p-n+结的温度特性及其应用

应用标准CMOS工艺制作了横向多晶硅p p-n 结,对其正向电流-电压的温度特性进行了理论分析和实验研究.实验结果表明:横向多晶硅p p-n 结的理想因子为1.89;在室温附近(T=27 ℃),恒定的正向偏置电流(1 μA)工作条件下,横向多晶硅p p-n 结正向压降的温度变化率约为-1.5 mV/K,与理论计算值相吻合;并且应用横向多晶硅p p-n 结正向压降的温度特性,研制成功非致冷红外微测辐射热计, 其黑体响应率Rbb(1 000 K,10 Hz)=4.3×103V/W.     

离子注入展宽p-n结终端

研究了离子注入展宽p-n结终端工艺,介绍了离子注入剂量或者注入净电荷选择理论.实验证明采用本工艺获得产品的击穿电压高于耗尽层刻蚀工艺所得产品的击穿电压.     

Practical aspects of the depletion etch method in high-voltage devices

In an earlier paper a new junction-termination geometry was described which was able to give near-ideal avalanche breakdown voltage in both plane and planar p-n junctions. The difficulty of the DEM (depletion etch method) was to achieve a precise etch depth which failure to achieve led to reduced effectiveness. In this paper the range of avalanche breakdown voltage is related to the accuracy of the depletion etch in a quanitative and rather general way so thatDelta V, the decrease in breakdown voltage below the ideal is related toDelta Y, the deviation in etch depth from the ideal, for any p-n junction.     

A theory of voltage breakdown of cylindrical P-N junctions, with applications

In certain p-n junctions, such as those made by the alloy method, edges on the junction surface will, by field concentration, lead to lower inverse breakdown voltages than would otherwise be obtained. These edges are approximated by pieces of circular cylinders, and a formula for the voltage breakdown of a circular cylindrical junction obtained. The results agree qualitatively with those found for certain alloy-type diodes.     

The planar junction etch for high voltage and low surface fields in planar devices

A modification of the moat etch type of surface contouring is described which can increase the avalanche breakdown voltage of planar p-n junctions and greatly reduce peak surface electric fields. A properly located moat etch or bevel is used to achieve what is effectively a positive bevel intersection angle between the junction and the surface. Qualitative arguments based on charge balance, exact computer solutions, and experimental results show that higher breakdown voltage and much lower surface fields can be achieved as some, but not all, of the deleterious effects of the junction curvature are eliminated. Optimum design and sensitivity to process variations are also considered.     

Thermal breakdown delay time in silicon p-n junctions

The geometric effects on the applied power dependence of the delay time preceding thermal breakdown in p-n junctions are predicted in terms of a linear heat-flow model and temperature-dependent reverse current. Measurements of the delay time on silicon planar p-n junctions of various areas are compared to the predictions and found to be in reasonable accord.     

Calculation of the diffusion curvature related avalanche breakdown in high-voltage planar p-n junctions

Avalanche multiplication calculations are performed in high-voltage planar p-n junctions to determine breakdown voltage limitations imposed by curvature effects. The issue of choice of ionization coefficient for avalanche multiplication is discussed. From the calculations, a series of design curves and equations are generated which relate the breakdown voltage and peak electric field to those of an ideal junction of the same doping profile, the critical parameters being the substrate doping concentration, the diffusion profile, and the ratio of the radius of curvature to the substrate depletion width for the ideal one-dimensional case. With appropriate distance normalization, these curves and equations can be reduced to a single curve and a single equation. The agreement between theory and experiment is consistently good provided the correct ionization coefficients are used in the theory.     

Junction breakdown instabilities in deep trench isolationstructures

Junction breakdown voltage instability in a p-n junction formed in bulk silicon adjacent to a deep trench filled with polysilicon was investigated. The structure investigated consists of a 5-μm-deep trench filled with heavily p-doped polysilicon. The trench is open at the bottom and is consequently shorted to the p-substrate. The time-dependent behavior of the walkout or the breakdown voltage instability is similar to that reported for planar p-n junctions terminating on surface oxide. Results suggest that trapping of holes in the trench sidewall dielectric is responsible for this phenomenon. The product of trapping center concentration and capture cross section N σ is estimated to be 90 cm^-1     

Monolithic GaP green-emitting LED matrix-addressable arrays

The fabrication and performance of matrix-addressable green-emitting monolithic light-emitting diode (LED) alphanumeric displays are described. Matrix addressability is achieved by p-n junction electrical isolation of n-type stripes of GaP in vapor-phase epitaxial n-epi/p-epi/n-substrate structures by a masked Zn diffusion. Each n-type stripe serves as the common cathode for the LED's in a given column, and with the assistance of a distributed ohmic contact, forms the column address. Light-emitting p-n junctions are formed in the isolated n-type stripes by a second masked Zn diffusion. Rows of LED anodes are electrically connected by thin-film metallization through vias in a glass insulating layer. This truly planar fabrication process potentially offers a marked reduction in the cost of matrix-addressable LED arrays. The transparency of nitrogen-free GaP to light generated at p-n junctions localized in a nitrogen-doped epitaxial layer permits displays of this type to be flip-chip bonded and viewed through the substrate.     

An analysis of the photoinduced current from a finely focused light beam in planar p-n junctions and Schottky-barrier diodes

We present analytic expressions for the photocurrent generated by a highly convergent light beam from a microscope objective lens incident on both planar p-n junctions and Schottky-barrier diodes. The variation of the current as a function of surface recombination velocity, depletion region width, diffusion length, and objective lens numerical aperture are all discussed. We also consider the application of the technique as a method of measuring minority-carrier diffusion lengths, which is independent of variations in surface reflectivity.     

In0.53Ga0.47As/InP floating guard ringavalanche photodiodes fabricated by double diffusion

In_0.53Ga_0.47As/InP separate absorption and multiplication region avalanche photodiodes (SAM-APDs) with doubly diffused floating guard rings have been demonstrated. The planar, front-side illuminated devices are easily fabricated and incorporate strong guarding against edge and surface breakdown. Edge gain is suppressed both by the action of the floating guard rings and by the grading of the p-n junction at the outer edges of the active region that results from the second diffusion. Uniform gains as high as 85 have been measured at multiplied dark currents <100 nA. Multiplied dark currents below 5 nA have been measured at 90% of breakdown, with capacitances below 400 fF for front-side illuminated devices. The low values of dark current and capacitance, as well as the ease of fabrication, make the devices well suited for fiber-optic applications     

A substrate etch geometry for near ideal breakdown voltage in p-n junction devices

A new junction-termination geometry is proposed which can be achieved by a simple etch. This etch effectively lowers peak surface fields in both plane and planar p-n junction devices without increasing peak bulk electric fields. This insures an ideal, or near-ideal, avalanche breakdown voltage. The further advantages of the proposed technique lie in a relative insensitivity to etch depth, a minimal loss in device area, and compatibility with planar technology. Theoretical and experimental results are given to illustrate the substrate-etch technique.