具有30dB增益和1-16GHz带宽的CMOS低噪声中频放大器

This paper presents a high-gain wideband low-noise IF amplifier aimed for the ALMA front end system using 90-nm LP CMOS technology.A topology of three optimized cascading stages is proposed to achieve a flat and wideband gain.Incorporating an input inductor and a gate-inductive gain-peaking inductor,the active shunt feedback technique is employed to extend the matching bandwidth and optimize the noise figure.The circuit achieves a flat gain of 30.5 dB with 3 dB bandwidth of 1-16 GHz and a minimum noise figure of 3.76 dB.Under 1.2 V supply voltage,the proposed IF amplifier consumes 42 mW DC power.The chip die including pads takes up 0.53 mm~2,while the active area is only 0.022 mm~2.     

Equalization and pre-emphasis based LVDS transceiver

This work presents an area-efficient, low-power, high data rate low voltage differential signal (LVDS) transmitter and receiver with signal quality enhancing techniques. The proposed common mode feedback scheme significantly reduces the size of the LVDS transmitter by eliminating the use of area consuming passive resistor and capacitor used for close loop stability compensation. A preemphasis technique has been introduced to enhance the transmitter output’s signal quality without significantly increasing the power draw. On the receiver part, an equalization technique has also been introduced to further enhance signal quality, increases data rate and improved jitter with relatively low power consumption. The LVDS transmitter consumes 5.4 mA of current while driving an external 100 ohm resistor with an output voltage swing of 440 mV. The chip consumes an area of 0.044 mm². This LVDS receiver has an input common mode range from 0.1 to 1.6 V. It consumes 34 mW of power with a maximum data rate of 2 Gbps. It consumes an area of 0.147 mm² a jitter of 11.74 ps rms. A test chip is implemented using 0.18 μm CMOS process.     

Low power high gain CMOS LNA based on inverter cell and self-body bias for UWB receivers

A low-power low-noise amplifier (LNA) utilized a resistive inverter configuration feedback amplifier to achieve the broadband input matching purposes. To achieve low power consumption and high gain, the proposed LNA utilizes a current-reused technique and a splitting-load inductive peaking technique of a resistive-feedback inverter for input matching. Two wideband LNAs are implemented by TSMC 0.18 μm CMOS technology. The first LNA operates at 2–6 GHz. The minimum noise figure is 3.6 dB. The amplifier provides a maximum gain (S₂₁) of 18.5 dB while drawing 10.3 mW from a 1.5-V supply. This chip area is 1.028×0.921 mm². The second LNA operates at 3.1–10.6 GHz. By using self-forward body bias, it can reduce supply voltage as well as save bias current. The minimum noise figure is 4.8 dB. The amplifier provides a maximum gain (S₂₁) of 17.8 dB while drawing 9.67 mW from a 1.2-V supply. This chip area is 1.274×0.771 mm².     

用于SDH STM-64光接收机的GaAs HBT限幅放大器

采用2μm GaAs HBT工艺实现了10Gb/s的限幅放大器.整个系统包括一级输入缓冲、三级放大、一级用于驱动50Ω传输线的输出缓冲和失调电压补偿回路四个部分.采用双电源供电,正电源为3.3V,负电源为-2V,功耗为500mW.在输出电压幅度保持恒定(单端峰峰值300mV)的条件下,输入动态范围约为38dB.芯片面积为1.15×0.7mm².     

Very Low-Voltage Switched-Current Circuits in Standard Digital CMOS Process

The inherent simplicity of switched-current circuits makes them suitable for low-voltage and very low voltage operation. This paper presents the design of 1.2-V switched-current circuits in a standard digital CMOS process. The core elements are the proposed fully differential SI memory cell and high resolution current quantizer. A delay line and a second-order delta-sigma modulator are implemented and measured. The delay line occupies an active chip area of 0.2 mm² and dissipates a power of 0.2 mW, and the modulator occupies an active chip area of 0.47 mm² and dissipates a power of 0.78 mW. The measured total harmonic distortion of the delay line is less than –48 dB with a 60% input modulation index and the measured dynamic range of the modulator is 10 bits.     

65nm工艺下20Gb/s无电感限幅放大器设计与分析

本文设计了一款能工作在20Gb/s速率下的无电感限幅放大器。限幅放大器包括三各部分：带直流失调消除的输入匹配级,增益级和输出驱动级。本设计采用交叉负反馈技术,使得放大器在获得高带宽的同时拥有较为平坦的频率响应。直流失调消除环路中增加了误差放大器来保证直流失调消除效果。放大器在65纳米工艺下成功流片,芯片面积为0.45 × 0.25平方毫米（不包括PAD）,测试结果显示放大器的差分增益为37dB,带宽为16.5GHz,在高达26.5GHz的频率内Sdd11和Sdd22分别小于-16dB和-9dB。除了驱动级,整个放大器在1.2V的电源电压下消耗50mA的电流。     

8 Gbits/s inductorless transimpedance amplifier in 90 nm CMOS technology

This work presents the design and the measured performance of a 8 Gb/s transimpedance amplifier (TIA) fabricated in a 90 nm CMOS technology. The introduced TIA uses an inverter input stage followed by two common-source stages with a 1.5 kΩ feedback resistor. The TIA is followed by a single-ended to differential converter stage, a differential amplifier and a 50 Ω differential output driver to provide an interface to the measurement setup. The optical receiver shows a measured optical sensitivity of ?18.3 dBm for a bit error rate = 10^?9. A gain control circuitry is integrated with the TIA to increase its input photo-current dynamic range (DR) to 32 dB. The TIA has an input photo-current range from 12 to 500 μA without overloading. The stability is guaranteed over the whole DR. The optical receiver achieves a transimpedance gain of 72 dBΩ and 6 GHz bandwidth with 0.3 pF total input capacitance for the photodiode and input PAD. The TIA occupies 0.0036 mm² whereas the complete optical receiver occupies a chip area of 0.46 mm². The power consumption of the TIA is only 12 mW from a 1.2 V single supply voltage. The complete chip dissipates 60 mW where a 1.6 V supply is used for the output stages.     

A Hybrid Audio ΔΣ Modulator with dB‐Linear Gain Control Function

A hybrid ΔΣ modulator for audio applications is presented in this paper. The pulse generator for digital‐to‐analog converter alleviates the requirement of the external clock jitter and calibrates the coefficient variation due to a process shift and temperature changes. The input resistor network in the first integrator offers a gain control function in a dB‐linear fashion. Also, careful chopper stabilization implementation using return‐to‐zero scheme in the first continuous‐time integrator minimizes both the influence of flicker noise and inflow noise due to chopping. The chip is implemented in a 0.13 μm CMOS technology (I/O devices) and occupies an active area of 0.37 mm². The ΔΣ modulator achieves a dynamic range (A‐weighted) of 97.8 dB and a peak signal‐to‐noise‐plus‐distortion ratio of 90.0 dB over an audio bandwidth of 20 kHz with a 4.4 mW power consumption from 3.3 V. Also, the gain of the modulator is controlled from –9.5 dB to 8.5 dB, and the performance of the modulator is maintained up to 5 ns_RMS external clock jitter.     

A Very Low Voltage Bipolar Op-Amp for Sensor Applications

A new bipolar four-quadrant operational amplifier operating at a power supply voltage of 0.8 V and with a supply current of 800 A is here presented and illustrated. It features low input offset, low bias current, low noise, low crossover distortion and a rail-to-rail output swing. Control circuits ensuring minimum and maximum current limits for the output transistors have been incorporated. The biasing circuitry follows a PTAT scheme. A simple compensation topology allows the reduction of the area. The chip, whose area is about 2 mm², has been fabricated in HF2CMOS 2 /6 GHz technology. Finally, Spice simulations and experimental results, which confirm the expected overall performances of the low voltage op-amp, are reported.     

Enhanced active feedback technique with dynamic compensation for low-dropout voltage regulator

This paper presents a novel frequency compensation technique for a low-dropout (LDO) voltage regulator. Enhanced active feedback frequency compensation is employed to improve the frequency response. The proposed LDO is capable of providing high stability for current loads up to 150 mA with or without loading capacitors. The proposed LDO voltage regulator provides a loop bandwidth of 7.8 MHz under light loads and 6.5 MHz under heavy loads. The maximum undershoot and overshoot are 59 and 90 mV, respectively, for changes in load current within a 200-ns edge time, while the compensation capacitors only require a total value of 7 pF. This enables easy integration of the compensation capacitors within the LDO chip. The proposed LDO regulator was designed using TSMC 0.35-μm CMOS technology. With an active area of 0.14 mm² (including feedback resistors), the quiescent current is only 40 μA. The input voltage ranges from 1.73 to 5 V for a loading current of 150 mA and an output voltage of 1.5 V. The main advantage of this approach is the stability of the LDO circuit when external load capacitors are connected, or even without load capacitors.     

一种5~6 GHz宽带全集成CMOS低噪声放大器

采用55 nm标准CMOS工艺,设计并流片实现了一种应用于Wi-Fi 6(5 GHz)频段的宽带全集成CMOS低噪声放大器(LNA)芯片,包括源极退化共源共栅放大器、负载Balun及增益切换单元。在该设计中,所有电感均为片上实现;采用Balun负载,实现信号的单端转差分输出;具备高低增益模式,以满足输入信号动态范围要求。测试结果表明,在高增益模式下该放大器的最大电压增益为20.2 dB,最小噪声系数为2.2 dB;在低增益模式下该放大器的最大电压增益为15 dB,最大输入1 dB压缩点为-3.2 dBm。芯片核心面积为0.28 mm²,静态功耗为10.2 mW。     

A 3.1 to 5 GHz CMOS Transceiver for DS‐UWB Systems

This paper presents a direct‐conversion CMOS transceiver for fully digital DS‐UWB systems. The transceiver includes all of the radio building blocks, such as a T/R switch, a low noise amplifier, an I/Q demodulator, a low pass filter, a variable gain amplifier as a receiver, the same receiver blocks as a transmitter including a phase‐locked loop (PLL), and a voltage controlled oscillator (VCO). A single‐ended‐to‐differential converter is implemented in the down‐conversion mixer and a differential‐to‐single‐ended converter is implemented in the driver amplifier stage. The chip is fabricated on a 9.0 mm² die using standard 0.18 µm CMOS technology and a 64‐pin MicroLead Frame package. Experimental results show the total current consumption is 143 mA including the PLL and VCO. The chip has a 3.5 dB receiver gain flatness at the 660 MHz bandwidth. These results indicate that the architecture and circuits are adaptable to the implementation of a wideband, low‐power, and high‐speed wireless personal area network.     

Low-power 10 Gb/s inductorless inverter based common-drain active feedback transimpedance amplifier in 40 nm CMOS

This study presents an inductorless 10 Gb/s transimpedance amplifier (TIA) implemented in a 40 nm CMOS technology. The TIA uses an inverter with active common-drain feedback (ICDF-TIA). The TIA is followed by a two-stage differential amplifier and a 50 Ω differential output driver to provide an interface to the measurement setup. The optical receiver shows measured optical sensitivities of ?17.7 and ?16.2 dBm at BER = 10^?12 for data rates of 8 and 10 Gb/s, respectively. The TIA has a simulated transimpedance gain of 47 dBΩ, 8 GHz bandwidth with 0.45 pF total input capacitance for the photodiode, ESD protection and input PAD. The TIA occupies 0.0002 mm² whereas the complete optical receiver occupies a chip area of 0.16 mm². The power consumption of the TIA is only 2.03 mW and the complete chip dissipates 17 mW for a 1.1 V single supply voltage. The complete optical receiver has a measured transimpedance gain of 57.5 dBΩ.     

BDI 型甚长波IRFPA 读出电路研究与设计

针对甚长波红外（VLWIR）探测器动态结阻抗过低、暗电流较大,且工作在高背景环境下等特点,设计了一种具有记忆功能背景抑制的3232甚长波红外焦平面（IRFPA）读出电路。该电路采用基于高增益负反馈运放的缓冲直接注入级（BDI）结构作为输入级,大幅降低了输入阻抗,提高了注入效率,并使探测器处于稳定偏压状态。同时,该电路采用具有记忆功能的背景抑制电路,有效提高了积分时间和红外焦平面的信噪比（SNR）,改善了动态范围和对比度。基于HHNECCZ6H0.35m1P4M标准CMOS工艺,完成了电路的流片制造。实测结果表明:50K低温下电路功能正常,输出范围大于2V,读出速率达到2.5MHz,RMS噪声小于0.3mV,线性度优于99%,功耗小于100mW。     

应用于60GHz的CMOS频率生成器

本文提出一种用于60GHz的频率生成器,其由电流模二分频器和倍频器组成. 得益于电流模结构和差分对的非线性,该频率生成器具有很宽的工作频率范围以补偿工艺,电压和温度的偏差。频率生成器用90nm 工艺投片验证。芯片的面积为0.64X0.65mm^2,。测试结果表明在输入0dBm功率的时候,该频率生成器可以工作在15GHz-25GHz。整个芯片工作电压是1.2V,消耗12.1mW功耗。     

A 65 mW, 0.4–2.3 GHz Bandpass Filter for Satellite Receivers

A monolithic tunable bandpass filter for satellite receiver front-ends is presented. The center frequency of the bandpass filter can be tuned from 0.4 GHz to 2.3 GHz. The filter is constructed using four transconductor-C poly-phase filter sections and has a 50 dB variable gain range. At 20 dB attenuation and at 30 dB gain the measured 1 dB compression point is –21 dBm and –56 dBm, respectively. Measured input IP3 is –12 dBm. The noise figure is 15 dB at maximum gain. An on-chip I/Q oscillator tracks the center frequency and enables automatic tuning. The bandpass filter dissipates 65 mW with 5 Volt supply voltage and occupies 0.16 mm² chip area. The filter is realized in a standard 11 GHz f _t bipolar technology.     

新型电流镜积分红外量子阱探测器读出电路的设计分析

设计了一种偏压可调电流镜积分(Current Mirroring Integration,CMI)红外量子阱探测器焦平面CMOS读出电路。该电路适应根据偏压调节响应波段的量子阱探测器,其中探测器偏压从0.61 V到1.55V范围内可调。由于CMI的电流反馈结构,使得输入阻抗接近0,注入效率达0.99;且积分电容可放在单元电路外,从而可以在一定的单元面积下,增大积分电容,提高了电荷处理能力和动态范围;为提高读出电路的性能,电路加入撇除(Skimming)方式的暗电流抑制电路。采用特许半导体(Chartered)0.35 m标准CMOS工艺对所设计的电路(16×1阵列)进行流片,测试结果表明:在电源电压为3.3V,积分电容为1.25pF时,电荷处理能力达到1.3×107个电子;输出摆幅达到1.76V;功耗为25mW;动态范围为75dB;测试结果显示CMI可应用于高性能FPA。     

一种全集成8位2.16 GS/s SAR ADC

设计了一种8位2.16 GS/s四通道、时间交织逐次逼近型模数转换器(TI-SAR ADC)。单通道SAR ADC采用数据环、异步时钟环的双环结构实现高速工作。采用带复位开关的动态比较器缩短量化时间,提高比较精度。结合反向单调切换时序,逐步增大共模电压,提升量化速度。基于55 nm CMOS工艺设计,后仿真结果表明,在1.2 V电源电压下,该TI-SAR ADC消耗 42.6 mA 电流,在奈奎斯特输入频率下,FOM值为212 fJ/(conv.step),信噪失真比(SNDR)为42.7 dB,无杂散动态范围(SFDR)为53 dB。芯片整体版图面积为3.4 mm²。     

一种低功耗的高速光接收器跨阻前置电路设计

为了降低芯片面积和功耗,提出了一种10 Gb/s光接收器跨阻前置放大电路。该电路采用了两个带有可调共源共栅（RGC）输入的交叉有源反馈结构,其中的跨阻放大器未使用电感,从而减少了芯片的总体尺寸。该跨阻前置电路采用0.13μm CMOS工艺设计而成,数据速率高达10 Gb/s。测试结果表明,相比其他类似电路,提出的电路芯片面积和功耗更小,芯片面积仅为0.072mm2,当电源电压为1.3 V时,功率损耗为9.1 mW,实测平均等效输入噪声电流谱密度为20pA/（0.1-10）Hz,且-3dB带宽为6.9 GHz。     

A power-constrained design strategy for CMOS tuned low noise amplifiers

This paper presents a design methodology for tuned low noise amplifiers (LNAs), based on the minimization of the noise figure for a given power consumption. Our proposed design strategy is demonstrated through the design of a 2.4 GHz LNA. Simulation results show that the amplifier draws 5 mA from a 3.3 V supply voltage and features a 1.7 dB noise figure, while keeping the input/output impedance matched to 50 Ω. The circuit achieves a gain of 11dB and a 1dB compression point of about −5 dB m. Custom ESD structures that do not degrade excessively the LNA performance are used for protection. The chip area (excluding the bonding pads) is approximately 0.3 × 0.3 mm².