Etching characteristics of SiO2 in CHF3 gas plasma

The etching characteristics of SiO₂} have been investigated in the CHF₃} gas plasma using the planar type reactor with the 400 kHz rf power. The etch rate of SiO₂}, the SiO₂} /Si and SiO₂}/resist etch rate ratios, and the deterioration of photoresist films are studied with a variety of etching parameters. The etching characteristics depend strongly on the coupling mode. With the cathode coupling mode, the values of 300å/min and of larger than 100 are obtained for the etch rate of SiO₂} and the SiO₂}/Si etch rate ratio, respectively. Only 8 is given for the SiO₂} /Si etch rate ratio with the anode one. The deterioration of photoresist films less occurs with the cathode coupling mode than with the anode one. The dependences of the etching characteristics on the rf current, gas pressure, gas flow rate, and the electrode separations are also studied some in detail with the cathode coupling mode. Possible explanations for some of the experimental results are discussed.     

Properties of low-temperature (80-300° C) pyrolytic SiO2 on Si and InP

We report on a new low-temperature pyrolytic deposition technology for silicon dioxide. We present data characterizing the electrical and optical properties of this dielectric deposited on Si and InP substrates. The effects of thermal processing are also reported. Deposition of high-quality SiO₂ is achieved by reacting SiH₄ and O₂ at pressures of 2–12 Torr. Reactions occur by pyrolysis only, promoting stoichiometric SiO₂ deposition and good interfacial properties. No plasma- or photo-enhancement is required. Deposition is achieved at temperatures as low as 80° C, the lowest temperature ever reported for pyrolytic SiO₂ deposition. Rates as high as 65 Å/min at 100° C and 100-150 Å/min at 150-300° C are attained. The leakage current densities measured for both Si and InP MIS capacitors (e.g. 10^-9 Å/cm² for 150° C SiO₂) are two to six orders of magnitude lower than values reported for plasma- and photo-enhanced SiO₂ deposited at equivalent temperatures. The high-temperature integrity of this dielectric also makes it a promising annealing cap for group III-V compound semiconductors. Our annealing studies show that SiO₂-capped indium phosphide surfaces remain specular up to 850° C.     

Use of photocurrent-voltage characteristics of MOS structures to determine insulator bulk trapped charge densities and centroids

A new technique is described for determining the density and centroid of trapped space charge in the oxide layer of metal-oxide-semiconductor (MOS) structures. Photo-current-voltage (photo I-V) characteristics for both the metal-oxide and Si-oxide interfaces are used to determine the internal fields due to bulk trapped charge, and hence its density and centroid. Experimental examples for locating both positive and negative charge are presented. For negative charge, an Al-Si0₂-W-SiO₂-Si structure (MOWOS) with a layer of approximately 10¹⁴ W atoms/cm² deposited 80 Å from the Si-SiO₂ interface and charged by electronic internal photoemission is investigated. For positive charge, the location of trapped holes generated by 16.85 eV photons or x-rays in the SiO₂ layer of an MOS structure under a voltage bias is discussed. The photo I-V technique is compared to others in terms of its direct, rapid, minimally perturbing, low current, and low field characteristics.     

Characterization of TiN/TiSi2 bilayer for application to ULSI

The properties of TiN/TiSi₂ bilayer formed by rapid thermal annealing (RTA) in an NH₃ ambient after the titanium film is deposited on the silicon substrate is investigated. It is found that the formation of TiN/TiSi₂ bilayer depends on the RTA temperature and a competitive reaction for the TiN/TiSi₂ bilayer occurs at 600°C. Both the TiN and TiSi₂ layers represent titanium-rich films at 600°C anneal. The TiN layer has a stable structure at 700°C anneal while the TiSi₂ layer has C₄₉ and C₅₄ phase. Both the TiN and TiSi₂ layers have stable structures and stoichiometries at 800°C anneal. When the TiN/TiSi₂ bilayer is formed, the redistribution of boron atoms within the TiSi₂ layer gets active as the anneal temperature is increased. According to secondary ion mass spectroscopy analysis, boron atoms pile up within the TiN layer and at the TiSi₂−Si interface. The electrical properties for n⁺ and p⁺ contacts are investigated. The n⁺ contact resistance increases slightly with increasing annealing temperature but the p⁺ contact resistance decreases. The leakage current indicates degradation of the contact at high annealing temperature for both n⁺ and p⁺ junctions.     

Arsenic silicide formation by oxidation of arsenic implanted silicon

Wet oxidations of (100) silicon implanted with an arsenic dose of 2 × 10¹⁶ cm⁻² and an energy of 30 keV were carried out in the temperature range between 600 and 900° C. The oxidation rate is increased on the arsenic implanted samples up to a factor of 2000 as compared to undoped samples. During these oxidations the arsenic suicide phase AsSi is precipitated at the oxide/silicon interface. After short oxidation times at 600° C, a continuous AsSi layer is found. It is dissolved during extended oxidation times and finally almost all As is incorporated in the oxide. After 900° C oxidations, substantial AsSi crystallites remain at the Si/SiO₂ interface. They are still observed up to the larg-est oxide thickness grown (2.3 μm). The AsSi phase and the distribution of the im-planted arsenic were analyzed by TEM, SIMS and XRF measurements.     

Growth and characterization of superconducting V3Si on Si and Al2O3 by molecular beam epitaxial techniques

A study of the growth parameters governing the nucleation of metastable superconducting A15 V₃Si on Si and A1₂O₃ is presented. Nominally, 500Å films of V_1-xSi_x were produced through codeposition of V and Si onto heated (111) Si and (1102) A1₂O₃ substrates. Samples were prepared in a custom-built ultrahigh vacuum (UHV) chamber containing dual e-beam evaporation sources and a high temperature substrate heater. V and Si fluxes were adjusted to result in the desired average film composition. V_0.75Si_0.25 films prepared at temperatures in excess of 550° C on Si show significant reaction with the substrate and are nonsuperconducting while similar films grown on A1₂O₃ exhibit superconducting transition temperatures(@#@ T_c @#@) approaching bulk values for V₃Si (16.6-17.1 K). Codeposition at temperatures between 350 and 550° C results in superconducting films on Si substrates while growth at lower temperatures results in nonsuperconducting films. Lowering the growth temperature to 400° C has been shown throughex situ transmission electron microscopy (TEM) and Auger compositional profiling to minimize the reaction with the Si substrate while still activating the surface migration processes needed to nucleate A15 V₃Si. Variation of film composition aboutx = 0.25 is shown to result in nonsuperconducting films for highx and superconducting films with T_c approaching the bulk V value (5.4 K) for lowx. Finally, lowering the V_0.75Si_0.25 deposition rate is shown to raise T_c.     

Effects of HCl and Cl2 additions on silicon oxidation kinetics

The growth kinetics of SiO₂ films (100-18000Å) on [100], 2Ωcm silicon have been investigated between 900-1100?C with additions of 0-9 vol.% HC1 or 0-2 vol.% Cl₂ to the dry oxygen ambient. The thickness-time data could best be fitted numerically to a mixed linear-parabolic equation that included a correction for fast initial growth. Equivalent amounts of chlorine (e.g., 2 vol.% HC1 or 1 vol.% Cl₂) produced completely different effects on the rate of SiO₂ growth. The quantitative effects of halogen additions were studied in greatest detail at 900?C. At that temperature, the parabolic rate constant increased linearly with the HC1 concentration. At the same time, the linear rate constant remained constant. Both rate constants did change when Cl₂ was used as an additive. The effect of HC1 additions on the parabolic rate constant reaches a maximum around 1000?C. Possible mechanisms for the halogen effects are discussed,← and it is seen that the gas phase reaction 4 HC1 + 0₂ → 2 H₂O + 2 Cl₂ is not reflected in the growth kinetics.     

Rapid thermal chemical vapor deposition of germanium on silicon and silicon dioxide and new applications of ge in ULSI technologies

In this study, low pressure chemical vapor deposition of pure germanium on silicon and silicon dioxide has been considered for new applications in future ultra large scale integration (ULSI) technologies. Germanium depositions were performed in a lamp heated cold-wall rapid thermal processor using thermal decomposition of GeH₄. It is shown that Ge deposition on Si can be characterized by two different regions: a) at temperatures below approximately 450° C, the deposition is controlled by the rate of surface reactions resulting in an activation energy of 41.7 kcal/mole. b) Above this temperature, mass transport effects become dominant. The deposition rate at the transition temperature is approximately 800 Å/min. It is shown that Ge deposition on SiO₂ does not occur, even at temperatures as high as 600° C, resulting in a highly selective deposition process. Selectivity, combined with low deposition temperature makes the process very attractive for a number of applications. In this work, it is shown for the first time that selective Ge deposition can be used to eliminate silicon consumption below the gate level during the silicidation of the shallow source and drain junctions of deep submicron MOSFETs. In addition, a new in situ technique has been developed which allows polycrystalline germanium (poly-Ge) deposition on SiO₂. In this work poly-Ge has been considered as a low temperature alternative to polycrystalline silicon (poly-Si) in the formation of gate electrodes in single-wafer manufacturing where low-thermal budget processes are most desirable.     

Phase equilibria of the Si-Ge-Ti system relevant to the reactions between SiGe alloys and Ti

The semiconductor-rich region of the Si-Ge-Ti ternary isotherm at 900°C was determined by metallography, x-ray diffraction, and electron microprobe analysis. The sample alloys were prepared by arc-melting. These alloys were brought to equilibrium by annealing at 900°C for 400 h. It was confirmed that at 900°C, TiSi₂ and TiGe₂ form a continuous solid solution Ti(Si_1−yGe_y)₂ with the C54 crystal structure. It was also shown that, other than Ti(Si_1−yGe_y)₂ and Si_1−xGe_x, there is not any binary or ternary phase within the Si-Ge-TiGe₂-TiSi₂ trapezoid region. Between the Ti(Si_1−yGe_y)₂ and Si_1−xGe_x single-phase fields is the Ti(Si_1−yGe_y)₂-Si_1−xGe_x two-phase region. The tie-lines for this two-phase region were determined. The tie-lines tilt slightly toward the TiSi₂ and Ge corners. In other words, at equilibrium, the silicon to germanium atomic ratio is larger in Ti(Si_1−yGe_y)₂ than in Si_1−xGe_x (x>y). This tendency for tie-lines to tilt toward the TiSi₂ and Ge corners had been proposed in the literature as the reason for the interesting microstructure evolution during the reactions between SiGe alloys and Ti. In addition, the possible diffusion paths for the reactions between SiGe alloys and Ti were discussed based on the obtained isotherm. Recognizing Si and Ge have higher mobilities in Ti(Si_1−yGe_y)₂, it is predicted that for SiGe the extent of concentration change is large but occurs over a shorter distance, and for TiSi₂ the extent of concentration change is small but occurs over a longer distance.     

Growth and characterization of Si doped vapor phase epitaxial GaAs for mesfet

This paper describes the Si-doping of GaAs that was grown using the AsCl₃:H₂:GaAs, Ga Chemical vapor deposition process. The doping sources were AsCl₃:SiCl₄ liquid solutions which proved to be highly reproducible for Si doping within the range, 1×1O¹⁶ to 2×10¹⁹ cm^?3. Incorporation of Si into the GaAs apparently occurs under near equilibrium conditions. This point is considered in detail and the consequences experimentally utilized to grow n, n+ bilayers using a single AsCl₃:SiCl₄ doping solution. Si impurity profiles based upon differential capacitance and SIMS data are presented. These can be very abrupt for n, n⁺ structures with order of magnitude changes occurring within 500 Å. For the 1×10₁₆ to 8×l0¹⁸ cm^?3 doped samples the mobilities at 78 and 298°K are comparable to the higher values reported for GaAs thin films grown by CVD. Power FET devices made from this material have demonstrated an output density of 0.86 watts/mm at 10 GHz.     

A comparison of MOS gate structures formed by depositing polycrystalline silicon on thin oxides using conventional low pressure chemical vapor deposition and rapid thermal chemical vapor deposition

MOS structures with 80Å-200Å thick gate oxides were fabricated using polycrystalline silicon gate electrodes deposited by rapid thermal chemical vapor deposition (RTCVD) and by conventional chemical vapor deposition (LPCVD). Polycrystalline silicon doping was achieved by BF₂ or As implantation followed by rapid thermal annealing (RTA). The Q-C method was employed to study the electrical properties of the capacitors through high and low frequencyC- V profiles. The electrical properties of the MOS structures show that the devices fabricated using RTCVD polycrystalline Si are comparable in quality to those with LPCVD polycrystalline silicon gate electrodes. However, the results also indicate that boron diffusion through the thin oxide is a problem regardless of the deposition technique used for polycrystalline silicon. Boron penetration is accompanied by a shift in threshold voltage, inversion layer capacitance and a high density of midgap interface traps. Dopant diffusion in polycrystalline silicon and through the thin gate oxides was also studied by secondary ion mass spectroscopy (SIMS). The findings of the SIMS analysis correlate well with the electrical measurements. The results indicate that significant boron diffusion can occur through an 80A oxide if an RTA temperature higher than 1000° C is used. On the other hand, both SIMS and electrical measurements suggest that As penetration into the substrate is negligible even at temperatures as high as 1100° C.     

Evidence for transient composition variations at GaAs/Ga1−xAlxAs heterostructure interfaces prepared by metal-organic chemical vapour deposition

The composition profiles of GaAs/Ga_1?xAl_xAs heterostructures prepared in two different Metal-Organic Chemical Vapour Deposition (MOCVD) reactors have been studied. Transmission electron microscopy (TEM). and Auger and secondary ion mass spectrometry (SIMS) sputter profiling results are in good agreement and interface widths below 20 å have been achieved. Significant new results on transient phenomena have been obtained. showing that large and sometimes very sharp excursions in composition can be associated with valve switching actions. Direct evidence is presented that gas pressure or flow transients can occur during valve operations. and it is suggested that such instabilities are the cause of the effects observed.     

Low-temperature processing of shallow junctions using epitaxial and polycrystalline CoSi2

Cobalt disilicide is grown epitaxially on (100) Si from a 15 nm Co/2 nm Ti bilayer by rapid thermal annealing (RTA) at 900°C. Polycrystalline CoSi₂ is grown on (100) Si using a 15 nm Co layer and the same annealing condition. Silicide/p⁺-Si/n-Si diodes are made using the silicide as dopant source:¹¹B⁺ ions are implanted at 3.5–7.5 kV and activated by RTA at 600–900°C. Shallow junctions with total junction depth (silicide plus p⁺ region) measured by high-resolution secondaryion mass spectroscopy of 100 nm are fabricated. Areal leakage current densities of 13 nA/cm² and 2 nA/cm² at a reverse bias of -5V are obtained for the epitaxial silicide and polycrystalline silicide junctions, respectively, after 700°C post-implant annealing.     

Room temperature oxidation of lead-indium alloy films

The kinetics of growth of thin (14 to 40Å) oxide layers on lead-indium alloys was investigated ellipsometrically, using: 3000Å thick films at 23°C; and oxygen exposures at 760 torr for times ranging from five minutes to five days. Assuming that the oxide layer is comprised of a two-phase mixture of PbO and In₂O₃ having a negligible extinction coefficient made it possible to estimate the oxide composition from the ellipsometrically-obtained oxide refractive index. Under these oxidizing conditions, the volume fraction of PbO in the oxide mixture decreases from a value of unity for pure lead to zero for alloys containing more than 30 at. percent In, in agreement with the Auger Electron Spectroscopy results of Chou and coworkers. The oxidation rate equals a exp (X₁/X), where α and X₁ will be seen to vary complexly with alloy composition. A theoretical explanation of these results is also presented.     

Ohmic contacts to InP-based materials induced by means of rapid thermal low pressure (metallorganic) chemical vapor deposition technique

A rapid-thermal-low-pressure-metallorganic-chemical-vapor-deposition (RT-LPMOCVD) technique was executed in order to deposit non-semiconductor thin layer materials, necessary for producing metal contact to InP-based microelectronic devices. Silicon dioxide (SiO₂) films were deposited onto InP substrates in rapid thermal cycles, using O₂ and 2% diluted SiH₄ in Ar, with very fast growth kinetics and low activation energy. The SiO₂ film exhibited excellent properties, such as refractivity index, density, internal stress, and wetp-etch rates. The SiO₂ films were dry etched in a given pattern to allow for the formation of a small metal contact to the InP-based material, onto which the SiO₂ layer was deposited. Subsequently, titanium-nitride (TiN _x ) thin films were deposited onto the InP substrate through rapid thermal deposition cycles, using a tetrakis (dimethylamido) titanium (DMATi) metallorganic liquid source as the precursor for the process, with fast kinetics. The deposited TiN _x films had a stoichiometric structure and contained nitrogen and titanium in a ratio close to unity, but incorporated a large amount of carbon and oxygen. The film properties, such as resistivity (40–80 μΩ·mm) and stress (compressive; ?0.5 to ?2.0×10⁹ dyne·cm^?2), were studied in addition to an intensive investigation of its microstructure and morphology, and their performance as an ohmic contacts while deposited ontop?In_0.53Ga_0.47As material (Zn doped 1.2×10¹⁸ cm^?3).     

The preparation of Gal-x Inx As by organometallic pyrolysis for homojunction LED’S

Ga_1-x}In_x}As epitaxial layers have been deposited on GaAs substrates using the technique of organometallic pyrolysis (metalorganic chemical vapour deposition). The deposition was performed in a laminar flow, resistively heated, reactor. Both n and p-type (10¹⁷}-10¹⁸} carriers/cm³}) epitaxial layers, several microns thick,were prepared, with values of x in the range 0 ≤x ≤0.3. Epitaxial layer characterisation was carried out using conventional electrical, optical and x-ray techniques. Restricted emitting area (50–75 μm diameter) zinc-diffused LED’s were prepared in ungraded epitaxial layers with emission spectral peaks in the range 0.9 —1.15 ym. External quantum efficiencies of these devices decreased rapidly with increasing x, from∼0.4% for GaAs LED’s to∼0.02% for Gao._0.75}In_0.25}As LED’s.     

Elimination of dislocations in heteroepitaxial MBE and RTCVD Ge x Si1-x grown on patterned Si substrates

We have grown Ge _x Si_1-x (0 <x < 0.20,1000–3000Å thick) on small growth areas etched in the Si substrate. Layers were grown using both molecular beam epitaxy (MBE) at 550° C and rapid thermal chemical vapor deposition (RTCVD) at 900° C. Electron beam induced current images (EBIC) (as well as defect etches and transmission electron microscopy) show that 2800Å-thick, MBE Ge_0.19Si_0.81 on 70-μm-wide mesas have zerothreading and nearly zero misfit dislocations. The Ge_0.19Si{0.81} grown on unpatterned, large areas is heavily dislocated. It is also evident from the images that heterogeneous nucleation of misfit dislocations is dominant in this composition range. 1000Å-thick, RTCVD Ge_0.14Si_0.86 films deposited on 70 μm-wide mesas are also nearly dislocation-free as shown by EBIC, whereas unpatterned areas are more heavily dislocated. Thus, despite the high growth temperatures, only heterogeneous nucleation of misfit dislocations occurs and patterning is still effective. Photoluminescence spectra from arrays of GeSi on Si mesas show that even when the interface dislocation density on the mesas is high, growth on small areas results in a lower dislocation density than growth on large areas.     

Photoluminescence of InxGa1-xAs-GaAs strained-layer superlattices

Photoluminescence of In_xGa_1-xAs-GaAs strained-layer superlattices (SLS's) grown by molecular beam epitaxy (MBE) is investigated. Highly strained SLS's composed of layers differing in their bulk lattice constants by as much as 2.7% are examined over the temperature range 20K-300K. Photoluminescence (PL) spectra for several In_0.28Ga_0.72AsGaAs SLS's are presented, providing data relating effective band gap and PL intensity to temperature and layer thickness. These data suggest a critical (maximum) alloy layer thickness for optical quality material in the range of 80å-100å for crystals with x = 0.28 and an In_xGa_1-xAs/GaAs layer thickness ratio of L_z/L_B = 1.3. Results of PL experiments on In_0.38Ga_{0 62}As-GaAs SLS's are also presented, and the effects of lattice misfit at the SLS/substrate interface upon the optical quality of these SLS's is examined.     

Process integration of Pr-based high-k gate dielectrics

We present the process integration of the Pr-based high-k oxides Pr₂O₃, PrTi_xO_y and Pr_xSi_yO_z for CMOS devices. MOS structures were grown in form of p⁺ poly-Si/Pr-based dielectric/Si(100) by MBE. RIE with CF₄/O₂ plasma was used to selectively remove the poly-Si layer. It was found that the Pr-based oxides layers can be dissolved with high selectivity in diluted H₂SO₄ solutions. Details of the etch kinetics of Pr-based oxides and poly-Si were studied. Electrical characteristics of MOS stacks with integrated Pr_xSi_yO_z are presented.     

Silicide formation in co-deposited TiSix layers: The effect of deposition temperature and Mo

The silicide reaction in co-deposited TiSi_x layers on single crystal and pre-amorphized Si has been studied in detail. Both the co-deposition ratio and the co-deposition temperature were found to have a strong effect on the formation of the C54-TiSi₂ phase in these films. An unusual dependence of the sheet resistance on the co-deposition ratio was observed for films deposited at room temperature and those deposited at 400°C: the C54-TiSi₂ phase forms more easily for layers deposited at 400°C in the co-deposition ranges x∼0 and x>1.5, while it forms more easily for layers deposited at room temperature in the co-deposition ratio range of x∼0.2–1.5. These dependencies are explained by the formation of crystalline silicide phase(s) with composition close to the co-deposition ratio. With a Si rich ratio, the C49-TiSi₂ phase forms at 400°C with very small grain size, which facilitates the C54-TiSi₂ phase formation. The initial reaction of Ti-rich layer deposited at 400°C involves the formation of metal rich silicide, which impedes the formation of the C54-TiSi₂ phase. An ultra-thin MoSi_2.0 layer (<0.5 nm) was found to promote the formation of the C54-TiSi₂ phase in layers co-deposited at room temperature, but it showed little effect on layers co-deposited on pre-amorphized substrates at elevated temperature.