低阻p型衬底上高阻厚层n型外延

介绍了高阻厚层反型外延片的一种实用生产技术，即在PE-2061S外延设备上，采取特殊的工艺控制在电阻率小于0.02Ω·cm的p型低阻衬底上实现了高阻厚层n型外延生长，外延层电阻率大于40Ω·cm，厚度大于100μm. 研究表明：该外延材料完全可以满足IGBT器件制作的需要.     

低阻P型衬底上高阻厚层n型外延

介绍了高阻厚层反型外延片的一种实用生产技术,即在PE-2061S外延设备上,采取特殊的工艺控制在电阻率小于0.02Ω·cm的p型低阻衬底上实现了高阻厚层n型外延生长,外延层电阻率大于40Ω·cm,厚度大于100μm.研究表明:该外延材料完全可以满足IGBT器件制作的需要.     

低阻P型衬底上高阻厚层n型外延

介绍了高阻厚层反型外延片的一种实用生产技术,即在PE-2061S外延设备上,采取特殊的工艺控制在电阻率小于0.02Ω·cm的p型低阻衬底上实现了高阻厚层n型外延生长,外延层电阻率大于40Ω·cm,厚度大于100μm.研究表明:该外延材料完全可以满足IGBT器件制作的需要.     

激活退火对As掺杂型HgCdTe材料的影响

研究了激活退火热处理过程对As掺杂碲镉汞外延材料组分的影响,实验包括不同的热处理条件以及不同厚度外延材料,并用红外透射光谱测量了退火前后材料组分的变化。实验结果表明,在相同温度和相同时间的热处理条件下,外延层的厚度越厚,热处理对材料组分的影响越小;在相同温度不同时间的热处理过程中,随着时间增加,材料的组分变化也随之增加,并且,外延层越厚,组分的变化量也越小。     

ZnO缓冲层的厚度对HVPE-GaN外延层的影响

为了得到高质量的GaN材料,首先在c面蓝宝石(Al2O3)衬底上射频磁控溅射不同厚度的ZnO缓冲层,然后采用氢化物气相外延(HVPE)法在ZnO缓冲层上生长约5.2μm厚的GaN外延层,研究ZnO缓冲层的厚度对GaN外延层质量的影响。用微分干涉显微镜(DIC)、扫描电子显微镜(SEM)、X射线衍射(XRD)和光致发光(PL)技术研究分析了GaN外延层的表面形貌、结晶质量和光学特性。结果表明,ZnO缓冲层的厚度对GaN外延层的特性有着重要的影响,200 nm厚的ZnO缓冲层最有利于高质量GaN外延层的生长。     

用于制作场效应晶体管的砷化镓的电解腐蚀及电子迁移率

本文介绍了n型砷化镓的电解腐蚀技术,此工艺用来制作场效应晶体管管芯片,可把较厚的并且不均匀的材料腐蚀成均匀的外延薄层。用这种方法制备的薄外延层样品的霍耳效应测量表明,对于减薄到2100埃厚的外延层,其迁移率与砷化镓材料体迁移率的理论值相同。对复盖有阳极氧化物的外延层进行霍耳效应测量表明,氧化层界面俘获的电荷密度是3.9×10~(11)电子/厘米~2,比外延层生长后的表面电荷密度值大。     

InGaAs/InP材料的MOCVD生长研究

研究了InGaAs/InP材料的MOCVD生长技术和材料的性能特征。InP衬底的晶向偏角能够明显影响外延生长模型以及外延层的表面形貌,用原子力显微镜(AFM)观察到了外延层表面原子台阶的聚集现象(step-bunching现象),通过晶体表面的原子台阶密度和二维生长模型解释了台阶聚集现象的形成。对外延材料进行化学腐蚀,通过双晶X射线衍射(DCXRD)分析发现异质结界面存在应力,用异质结界面岛状InAs富集解释了应力的产生。通过严格控制InGaAs材料的晶格匹配,并优化MOCVD外延生长工艺,制备出厚层InGaAs外延材料,获得了低于1×1015cm-3的背景载流子浓度和良好的晶体质量。     

用于光电集成的GaAs/InP MESFET研究

提出了一种新的生长过渡层的方法，并利用低压金属有机气相外延技术在InP衬底上生长出高质量GaAs外延材料，用X射线双晶衍射测得5μm厚GaAs外延层的（004）品面行射半高峰宽（FWHM）低至140arcsee。并制出GaAs金属半导体场效应晶体管（MESFET），其单位跨导为100mS／mm，可满足与长波长光学器件进行单片集成的需要。     

新型功率器件IGBT研制

本文简述了ＩＧＢＴ的设计技术和制造工艺，对ＩＧＢＴ的Ｉ－Ｖ特性，开关特性及闩锁效应进行了系统的研究，结合实施工艺对ＩＧＢＴ的版 图及工艺进行了优化设计。合作开发了适于制作ＩＧＢＴ的异型厚外延材料，成功地制了１０Ａ／８００Ｖ，２０Ａ／１０５０Ｖ的ＩＧＢＴ芯片，给出了试制样品的测试结果。     

新型功率器件IGBT研制

简述了ＩＧＢＴ的设计技术和制造工艺。对ＩＧＢＴ的Ｉ－Ｖ特性，开关特性及闩锁效应了系统的研究，结合实际工艺对ＩＧＢＴ的版图及工艺进行了优化设计，合作开发了适于制作ＩＧＢＴ的异型厚外延材料。成功地制作了１０Ａ／８００Ｖ，２０Ａ／１０５０Ｖ的ＩＧＢＴ芯片，给出了试制样品的测试结果。     

Theory and application of a two-layer Hall technique

The electrical characterization of epitaxial layers on substrates of the opposite conductivity type presents serious problems if the p-n junction at the interface has significant leakage current such that it cannot be used to effectively electrically isolate the two regions. In order to meet the need for nondestructively characterizing such structures, a modification of the conventional Hall technique was developed in which the Hall measurements are made simultaneously on both the epitaxial layer and its substrate, the interface impedance is measured, and the interaction between the two regions is modeled and taken into account. This technique can be used to verify those cases in which the perturbing effects of a high-resistivity substrate are negligible, thus justifying conventional measurements on the epitaxial layer. In principle, it can be used to measure the resistivity and Hall coefficient of each layer separately if the assumptions of the model are realized in practice. The use of this technique is discussed and applied to the case of a thin n-type silicon epitaxial layer on: 1) a conducting substrate of indium-doped silicon that had a significant amount of leakage at the interface p-n junction and 2) a high-resistivity silicon substrate that had negligible influence on the measurement of the Hall coefficient of the epitaxial layer.     

Microwave silicon Schottky-barrier field-effect transistor

Schottky-barrier field-effect transistors have been realised in silicon epitaxial films on high-resistivity silicon substrates. The 1 ?m wide gates are produced by projection-masking techniques. The maximum transconductances observed are 42 mA/V per mm gate length; the maximum frequency of oscillation fmax was 8 GHz.     

A flat-panel display control IC with 150-V drivers

A flat-panel display control IC with 150-V drivers is realized in high-voltage analog/digital IC technology utilizing a low-cost p-n junction isolation process. An improved semiwell isolation structure that has an epitaxial layer of two different thicknesses is used. In order to achieve high-voltage push-pull operation, totem-pole-type output circuits are formed in the structure's thick, high-resistivity epitaxial area. A compact complementary transistor logic circuit is successfully integrated in the n-wells of the structure's thin epitaxial area to meet the high-speed requirement for control logic. A stacked circuit is used to reduce the standby power needs of the logic circuits.     

A Monolithic Single-Ended X-Band Mixer Circuit

A monolithic single-ended X-band mixer circuit has been fabricated on a high-resistivity silicon substrate, employing selective epitaxial deposition. The final resistivities of the N-type substrates are between 5000 and 17000 ohm-cm. The mixer diode is a molybdenum-silicon Schottky barrier diode. The overall single-sideband noise figure for the circuit obtained at 9 GHz was 10.5 dB.     

Effect of undepleted high-resistivity region on microwave efficiency of GaAs IMPATT diodes

Degradation of the microwave efficiency due to the undepleted high-resistivity epitaxial region was experimentally found to be remarkably, small on GaAs X-band conventional-type IMPATT diodes. The result seems to be consistent with large low-field drift mobility for electrons in GaAs. Present study confirms the superiority of n-GaAs over other materials for IMPATT diode use.     

GaAs f.e.t.s with silicon-implanted channels

Field-effect transistors with channel doping profiles fabricated by the implantation of silicon ions into high-resistivity vapour phase epitaxial GaAs have given noise figures of 2.9 dB with an associated gain of approximately 5 dB at 10 GHz. Similar measurements on F.E.T.S fabricated in an identical manner, except for the channel fabrication, where silicon ions were implanted directly into a Cr-doped semi-insulating GaAs substrate, have resulted in nose figures typically 1 dB higher.     

GaAs on Si as a substrate for microwave and millimeter-wavemonolithic integration

The authors calculated the effective dielectric constant, characteristic impedance, and dielectric loss of a shielded microstrip line manufacture on namely GaAs, Si, and GaAs/Si. Dielectronic loss versus frequency for the GaAs and Si substrates are shown. The same parameters for GaAs/Si substrate were plotted for two different resistivities of the GaAs overlay material, and for each of three different GaAs overlayer thicknesses. The measurements covered the 10-100-GHz frequency range. Depending on the thickness, results show that high-resistivity GaAs epitaxial layers on Si substrates having moderate resistivities reduce the dielectric loss     

Electrical and structural properties of pulse laser-annealed polycrystalline silicon films

Doped epitaxial films of Si on single-crystal high-resistivity Si substrates have been prepared using ion implantation and Q-switched ruby laser annealing of LPCVD polycrystalline Si layers. Films, doped with B or As in the range 10¹⁷to 5 × 10²⁰cm^-3were studied by the measurement of their resistivities, Hall mobilities, and doping density profiles. The good film quality achieved permitted the fabrication of p-channel MOS transistors which, through measurements of threshold voltage and transconductance, yielded additional data on the surface mobility and the integrity of the Si-SiO2interface. The electrical properties of the films compared favorably with those of similarly doped single-crystal material, and transmission electron microscopy was used to confirm the good structural quality of the epitaxial growth.     

An epitaxial planar structure for the unijunction transistor

A unijunction transistor with fast recovery time and high interbase resistance is made by growing a thin high-resistivity boron-doped epitaxial layer on a low-resistivity arsenic-doped substrate. Ring-and-dot base contacts are made directly on the p-type epitaxial layer with the beam-lead contact process. With the dot grounded and a negative bias on the ring, the most positive point along the edge of the space-charge region in the epitaxy is centered below the dot. When the substrate is adequately biased in the forward direction with respect to this point, conductivity modulation of the spreading resistance under the dot begins because of minority charge injection from the substrate. Experimental devices have been made by growing a 7.1-micron 53.1-Ω.cm epitaxial layer on a 5Ω.cm substrate. Interbase resistance was ∼ 100k Ω, intrinsic stand-off ratio ∼ 0.5, holding current ∼ 1 mA, and recovery time <20 ns. The paper concludes with possible memory array and shift register circuit applications that incorporate the unit described as well as a junction-isolated version that is free of parasitic transistors.     

Optical and electrical properties of 4<Emphasis Type="Italic">H</Emphasis>-SiC irradiated with fast neutrons and high-energy heavy ions

Photoluminescence and deep-level transient spectroscopy are used to study the effect of irradiation with fast neutrons and high-energy Kr (235 MeV) and Bi (710 MeV) ions on the optical and electrical properties of high-resistivity high-purity n-type 4H-SiC epitaxial layers grown by chemical vapor deposition. Electrical characteristics were studied using the barrier structures based on these epitaxial layers: Schottky barriers with Al and Cr contacts and p⁺-n-n⁺ diodes fabricated by Al ion implantation. According to the experimental data obtained, neutrons and high-energy ions give rise to the same defect-related centers. The results show that, even for the extremely high ionization density (34 keV/nm) characteristic of Bi ions, the formation of the defect structure in SiC single crystals is governed by energy losses of particles due to elastic collisions.