Improving cooling effectiveness by use of chamfers on the top of electronic components

A Computational Fluid Dynamic (CFD) study based on Reynolds Averaged Navier–Stokes (RANS) approach is carried out to predict the mean velocity field and the heat transfer rate of an impinging jet in cross-flow configuration on a heated wall-mounted cube. Targeting an electronic cooling configuration, the aim is to investigate the effect of geometrical modification of the component on the cooling effectiveness. For the same cross flow Reynolds number Re_H = 3410, three levels of impinging jets are computed as well as a case without impinging jet that will serve as baseline case for comparison. The results from the RANS computation are compared to experimental data from published scientific literature. The validation shows qualitatively good agreement and almost all flow structures are well reproduced by the computation. In an attempt to optimize the wall heat flux over the cube surface, a new geometry is proposed without sharp corners on the top cube face. Numerical results show that with minor geometrical modification (chamfer), the fluid flow structure around the electronic component is radically transformed and the heat transfer rate can be improved. The highest cooling effectiveness improvement is realize for the highest Reynolds number ratio Re_j/Re_H = 1.5 and for the chamfer height of 4 mm.     

High-performance C60 and picene thin film field-effect transistors with conducting polymer electrodes in bottom contact structure

C₆₀ and picene thin film field-effect transistors (FETs) in bottom contact structure have been fabricated with poly(3,4-ethylenedioxythiophene): poly(styrenesulfonate) (PEDOT:PSS) electrodes for a realization of mechanical flexible organic FETs. The C₆₀ thin film FETs showed n-channel enhancement-type characteristics with the field-effect mobility μ value of 0.41 cm² V^?1 s^?1, while the picene thin film FET showed p-channel enhancement-type characteristics with the μ of 0.61 cm² V^?1 s^?1. The μ values recorded for C₆₀ and picene thin film FETs are comparable to those for C₆₀ and picene thin film FETs with Au electrodes.     

Scaling down of organic complementary logic gates for compact logic on foil

In this work, we realize complementary circuits with organic p-type and n-type transistor integrated on polyethylene naphthalate (PEN) foil. We employ evaporated p-type and n-type organic semiconductors spaced side by side in bottom-contact bottom-gate coplanar structures with channel lengths of 5 μm. The area density is 0.08 mm² per complementary logic gate. Both p-type and n-type transistors show mobilities >0.1 cm²/V s with V_on close to zero volt. Small circuits like inverters and 19-stage ring oscillators (RO) are fabricated to study the static and the dynamic performance of the logic inverter gate. The circuits operate at V_dd as low as 2.5 V and the inverter stage delay at V_dd = 10 V is as low as 2 μs. Finally, an 8 bit organic complementary transponder chip with data rate up to 2.7 k bits/s is fabricated on foil by successfully integrating 358 transistors.     

Organic light-emitting diodes based on an ambipolar single crystal

Slice-like organic single crystals of 1,4-bis(2-cyano-2-phenylethenyl)benzene (BCPEB) are grown by the physical vapor transport (PVT) method, and exhibit a very high photoluminescence quantum efficiency (Φ_PL) of 75%. The ambipolar behavior of BCPEB single crystals are confirmed using the time of flight technique. The high efficiency and balanced (μ_h = 0.059 cm²/Vs and μ_e = 0.070 cm²/Vs) carriers’ mobility imply that the BCPEB single crystal is a promising light-emitting layer in the diodes structure. Intense green electroluminescence (EL) from a diode has been successfully demonstrated at an applied electric field of 2 × 10⁵ V/cm.     

Operational frequency degradation induced trapping in scaled GaN HEMTs

Cut-off frequency increase from 12.1 GHz to 26.4 GHz, 52.1 GHz and 91.4 GHz is observed when the 1 μm gate length GaN HEMT is laterally scaled down to L_G = 0.5 μm, L_G = 0.25 μm and L_G = 0.125 μm, respectively. The study is based on accurately calibrated transfer characteristics (I_D-V_GS) of the 1 μm gate length device using Silvaco TCAD. If the scaling is also performed horizontally, proportionally to the lateral (full scaling), the maximum drain current is reduced by 38.2% when the gate-to-channel separation scales from 33 nm to 8.25 nm. Degradation of the RF performance of a GaN HEMT due to the electric field induced acceptor traps experienced under a high electrical stress is found to be about 8% for 1 μm gate length device. The degradation of scaled HEMTs reduces to 3.5% and 7.3% for the 0.25 μm and 0.125 gate length devices, respectively. The traps at energy level of E_T = E_V + 0.9 eV (carbon) with concentrations of N_IT = 5 × 10¹⁶cm^− 3, N_IT = 5 × 10¹⁷cm^− 3 and N_IT = 5 × 10¹⁸cm^− 3 are located in the drain access region where highest electrical field is expected. The effect of traps on the cut-off frequency is reduced for devices with shorter gate lengths down to 0.125 μm.     

Offset-fed complementary split ring resonators loaded monopole antenna for multiband operations

A miniaturized multiband monopole antenna based on rectangular-shaped Complementary Split Ring Resonators (CSRRs) with offset-fed microstrip line is proposed for Global System for Mobile Communication (GSM) and Wireless Local Area Network (WLAN) applications. The proposed antenna is fabricated on a FR-4 substrate having a dielectric constant (ɛ_r) of 4.4 within a small size of 19.18 × 22.64 × 1.6 mm³. CSRRs in the monopole antenna create a multiband characteristics and bandwidth improvement, which is analyzed by use of the precise quasi-static design equations and electromagnetic simulation software (HFSS version 13). By selecting a proper offset-fed microstrip line, it is capable to achieve 50 Ω characteristic impedance and good impedance matching. The parameter extraction procedure of the metamaterial property of the CSRRs is enlightened in detail, by which the negative permittivity existence and the new resonance frequencies are verified. Simulated and measured result coincides with each other. The measured H-Plane (azimuthal plane) exhibits omnidirectional radiation pattern and E-plane (elevation plane) shows a dipole like bidirectional radiation pattern. The proposed antenna has adequate advantages, including simple design, small size, lower return loss and capable of multiband operations.     

Planar copper-tin inter-metallic film formation on strained substrates

This paper presents the results of four-point bending tests investigating the effects of substrate strain on the growth ɛ of interfacial Cu–Sn inter-metallic compounds (IMCs). Test specimens were cut into strips, 27.5 mm in length and 5 mm in width, from 4 in. double polished silicon wafers. A very thin adhesion layer (Ta) was deposited on the silicon substrate by sputtering followed by a 10 μm thick layer of copper using electroplating. Finally, a 30 μm tin layer was deposited over the copper film also by electroplating. Samples were then placed in a furnace at 200 °C to undergo bending in order to introduce in-plane strain under tension or compression. Control samples also underwent the same treatment without applied strain. Our aim was to investigate the influence of substrate strain and aging time on the formation of IMCs (1.54 × 10⁻⁴, 2.3 × 10⁻⁴ and 3.46 × 10⁻⁴). The thickness and separation of each phase (Cu₃Sn) and η (Cu₆Sn₅) are clearly visible in scanning electron microscope images. Compressive strain and tensile strain both increased the thickness of the IMC layer during the aging process; however, the effects of compressive strain were more pronounced than those of tensile strain. We hypothesize that the increase in IMC thickness is related to the strain enhanced out-diffusion of Cu towards the solder as well as strain in the underlying lattice at the diffusion interface.     

Fabrication of single crystal field-effect transistors with phenacene-type molecules and their excellent transistor characteristics

Single crystal field-effect transistors (FETs) using [6]phenacene and [7]phenacene show p-channel FET characteristics. Field-effect mobilities, μs, as high as 5.6 × 10^?1 cm² V^?1 s^?1 in a [6]phenacene single crystal FET with an SiO₂ gate dielectric and 2.3 cm² V^?1 s^?1 in a [7]phenacene single crystal FET were recorded. In these FETs, 7,7,8,8-tetracyanoquinodimethane (TCNQ) was inserted between the Au source/drain electrodes and the single crystal to reduce hole-injection barrier heights. The μ reached 3.2 cm² V^?1 s^?1 in the [7]phenacene single crystal FET with a Ta₂O₅ gate dielectric, and a low absolute threshold voltage |V_TH| (6.3 V) was observed. Insertion of 2,3,5,6-tetrafluoro-7,7,8,8-tetracyanoquinodimethane (F₄TCNQ) in the interface produced very a high μ value (4.7–6.7 cm² V^?1 s^?1) in the [7]phenacene single crystal FET, indicating that F₄TCNQ was better for interface modification than TCNQ. A single crystal electric double-layer FET provided μ as high as 3.8 × 10^?1 cm² V^?1 s^?1 and |V_TH| as low as 2.3 V. These results indicate that [6]phenacene and [7]phenacene are promising materials for future practical FET devices, and in addition we suggest that such devices might also provide a research tool to investigate a material’s potential as a superconductor and a possible new way to produce the superconducting state.     

105 nm Gate length pMOSFETs with high-K and metal gate fabricated in a Si process line on 200 mm GeOI wafers

We report on the fabrication and electrical characterization of deep sub-micron (gate length down to 105 nm) GeOI pMOSFETs. The Ge layer obtained by hetero-epitaxy on Si wafers has been transferred using the Smart Cut^TM process to fabricate 200 mm GeOI wafers with Ge thickness down to 60–80 nm. A full Si MOS compatible pMOSFET process was implemented with HfO₂/TiN gate stack. The electrical characterization of the fabricated devices and the systematic analysis of the measured performances (I_ON, I_OFF, transconductance, low field mobility, S, DIBL) demonstrate the potential of pMOSFET on GeOI for advanced technological nodes. The dependence of these parameters have been analyzed with respect to the gate length, showing very good transport properties (μ_h ～ 250 cm²/V/s, I_ON = 436 μA/μm for L_G = 105 nm), and OFF current densities comparable or better than those reported in the literature.     

Modeling of Ga1−xInxAs1−y−zNySbz/GaAs quantum well properties for near-infrared lasers

The aim of this work is to model the properties of GaInAsNSb/GaAs compressively strained structures. Indeed, Ga_1?xIn_xAs_1?y?zN_ySb_z has been found to be a potentially superior material to GaInAsN for long wavelength laser dedicated to optical fiber communications. Furthermore, this material can be grown on GaAs substrate while having a bandgap smaller than that of GaInNAs. The influence of nitrogen and antimony on the bandgap and the transition energy is explored. Also, the effect of these two elements on the optical gain and threshold current density is investigated. For example, a structure composed of one 7.5 nm thick quantum well of material with In=30%, N=3.5%, Sb=1% composition exhibits a threshold current density of 339.8 A/cm² and an emission wavelength of 1.5365 μm (at T=300 K). It can be shown that increasing the concentration of indium to 35% with a concentration of nitrogen and antimony, of 2.5% and 1%, respectively, results in a decrease of the threshold current density down to 253.7 A/cm² for a two well structure. Same structure incorporating five wells shows a threshold current density as low as 221.4 A/cm² for T=300 K, which agrees well with the reported experimental results.     

Self-aligned inversion n-channel In0.2Ga0.8As/GaAs metal–oxide–semiconductor field-effect-transistors with TiN gate and Ga2O3(Gd2O3) dielectric

A self-aligned process for fabricating inversion n-channel metal–oxide–semiconductor field-effect-transistors (MOSFET’s) of strained In_0.2Ga_0.8As on GaAs using TiN as gate metal and Ga₂O₃(Gd₂O₃) as high κ gate dielectric has been developed. A MOSFET with a 4 μm gate length and a 100 μm gate width exhibits a drain current of 1.5 mA/mm at V_g = 4 V and V_d = 2 V, a low gate leakage of <10^?7 A/cm² at 1 MV/cm, an extrinsic transconductance of 1.7 mS/mm at V_g = 3 V, V_d = 2 V, and an on/off ratio of ～10⁵ in drain current. For comparison, a TiN/Ga₂O₃(Gd₂O₃)/In_0.2Ga_0.8As MOS diode after rapid thermal annealing (RTA) to high temperatures of 750 °C exhibits excellent electrical and structural performances: a low leakage current density of 10^?8–10^?9 A/cm², well-behaved capacitance–voltage (C–V) characteristics giving a high dielectric constant of ～16 and a low interfacial density of state of ～(2～6) × 10¹¹ cm^?2 eV^?1, and an atomically sharp smooth Ga₂O₃(Gd₂O₃)/In_0.2Ga_0.8As interface.     

Solution processable poly(2,5-dialkyl-2,5-dihydro-3,6-di-2-thienyl-pyrrolo[3,4-c]pyrrole-1,4-dione) for ambipolar organic thin film transistors

Solution processable diketopyrrolopyrrole (DPP)-bithiophene polymers (PDBT) with long branched alkyl side chains on the DPP unit are synthesized. These polymers have favourable highest occupied molecular orbital (HOMO) and lowest unoccupied molecular orbital (LUMO) energy levels for the injection and transport of both holes and electrons. Organic thin film transistors (OTFTs) using these polymers as semiconductors and gold as source/drain electrodes show typical ambipolar characteristics with very well balanced high hole and electron mobilities (μ_h = 0.024 cm² V^?1 s^?1 and μ_e = 0.056 cm² V^?1 s^?1). These simple and high-performing polymers are promising materials for ambipolar organic thin film transistors for low-cost CMOS-like logic circuits.     

Ambipolar field-effect transistors with bilayered thiophene/phenylene co-oligomers

Bilayered organic field-effect transistors were fabricated by successive vapor-depositions of 1,4-bis{5-[4-(trifluoromethyl)phenyl]thiophene-2-yl}benzene (AC5-CF₃) and 5,5″-bis(4-biphenylyl)-2,2′:5′,2″-terthiophene (BP3T). With decreasing thickness of the n-type AC5-CF₃ film in contact with the dielectric layer, ambipolar characteristics were improved under both positive and negative gate biases. Two types of asymmetric source/drain electrodes were prepared by either obliquely shadowed lamination or mask-shifted depositions of AlLi and Au. The latter method in which the device was characterized without exposure to air after the electrode deposition of AlLi resulted in remarkable improvement of ambipolarity and reduction of leak currents. Finally, optimized ambipolar mobilities of μ_e = 5.00 × 10^?2 and μ_h = 1.56 × 10^?2 cm² V^?1 s^?1) were obtained with 5-nm-thick AC5-CF₃ and 30-nm-thick BP3T.     

Realizing high breakdown voltage for a novel interface charges islands structure based on partial-SOI substrate

A novel interface charge islands partial-SOI (ICI PSOI) high voltage device with a silicon window under the source and its mechanism are studied in this paper. ICI PSOI is characterized by a series of equidistant high concentration n⁺-regions on the bottom interface of top silicon layer. On the condition of high-voltage blocking state, inversion holes located in the spacing of two n⁺-regions effectively enhance the electric field of the buried oxide layer (E_I) and reduce the electric field of the silicon layer (E_S), resulting in a high breakdown voltage (V_B). It is shown by the simulations that the enhanced field ΔE_I and reduced field ΔE_S by the accumulated holes reach to 449 V/μm and 24 V/μm, respectively, which makes V_B of ICI PSOI increase to 663 V from 266 V of the conventional PSOI on 5 μm silicon layer and 1 μm buried oxide layer with the same silicon window length. On-resistance of ICI PSOI is lower than that of the conventional PSOI. Moreover, self-heating-effect is alleviated by the silicon window in comparison with the conventional SOI at the same power of 1 mW/μm.     

The effect of gate overlap lightly doped drains on low temperature poly-Si thin film transistors

Low temperature polycrystalline silicon (LTPS) thin-film transistors (TFTs) have a high carrier mobility that enables the design of small devices that offer large currents and fast switching speeds. However, the electrical characteristics of the conventional self-aligned polycrystalline silicon (poly-Si) TFTs are known to present several undesired effects, such as large leakage currents, the kink effect, and the hot-carrier effect. For this paper, LTPS TFTs were fabricated, and the SiN_x/SiO₂ gate dielectrics and the effect of the gate-overlap lightly doped drain (GOLDD) were analyzed in order to minimize these undesired effects. GOLDD lengths of 1, 1.5 and 2 μm were used, while the thickness of the gate dielectrics (SiN_x/SiO₂) was fixed at 65 nm (40 nm/25 nm). The electrical characteristics show that the kink effect is reduced in the LTPS TFTs using a more than 1.5 μm of GOLDD length. The TFTs with the GOLDD structure have more stable characteristics than the TFTs without the GOLDD structure under bias stress. The degradation from the hot-carrier effect was also decreased by increasing the GOLDD length. After applying the hot-carrier stress test, the threshold voltage variation (ΔV_TH) was decreased from 0.2 V to 0.06 V by the increase of the GOLDD length. The results indicate that the TFTs with the GOLDD structure were protected from the degradation of the device due to the decreased drain field. From these results it can be seen that the TFTs with the GOLDD structure can be applied to achieve high stability and high performance in driving circuit applications for flat-panel displays.     

Influence of processing and annealing steps on electrical properties of InAlN/GaN high electron mobility transistor with Al2O3 gate insulation and passivation

We report on preparation and electrical characterization of InAlN/AlN/GaN metal–oxide–semiconductor high electron mobility transistors (MOS HEMTs) with Al₂O₃ gate insulation and surface passivation. About 12 nm thin high-κ dielectric film was deposited by MOCVD. Before and after the dielectric deposition, the samples were treated by different processing steps. We monitored and analyzed the steps by sequential device testing. It was found that both intentional (ex situ) and unintentional (in situ before Al₂O₃ growth) InAlN surface oxidation increases the channel sheet resistance and causes a current collapse. Post deposition annealing decreases the sheet resistance of the MOS HEMT devices and effectively suppresses the current collapse. Transistors dimensions were source-to-drain distance 8 μm and gate width 2 μm. A maximum transconductance of 110 mS/mm, a drain current of ～0.6 A/mm (V_GS = 1 V) and a gate leakage current reduction from 4 to 6 orders of magnitude compared to Schottky barrier (SB) HEMTs was achieved for MOS HEMT with 1 h annealing at 700 °C in forming gas ambient. Moreover, InAlN/GaN MOS HEMTs with deposited Al₂O₃ dielectric film were found highly thermally stable by resisting 5 h 700 °C annealing.     

Study on mobility enhancement in MOVPE-grown AlGaN/AlN/GaN HEMT structures using a thin AlN interfacial layer

Al_0.26Ga_0.74N/AlN/GaN high-electron-mobility transistor (HEMT) structures with AlN interfacial layers of various thicknesses were grown on 100-mm-diameter sapphire substrates by metalorganic vapor phase epitaxy, and their structural and electrical properties were characterized. A sample with an optimum AlN layer thickness of 1.0 nm showed a highly enhanced Hall mobility (μ_Hall) of 1770 cm²/Vs with a low sheet resistance (ρ_s) of 365 Ω/sq. (2DEG density n_s = 1.0 × 10¹³/cm²) at room temperature compared with those of a sample without the AlN interfacial layer (μ_Hall = 1287 cm²/Vs, ρ_s = 539 Ω/sq., and n_s = 0.9 × 10¹³/cm²). Electron transport properties in AlGaN/AlN/GaN structures were theoretically studied, and the calculated results indicated that the insertion of an AlN layer into the AlGaN/GaN heterointerface can significantly enhance the 2DEG mobility due to the reduction of alloy disorder scattering. HEMTs were successfully fabricated and characterized. It was confirmed that AlGaN/AlN/GaN HEMTs with the optimum AlN layer thickness show superior DC properties compared with conventional AlGaN/GaN HEMTs.     

High power 4H–SiC pin diodes (10 kV class) with record high carrier lifetime

The hole lifetime τ_p in the n-base and isothermal (pulse) current–voltage characteristics have been measured in 4H–SiC diodes with a 10 kV blocking voltage (100 μm base width). The τ_p value found from open circuit voltage decay (OCVD) measurements is 3.7 μs at room temperature. To the best of the authors’ knowledge, the above value of τ_p is the highest reported for 4H–SiC. The forward voltage drops V_F are 3.44 V at current density j = 100 A/cm² and 5.45 V at j = 1000 A/cm². A very deep modulation of the blocking base by injected non-equilibrium carriers has been demonstrated. Calculations in term of a simple semi-analytical model describe well the experimental results obtained.     

A facile chemical reduction approach for effectively tuning thermoelectric properties of PEDOT films

Poly(3,4-ethylenedioxythiophene)–tosylate–polyethylene glycol–polypropylene glycol–polyethylene glycol (PEDOT–Tos–PPP) films were prepared via a vapor phase polymerization (VPP) method. The films possess good electrical conductivity (1550 S cm⁻¹), low Seebeck coefficient (14.9 μV K⁻¹) and thermal conductivity (0.501 W m⁻¹ K⁻¹), and ZT ∼ 0.02 at room temperature (RT, 295 K). Then, the films were treated with NaBH₄/DMSO solutions of different NaBH₄ concentrations to adjust the redox level. After the NaBH₄/DMSO treatment (dedoping), the electrical conductivity of the films continuously decreased from 1550 to 5.7 S cm⁻¹, whereas the Seebeck coefficient steeply increased from 14.9 to 143.5 μV K⁻¹. A maximum power factor of 98.1 μW m⁻¹ K⁻² has been achieved at an optimum redox level. In addition, the thermal conductivity of the PEDOT–Tos–PPP films decrease from 0.501 to 0.451 W m⁻¹ K⁻¹ after treated with 0.04% NaBH₄/DMSO solution. A maximum ZT value of 0.064 has been achieved at RT. The electrical conductivity and thermal conductivity (Seebeck coefficient) of the untreated and 0.04% NaBH₄/DMSO treated PEDOT–Tos–PPP films decrease (increases) with increasing temperature from 295 to 385 K. And the power factor of the films monotonically increases with temperature. The ZT at 385 K of the 0.04% NaBH₄/DMSO treated film is 0.155.     

Measurements of n-InGaAs with MBE layers: Relevance of negative magnetoresistance in the investigated samples

Measurements of n_H were performed. n_H values showed a distinct increase at temperatures below ~90 K (1.1 μm n-InGaAs samples) and a decrease at temperatures below ~30 K (7 μm n-InGaAs samples), depending on the doping level. These trends might be related to the magnetoresistance (MR) of the n-InGaAs samples. The MR behavior of the n-InGaAs samples with respect to magnetic field and temperature was apparently dependent on the doping level. Two n-InGaAs samples, one of which had a thin InGaAs epilayer (1.1 μm) and the other with a thicker (7 μm) epilayer, showed interesting behavior at low temperature. Their behavior at magnetic fields of approximately −15000 to +15,000 G were determined. The resistivity ((ρ_G – ρ₀)/ρ₀) of the 1.1 μm sample was negative at temperatures lower than 30 K.