Reliability improvements in 50 nm MLC NAND flash memory using short voltage programming pulses

For the first time, an innovative programming methodology based on the use of ultra-short voltage pulses is applied in NAND flash architecture. The methodology starts from the physics of SILC dynamics and oxide damage, and relies on the trade-off between duration and amplitude of short voltage programming pulses, minimizing the creation of new traps in the tunnel oxide. The short pulses programming technique is applied on a small 50 nm NAND array designed for multibit application. Benefits of the short-pulse operation lie in that data retention and endurance which show meaningful improvements. The result is relevant for application in multibit technology, and opens the way to more aggressive cell scaling rules.     

Time-domain writing architecture for multilevel RRAM cells resilient to temperature and process variations

The high potential of memristors as multilevel resistance devices is undermined by their highly non-linear behaviour and a strong dependency on different sources of variability (process, voltage, temperature…). Temperature fluctuations are specially harmful because small thermal variations may significantly modify the operation point of the device. For these reasons the circuitry required to accurately read or write multilevel devices is complex and area demanding, especially if multi-level storage is considered. This work addresses the problem of accurately writing a given resistance value in a memristive cell by using a time-domain architecture found on variable pulses. Temperature resiliency is achieved after performing an in depth analysis of the definition of the resistance levels in the presence of thermal variations. Furthermore, a calibration procedure has been conceived to make the writing circuitry resilient to device to device variations. Experimental results show that the proposed approach is valid for a wide temperature range.     

利用射频与高压直接耦合等离子体注入进行不锈钢表面改性

介绍了一种新的等离子体离子注入在不锈钢表面改性上的应用.将高压脉冲和射频脉冲直接耦合到工件上,不需外部等离子体源,利用工件自身加射频产生等离子体,随后施加高压对不锈钢表面进行了注氮处理.XPS分析显示,在基体表面有氮元素存在,说明实现了射频与高压直接耦合的离子注入效果.进一步研究表明,等离子体离子注入后,在不锈铜基体表层形成了Cr2O3以及CrN,FeN等硬质相,因此处理后的试件耐摩擦、磨损和耐腐蚀性能得到了较大提高.同时研究显示,射频脉冲宽度或射频与高压相位的改变对摩擦系数影响不大.     

非正弦波通信时域正交椭圆球面波脉冲设计方法

针对非正弦波信号的频带传输问题,同时为了有效提高非正弦波通信系统的频带利用率及功率利用率,提出了时域正交椭圆球面波脉冲集设计方法。通过参数设置、频段划分、求解方程、Schmidt正交化等步骤设计时域正交椭圆球面波脉冲集,调整脉冲参数实现脉冲集信号的频谱搬移与频谱控制,脉冲集信号为频谱特性可控的带限信号。仿真结果表明:时域正交椭圆球面波脉冲集具有较好的能量聚集性,利用该脉冲集实现多路信息并行传输时,在保证系统具有较好的功率利用率前提下,系统的频带利用率可快速接近奈奎斯特速率。     

Five-stepped PWM inverter used in photovoltaic systems

A PWM (pulse-width-modulated) inverter that has five-stepped output-voltage levels is introduced. In this inverter, the waveform of the output voltage has a smaller harmonic content than that of a conventional PWM inverter. A novel PWM technique is analyzed. The PWM pulses included in the waveform of the output voltage are formed using a criterion based on the calculation that each area of voltage pulses is equal to the integrated value of each time shared area of a reference sinusoidal waveform. This PWM technique for the five-stepped PWM inverter is superior to the conventional PWM technique, and the experimental results coincided with the calculation obtained using the fast Fourier transform. In addition, the relations between the number of PWM pulses and the harmonic contents of the output voltage are described     

Nd: Sr5 (PO4) 3F Crystal Laser Characteristics Using GaAs as Passive Q-switch

It is investigated the properties of a diode-pumped Nd: Sr5 ( PO4 )3F laser that is passively Q-switched by a thin, single crystal GaAs wafer. The short high-peak-power pulses of the laser have been obtained. The pulse energies, pulse widths and pulse repetition rates for different conditions have been measured and the experimental results show that GaAs is an excellent passive Q-switch of the diode-pumped Nd: Sr5(PO4)3F lasers.     

Reduction of threshold voltage for bistable liquid-crystal switching using a priming voltage

A method is described for reducing the threshold field required to achieve high-speed matrix addressing of a bistable nematic liquid-crystal storage display. A short ac priming voltage pulse applied to the device modifies the binding energy for disclinations attached to sites of orientational discontinuity, thereby changing the threshold field for electrical switching between bistable states. The threshold reduction depends on the ac frequency and width of the writing pulse. The physical mechanism underlying this effect is described. Matrix addressing (3:1) with 2-ms pulses has been demonstrated with select voltage levels as low as 2 V0= 70 V and nonselect levels of V0= 35 V.     

Transmission line based energy recovery circuits and theirapplication in copper vapor laser systems

Energy recovery of narrow, high power pulses based on loss free resistor topology is described. A novel regenerative snubber realization based on transmission lines is presented. The purpose of this snubber is to recycle high voltage, high power (up to 20 kV 1 MW) parasite pulses which arise in a copper vapor laser. These pulses consume up to 40% of the total power of the system. Currently, a low voltage (170 V) circuit of this type has been constructed and operated at recycling efficiency up to 85%     

Sociological insights on the comparison of writing/reading on paper with writing/reading digitally

The aim of this article is to investigate the impact of digital technologies on writing and reading within an educational rather than business environment. It explores the affordances of writing and reading on paper and those of writing on a keyboard and reading on a screen. The analysis is based on an exploratory study carried out with a class of Masters Students in Multimedia Communication and Technologies of Information at the University of Udine (Italy) who were asked to write an essay on this topic. The methodology applied in this study is qualitative content analysis of the essays produced by the students. The principal results of this study show that reading and writing competencies are changing with the use of digital technologies but that paper and digital interactions are not mutually exclusive. Students are more productive textually with writing than with reading, however, they still see the virtues of writing on paper which they continue to use extensively. It appears that chirographic writing and paper is more multi-sensorial and meta-communicative than using the keyboard or screen. Further research is recommended to explore this complementarities of writing on paper and on screen/keyboard as well as the perceived changes in preferred sources of reading material.     

CMOS level shifters from 0 to 18 V output

A design methodology for level shifters voltage translators, where the output voltage ranges from 0 to 18 V, and the input voltage ranges from 2 to 5.5 V in a 0.6 µm CMOS-HV technology, is presented. This family of circuits have a special interest in the case of implantable medical devices where is common to handle previously unknown voltages either positive or negative, above or below the control logic supply V_DD. Two application examples are presented: a composite switch to control negative stimuli voltage pulses, and a multi-channel programmable charge-pump voltage multiplier, aimed at charging the output capacitors of an IMD.

     

红外焦平面读出电路片上驱动电路设计

线列红外焦平面读出电路在正常工作时需要提供多路数字脉冲和多路直流偏置电压。本文基于0.5 μm CMOS工艺设计了一款驱动电路芯片,为电容负反馈放大型（CTIA）读出电路（ROIC）提供驱动信号。电路芯片采用带隙基准电路产生低噪声低温漂的直流偏置电压,采用数字逻辑电路生成CLK1,CLK2,RESET等八路数字脉冲。仿真及测试结果表明：驱动电路芯片输出的数字脉冲及偏置电压符合设计值,可驱动CTIA型线列红外焦平面读出电路稳定工作。     

Improvement of output voltage control performance for low-speed operation of matrix converter

The matrix converter (MxC) is an ac-to-ac conversion device that can generate variable frequency and variable voltage output. The nine bidirectional switches of an MxC allow pulse-width modulation (PWM) control of input currents and output voltages. PWM switches need "switch commutations" from one switch to another. During these switch commutations, however, unwanted voltage error occurs like a dead time effect in a voltage source inverter (VSI). When PWM pulse-widths are narrower than the time for completing a commutation sequence, voltage error rapidly increases. In the low-speed range, PWM pulses become narrower and voltage distortions become larger due to incomplete commutations. Moreover, these errors are critical in the low-speed operation because the system is sensitive to the smallest voltage error. In this paper, a new PWM strategy is proposed for improving voltage control performance in the low-speed range. Based on the input and output voltage information, PWM pulse-widths are controlled to avoid incomplete commutation. The feasibility of the proposed method is proved through simulation and experimental results.     

Ladder-shaped network for ESD protection of millimetre-wave CMOS ICs

A compact ladder-shaped electrostatic discharge (ESD) protection circuit is presented for millimetre-wave integrated circuits (ICs) in CMOS technology. Multiple shorted shunt stubs form a ladder network together with series stubs as ESD protection that discharges current/voltage pulses caused by an ESD event, while at the same time the network is embedded as part of the matching circuit for a normal operation. A 60 GHz low-noise amplifier using a 90 nm CMOS process is demonstrated with the proposed ESD protection methodology that introduces less than 1 dB insertion loss. Owing to the ESD current distribution through multiple shorted stubs, the proposed methodology is useful to millimetre-wave ICs with advanced CMOS technology that suffers from higher sheet resistance of the metal layers.     

LiNbO3:Fe晶体中飞秒二波耦合光栅衍射自增强现象

在超快二波耦合配置下的LiNbO3：Fe晶体中写人了体相位栅，通过一定的脉冲写人方法进行飞秒脉冲写人光栅的衍射自增强实验，在双光写人饱和后进行单写人光照射，产生了持续1h的衍射自增强，同时又发现在光栅写人未饱和的时候改为单光写人也产生了衍射自增强现象，持续2h。随后从光调制角度分析了该自增强现象的理论原因：脉冲衍射光和写人光共同作用，提高了二者耦合程度，写人了新光栅，从而加强原光栅，导致衍射效率提高，从而证明飞秒脉冲写人光栅的读出擦除可抑制，这对提高光全息记录的读出质量有正面意义。     

A statistical methodology as applied to a 256 Mbit DRAM passtransistor design

We present a novel design for manufacturing (DFM) methodology that has been applied to the design of a pass transistor for 256 Mbit DRAM. The design inputs that include gate oxide thickness, which limits the booted wordline voltage, the threshold voltage adjust implant, and the substrate bias voltage, for different channel lengths, are optimized to meet the constraints on performance, reliability, and robustness against manufacturing variations. The problems associated with applying conventional DFM techniques are discussed and a new methodology based on “margins” is presented. The results pertaining to the optimized DRAM pass transistor design for a power supply voltage V_cc=2.5 V are presented,     

Voltage Optimization of Power Delivery Networks through Power Bump and TSV Placement in 3D ICs

To reduce interconnect delay and power consumption while improving chip performance, a three‐dimensional integrated circuit (3D IC) has been developed with die‐stacking and through‐silicon via (TSV) techniques. The power supply problem is one of the essential challenges in 3D IC design because IR‐drop caused by insufficient supply voltage in a 3D chip reduces the chip performance. In particular, power bumps and TSVs are placed to minimize IR‐drop in a 3D power delivery network. In this paper, we propose a design methodology for 3D power delivery networks to minimize the number of power bumps and TSVs with optimum mesh structure and distribute voltage variation more uniformly by shifting the locations of power bumps and TSVs while satisfying IR‐drop constraint. Simulation results show that our method can reduce the voltage variation by 29.7% on average while reducing the number of power bumps and TSVs by 76.2% and 15.4%, respectively.     

Nanofabrication on gold surface with scanning tunneling microscopy

We have developped an experimental technique for writing stable features on an atomically flat gold (111) surface with Scanning Tunneling Microscope (STM). By applying voltage pulses (close to 3 V) across the tunneling junction in controlled atmosphere with the presence of water or ethanol vapour, nano-hole can be produced. The smallest hole formed is 3 nm in diameter and 0.24 nm in depth. This nano-hole represents the loss of about 100 Au atoms in the top atomic layer of gold surface, there is no atomic perturbation seen inside and outside the nano-hole. Different nanostructures (lattice of dots, legends, map, etc.) are fabricated. We report the dependence of the threshold voltage for the formation of a nano-hole on the relative humidity and the existence of a “critical humidity”. Different tips (Pt---Ir, Au, Au---Pd, Ag and W) are used, the relationship between the threshold voltage and the relative humidity is basically independent of the tip material. We approve that the mechanism involved in pit formation could be electrochemical in origin.     

A Direct PWM Technique for a Single-Phase Full-Bridge Inverter Through Controlled Capacitor Charging

The controlled-capacitor-charging (CCC) technique is utilized in this paper to synthesize a sinusoidal voltage at the output from the unregulated dc at the input. The method is based on the controlled charging/discharging of a capacitor to realize the desired voltage waveform. A capacitor that is connected across the load is charged/discharged through an inductor by applying high-frequency pulses. The applied pulses could be of either positive or negative polarity, depending on the error signal in the controller. The controller senses the output voltage and current and operates to maintain zero-current switching at every turn-on while keeping the output voltage close to the reference waveform by a tracking-control algorithm, enforcing limits in maximum switching frequency and voltage ripples. This paper presents a direct method of implementing the pulsewidth modulation for the single-phase full-bridge inverter, using the CCC technique. A simple procedure to design such an inverter is also discussed. The proposed controller is simulated in a personal computer simulation program with integrated circuit emphasis. Supporting results from an experimental prototype confirm the usefulness of the proposed controller. The inverter may be used in uninterruptible power supply and many other applications.      

Electrothermal behavior of the elements of SOS CMOS chips

Using two-dimensional (2D) numerical electrothermal simulation, the character of heating of SOS CMOS chip elements under the action of single voltage pulses was determined. The experiments carried out on SOS CMOS chips confirmed the validity of the developed numerical model of thin structure heating under the action of single voltage pulses. It was confirmed that the dependence of the pulse electric strength level on a single voltage pulses (SVP) length for SOS CMOS chips is weaker than that for CMOS chips fabricated using bulk or epitaxial technologies.     

基于粒子群算法的超宽带脉冲波形设计

首先分析了在超宽带系统中高斯脉冲成形因子和微分阶数对其能量谱密度的影响,并在此基础上,为了提高高斯脉冲波形的频谱利用率,采用高斯导函数线性组合来产生脉冲波形,提出并分析了一种基于粒子群（PSO）优化算法的超宽带无线脉冲波形优化设计方法,仿真表明该方法产生的高斯导函数线性组合脉冲能够很好地满足FCC的频谱掩模限制。