单片集成GaAs增强／耗尽型赝配高电子迁移率晶体管

介绍了单片集成GaAs增强／耗尽型赝配高电子迁移率晶体管（PHEMT）工艺。借助栅金属的热处理过程,形成了热稳定性良好的Pt／Ti／Pt／Au栅。AFM照片结果表明Pt金属膜表面非常平整,2nm厚度膜的粗糙度RMS仅为0．172nm。通过实验,我们还得出第一层Pt金属膜的厚度和退火后的下沉深度比大概为1：2。制作的增强型／耗尽型PHEMT的闽值电压（定义于1mA／mm）、最大跨导、最大饱和漏电流密度、电流增益截止频率分别是＋0．185／-1．22V、381．2／317．5mS／mm、275／480mA／mm、38／34GHz。增强型器件在4英寸圆片上的阈值电压标准差为19mV。     

N2O treatment enhancement-mode InAlN/GaN HEMTs with HfZrO2 High-k insulator

A normally-off InAlN/GaN MIS-HEMT with HfZrO₂ gate insulator was realized and investigated. By using N₂O plasma treatment beneath the gate region, 13 nm InAlN Schottky layer was oxidized to AlON_x + 4 nm InAlN Schottky layer. The strong polarization induced carriers in traditional InAlN/GaN 2 DEG quantum well was reduced for enhancement-mode operation. High-k thin film HfZrO₂ was used for gate insulator of E-mode device to further suppress gate leakage current and enhance device gate operation range. The maximum drain current of E-mode InAlN/GaN MIS-HEMT was 498 mA/mm and this value was higher than previous published InAlN/GaN E-mode devices. The measurement results of low-frequency noise also concluded that the low frequency noise is attributed to the mobility fluctuation of the channel and N₂O plasma treatment did not increase fluctuation center of gate electrode.     

Dual-Gate E/E- and E/D-Mode AlGaAs/InGaAs pHEMTs for Microwave Circuit Applications

In this paper, we developed dual-gate enhancement/enhancement-mode (E/E-mode) and enhancement/depletion-mode (E/D-mode) AlGaAs/InGaAs pHEMTs for high-voltage and high-power device applications. These dual-gate devices had a higher breakdown voltage (V_br) and maximum oscillation frequency (f_max). This could be obtained because there were two depletion regions, and the total electrical field was shared between the two regions, leading to lower output conductance (g_o) and lower gate-to-drain capacitance (C_gd). The dual-gate device can be operated at a higher drain-to-source voltage (V_ds), resulting in better linear gain and output power performance, as compared to a conventional single-gate E-mode GaAs pHEMT device. The maximum oscillation frequency obtained using the dual-gate E/E-mode device increased from 78 to 123 GHz. When operated at 2.4 GHz, the maximum RF output power of the single-gate E-mode and dual-gate E/D-mode devices increased from 636 to 810 mW/mm, respectively. We also produced a 2.4-GHz high-gain and high-power density two-stage power amplifier using dual-gate E/E and E/D-mode transistors. A linear gain of 40 dB and a maximum output power of 24 dBm were obtained.     

The study of δ-doped InGaP/InGaAs/GaAs pseudomorphic high electron mobility transistor

An enhancement-mode pseudomorphic high electron mobility transistor (E-mode pHEMT) with In_0.49Ga_0.51P/In_0.25Ga_0.75As/GaAs structure is studied in this paper. The two-dimensional device simulator, MEDICI, is used to solve the Poisson's equation and the electron/hole current continuity equations. An optimized δ-doped InGaP/InGaAs pHEMT structure is found to be superior to the conventional AlGaAs/InGaAs pHEMT. It reveals that the maximum drain-source current (I_DS) goes up to 1600 mA/mm and transconductance (G_m) is 2120 mS/mm.     

On the Pseudomorphic High Electron Mobility Transistors (PHEMTs) With a Low-Temperature Gate Approach

The characteristics of AlGaAs/InGaAs/GaAs depletion-mode (D-mode) and enhancement-mode (E-mode) pseudomorphic high electron mobility transistors (PHEMTs) fabricated using an electroless-plated (EP) deposition approach are investigated. Under the low-temperature and low-energy conditions, the EP deposition approach can form a better metal–semiconductor interface. For the studied devices, with a $hbox{1} times hbox{100} muhbox{m}^{2}$ gate dimension, excellent characteristics of the maximum drain saturation current (168.9 mA/mm) and extrinsic transconductance (225.8 mS/mm) are obtained for the D-mode device. The corresponding values for the E-mode device are 152.5 mA/mm and 211.7 mS/mm, respectively. Moreover, the EP approach also has the advantages of easy operation and low cost.      

Effect of the work function of gate electrode on hysteresis characteristics of organic thin-film transistors with Ta2O5/polymer as gate insulator

Organic thin-film transistors (OTFTs) using high dielectric constant material tantalum pentoxide (Ta₂O₅) and benzocyclobutenone (BCBO) derivatives as double-layer insulator were fabricated. Three metals with different work function, including Al (4.3 eV), Cr (4.5 eV) and Au (5.1 eV), were employed as gate electrodes to study the correlation between work function of gate metals and hysteresis characteristics of OTFTs. The devices with low work function metal Al or Cr as gate electrode exhibited high hysteresis (about 2.5 V threshold voltage shift). However, low hysteresis (about 0.7 V threshold voltage shift) OTFTs were attained based on high work function metal Au as gate electrode. The hysteresis characteristics were studied by the repetitive gate voltage sweep of OTFTs, and capacitance–voltage (C–V) and trap loss-voltage (G_p/ω?V) measurements of metal–insulator–semiconductor (MIS) devices. It is proved that the hysteresis characteristics of OTFTs are relative to the electron injection from gate metal to Ta₂O₅ insulator. The electron barrier height between gate metal and Ta₂O₅ is enhanced by using Au as gate electrode, and then the electron injection from gate metal to Ta₂O₅ is reduced. Finally, low hysteresis OTFTs were fabricated using Au as gate electrode.     

Analysis of nanometer-scale InGaAs/InAs/InGaAs composite channel MOSFETs using high-K dielectrics for high speed applications

The outstanding electron transport properties of InGaAs and InAs semiconductor materials, makes them attractive candidates for future nano-scale CMOS. In this paper, the ON state and OFF state performance of 30 nm gate length InGaAs/InAs/InGaAs buried composite channel MOSFETs using various high-K dielectric materials is analyzed using Synopsys TCAD tool. The device features a composite channel to enhance the mobility, an InP spacer layer to minimize the defect density and a heavily doped multilayer cap. The simulation results show that MOSFETs with Al₂O₃/ZrO₂ bilayer gate oxide exhibits higher gm/I_D ratio and lower sub threshold swing than with the other dielectric materials. The measured values of threshold voltage (V_T), on resistance (R_ON) and DIBL for Lg = 30 nm In_0.53Ga_0.47As/InAs/In_0.53Ga_0.47As composite channel MOSFET having Al₂O₃/ZrO₂ (EOT = 1.2 nm) bilayer dielectric as gate oxide are 0.17 V, 290 Ω-µm, and 65 mV/V respectively. The device displays a transconductance of 2 mS/µm.     

Fast,simple ZnO/organic CMOS integrated circuits

Hybrid organic–inorganic CMOS thin-film circuits are a simple, potentially low-cost, approach for large-area, low-power microelectronic applications. We have used atmospheric pressure processes to deposit inorganic ZnO and organic diF TES-ADT semiconductor layers and an Al₂O₃ gate dielectric. The organic semiconductor uses a contact-treatment-related microstructure that allows circuits to operate without directly patterning the organic layer. Using a simple 4-mask process with bifunctional Ti/Au contacts for both ZnO and organic transistors, 7-stage ring oscillators were fabricated and operated at >500 kHz corresponding to a propagation delay of <150 ns/stage at a supply bias of 35 V. These are the fastest organic–inorganic CMOS circuits reported to date.     

Tuning nonlinear susceptibility in strained AlGaAs/InGaAs quantum cascade lasers

This paper explores enhancement of nonlinear susceptibility in strained quantum cascade lasers (QCLs) that lead to unique intracavity characteristics that include frequency mixing producing both fundamental and higher order modes that propagate freely within a GaAs matrix. Doing so provides a QCL cavity design with emission near the 3.5 μm range, a region suitable for applications within the 3–5 μm atmospheric transmission window. In this study, a self-consistent Schrodinger–Poisson solver was employed to analyze the effects of strain within an AlGaAs/InGaAs active region between AlGaAs/GaAs injectors on a [1 1 1] GaAs matrix for the purpose of enhancing nonlinear susceptibility. Strain relief available through the use of [1 1 1] GaAs allows increased indium composition in the active region and results in observation of second-harmonics below the 5 μm range with tunable optical dipole moments and oscillator strengths. Results demonstrate the feasibility of strained AlGaAs/InGaAs devices on GaAs for producing higher order harmonics that lay below the 4 μm spectral limit.     

Metalorganic vapor phase epitaxy growth and properties of GaAs/AlGaAs and InGaAs/GaAs quantum well structures on (111)A GaAs substrates

We review the recent advances in the fabrication and properties of GaAs/AlGaAs and InGaAs/GaAs quantum well (QW) structures grown on (111)A GaAs substrates by atmospheric pressure metalorganic vapor phase epitaxy (MOVPE). We show that a 25-period GaAs/AlGaAs multi-QW (MQW) structure was fabricated with good crystal quality, high photoluminescence (PL) emission intensity and monolayer (ML) interfacial roughness. A PL full width at half maximum (FWHM) of 10.5 meV was achieved for a 25-period MQW with a well width of 44 Å. This is the narrowest linewidth reported to date for any similar structures grown on (111)A or B substrates by any growth technique. We also report the properties of an InGaAs/GaAs single quantum well structure grown on (111)A GaAs. For this structure, the PL FWHM value was 9.1 meV, corresponding to a 1 ML interfacial roughness for a well width of 41 Å. This is the first demonstration of an InGaAs/GaAs quantum well structure grown on (111)A or (111)B GaAs by MOVPE.     

Memory effects in hybrid silicon-metallic nanoparticle-organic thin film structures

We report on the electrical behaviour of metal–insulator–semiconductor (MIS) structures fabricated on silicon substrates and using organic thin films as the dielectric layers. These insulating thin films were produced by different methods, including spin-coating (polymethylmethacrylate), thermal evaporation (pentacene) and Langmuir–Blodgett deposition (cadmium arachidate). Gold nanoparticles, deposited at room temperature by chemical self-assembly, were used as charge storage elements. In all cases, the MIS devices containing the nanoparticles exhibited hysteresis in their capacitance versus voltage characteristics, with a memory window depending on the range of the voltage sweep. This hysteresis was attributed to the charging and discharging of the nanoparticles from the gate electrode. A maximum memory window of 2.5 V was achieved by scanning the applied voltage of an Al/pentacene/Au nanoparticle/SiO₂/p-Si structure between 9 and −9 V.     

Photo-patternable polyimide gate insulator with fluorine groups for improving performance of 2,7-didecyl[1]benzothieno[3,2-b][1]benzothiopene (C10-BTBT) thin-film transistors

Surface properties of gate insulators strongly affect the device performance of organic thin-film transistors (OTFTs). To improve the performance of OTFTs, we have developed photo-sensitive polyimide gate insulator with fluorine groups. The polyimide gate insulator film could be easily patterned by selective UV exposure without any photoinitiator. The polyimide gate insulator film, fabricated at 130 °C, has a dielectric constant of 2.8 at 10 kHz, and leakage current density of <1.6 × 10^?10 A/cm² while biased from 0 to 90 V. To investigate the potential of the polyimide with fluorine groups as a gate insulator, we fabricated C₁₀-BTBT TFTs. The field-effect mobility and the on/off current ratio of the TFTs were measured to be 0.76 ± 0.09 cm²/V s and >10⁶, respectively.     

Investigation of TiO2 on AlGaAs prepared by liquid phase deposition and its application

The study explored titanium dioxide (TiO₂) on aluminum gallium arsenide (AlGaAs) prepared by liquid phase deposition (LPD) at 40 °C. The leakage current density was about 8.4 × 10^?6 A/cm² at 1 MV/cm. The interface trap density (D_it) and the flat-band voltage shift (ΔV_FB) were 2.3 × 10¹² cm^?2 eV^?1 and 1.2 V, respectively. After rapid thermal annealing (RTA) in the ambient N₂ at 350 °C for 1 min, the leakage current density, D_it, and ΔV_FB were improved to 2.4 × 10^?6 A/cm² at 1 MV/cm, 7.3 × 10¹¹ cm^?2 eV^?1, and 1.0 V, respectively. Finally, the study demonstrates the application to the AlGaAs/InGaAs metal–oxide–semiconductor pseudomorphic high-electron-mobility transistor (MOS-PHEMT). The results indicate the potential of the proposed device with a LPD-TiO₂ gate oxide for power application.     

IGZO thin film transistors with Al2O3 gate insulators fabricated at different temperatures

Thin film transistors (TFTs) with bottom gate and staggered electrodes using atomic layer deposited Al₂O₃ as gate insulator and radio frequency sputtered In–Ga–Zn Oxide (IGZO) as channel layer are fabricated in this work. The performances of IGZO TFTs with different deposition temperature of Al₂O₃ are investigated and compared. The experiment results show that the Al₂O₃ deposition temperature play an important role in the field effect mobility, I_on/I_off ratio, sub-threshold swing and bias stability of the devices. The TFT with a 250 °C Al₂O₃ gate insulator shows the best performance; specifically, field effect mobility of 6.3 cm²/Vs, threshold voltage of 5.1 V, I_on/I_off ratio of 4×10⁷, and sub-threshold swing of 0.56 V/dec. The 250 °C Al₂O₃ insulator based device also shows a substantially smaller threshold voltage shift of 1.5 V after a 10 V gate voltage is stressed for 1 h, while the value for the 200, 300 and 350 °C Al₂O₃ insulator based devices are 2.3, 2.6, and 1.64 V, respectively.     

Hall and photoluminescence studies of effects of the thickness of an additional In0.3Ga0.7As layer in the center of In0.15Ga0.85As/Al0.25Ga0.75As/GaAs high electron mobility transistors

In order to reduce the noise and carrier–donor scattering and thereby increase the carrier mobility of the pseudomorphic AlGaAs/InGaAs high electron mobility transistors (pHEMTs), we have grown Al_0.25Ga_0.75As/In_0.15Ga_0.85As/In_0.3Ga_0.7As/GaAs pHEMTs with varied In_0.3Ga_0.7As thickness, and studied the effects of the In_0.3Ga_0.7As thickness on the electron mobility and sheet density by Hall measurements and photoluminescence measurements. We calculated the electron and hole subbands and obtained good agreement between calculated and measured PL energies. It was found that the additional In_0.3Ga_0.7As layer could be used to reduce the carrier–donor scattering, but due to the increased interface roughness as the In_0.3Ga_0.7As layer becomes thicker, the interface scattering reduced the electron mobility. An optimal thickness of the In_0.3Ga_0.7As was found to be 2 nm.     

Fabrication of the flexible pentacene thin-film transistors on 304 and 430 stainless steel (SS) substrate

Flexible organic thin-film transistors (OTFT) were fabricated on 304 and 430 stainless steel (SS) substrate with aluminum oxide as a gate insulator and pentacene as an organic semiconductor. Chemical mechanical polishing (CMP) process was used to study the effect of the SS roughens on the dielectric properties of the gate insulator and OTFT characteristics. The surface roughness was decreased from 33.8 nm for 304 SS and 19.5 nm for 430 SS down to ～2.5 nm. The leakage current of the metal–insulator–metal (MIM) structure (Au/Al₂O₃/SS) was reduced with polishing. Mobility and on/off ratio of pentacene TFT with bare SS showed a wide range of values between 0.005 and 0.36 cm²/Vs and between 10³ and 10⁵ depending on the location in the substrate. Pentacene TFTs on polished SS showed an improved performance with a mobility of 0.24–0.42 cm²/Vs regardless of the location in the substrate and on/off ratio of ～10⁵. With self assembled monolayer formation of octadecyltrichlorosilane (OTS) on insulator surface, mobility and on/off ratio of pentacene TFT on polished SS was improved up to 0.85cm²/Vs and ～10⁶. I–V characteristics of pentacene TFT with OTS treated Al₂O₃/304 SS was also obtained in the bent state with a bending diameter (D) of 24, 45 or 70 mm and it was confirmed that the device performed well both in the linear regime and the saturation regime.     

Nonvolatile memory performance improvements for solution-processed thin-film transistors with composition-modified In–Zn–Ti–O active channel and ferroelectric copolymer gate insulator

The nonvolatile memory thin-film transistors (M-TFTs) using a solution-processed indium-zinc-titanium oxide (IZTiO) active channel and a poly(vinylidene fluoride-trifluoroethylene) ferroelectric gate insulator were fabricated and characterized to elucidate the relationships between the IZTiO channel composition and the memory performances such as program speed and data retention. The compositions of the spin-coated IZTiO layers were modified with different Ti amounts of 0, 2, 5, and 10 mol%. The carrier concentration of IZTiO channel layer was effectively modulated by the incorporated Ti amounts and the defect densities within the channel were effectively reduced by Ti incorporation. The M-TFT fabricated with IZTiO channel with 2-mol% Ti composition exhibited the best overall device performances, in which the μ_FE, SS, MW, and programmed I_on/off were obtained to be 23.6 cm² V^?1 s^?1, 701 mV/decade, 11.8 V, and 1.2 × 10⁵, respectively. Furthermore, thanks to the suitable amounts of Ti incorporation into the IZO, the improved program speed and data retention properties were successfully confirmed.     

Capacitance–conductance–current–voltage characteristics of atomic layer deposited Au/Ti/Al2O3/n-GaAs MIS structures

We have studied the admittance and current–voltage characteristics of the Au/Ti/Al₂O₃/n-GaAs structure. The Al₂O₃ layer of about 5 nm was formed on the n-GaAs by atomic layer deposition. The barrier height (BH) and ideality factor values of 1.18 eV and 2.45 were obtained from the forward-bias ln I vs V plot at 300 K. The BH value of 1.18 eV is larger than the values reported for conventional Ti/n-GaAs or Au/Ti/n-GaAs diodes. The barrier modification is very important in metal semiconductor devices. The use of an increased barrier diode as the gate can provide an adequate barrier height for FET operation while the decreased barrier diodes also show promise as small signal zero-bias rectifiers and microwave. The experimental capacitance and conductance characteristics were corrected by taking into account the device series resistance R_s. It has been seen that the non-correction characteristics cause a serious error in the extraction of the interfacial properties. Furthermore, the device behaved more capacitive at the reverse bias voltage range rather than the forward bias voltage range because the phase angle in the reverse bias has remained unchanged as 90° independent of the measurement frequency.     

蓝宝石衬底上槽栅型X波段增强型AlGaN/GaN HEMT

研制了一款X波段增强型AlGaN/GaN高电子迁移率晶体管(HEMT)。在3英寸(1英寸=2.54 cm)蓝宝石衬底上采用低损伤栅凹槽刻蚀技术制备了栅长为0.3μm的增强型AlGaN/GaN HEMT。所制备的增强型器件的阈值电压为0.42 V,最大跨导为401 mS/mm,导通电阻为2.7Ω·mm。器件的电流增益截止频率和最高振荡频率分别为36.1和65.2 GHz。在10 GHz下进行微波测试,增强型AlGaN/GaN HEMT的最大输出功率密度达到5.76 W/mm,最大功率附加效率为49.1%。在同一材料上制备的耗尽型器件最大输出功率密度和最大功率附加效率分别为6.16 W/mm和50.2%。增强型器件的射频特性可与在同一晶圆上制备的耗尽型器件相比拟。     

Structural and electrical characteristics of lanthanum oxide gate dielectric film on GaAs pHEMT technology

This paper investigates the feasibility of using a lanthanum oxide thin film (La_2O_3) with a high dielectric constant as a gate dielectric on GaAs pHEMTs to reduce gate leakage current and improve the gate to drain breakdown voltage relative to the conventional GaAs pHEMT. An E/D mode pHEMT in a single chip was realized by selecting the appropriate La_2O_3 thickness. The thin La_2O_3 film was characterized: its chemical composition and crystalline structure were determined by X-ray photoelectron spectroscopy and X-ray diffraction, respectively.La_2O_3 exhibited good thermal stability after post-deposition annealing at 200, 400 and 600 ℃ because of its high binding-energy (835.6 eV). Experimental results clearly demonstrated that the La_2O_3 thin film was thermally stable.The DC and RF characteristics of Pt/La_2O_3/Ti/Au gate and conventional Pt/Ti/Au gate pHEMTs were examined.The measurements indicated that the transistor with the Pt/La_2O_3/Ti/Au gate had a higher breakdown voltage and lower gate leakage current. Accordingly, the La_2O_3 thin film is a potential high-k material for use as a gate dielectric to improve electrical performance and the thermal effect in high-power applications.