Design and performance analysis of double-gate MOSFET over single-gate MOSFET for RF switch

In this paper, we have designed a double-gate MOSFET and compared its performance parameters with the single-gate MOSFET as RF CMOS switch, particularly the double-pole four-throw (DP4T) switch, for the wireless telecommunication systems. A double-gate radio-frequency complementary metal-oxide-semiconductor (DG RF CMOS) switch operating at the frequency of microwave range is investigated. This RF switch is capable to select the data streams from antennas for both the transmitting and receiving processes. We emphasize on the basics of the circuit elements (such as drain current, threshold voltage, resonant frequency, resistances at switch ON condition, capacitances, and switching speed) required for the integrated circuit of the radio frequency sub-system of the DG RF CMOS switch and the role of these basic circuit elements are also discussed. These properties presented in the switches due to the double-gate MOSFET and single-gate MOSFET have been discussed.     

An analytical drain current model for dual material engineered cylindrical/surrounded gate MOSFET

In this paper, a drain current model incorporating drain-induced barrier lowering (DIBL) has been developed for Dual Material gate Cylindrical/Surrounding gate MOSFET (DMG CGT/SGT MOSFET) and the expressions for transconductance and drain conductance have been obtained. It is shown that DMG design leads to drain current enhancement and reduced output conductance. The effectiveness of DMG design was scrutinized by comparing with single metal gate (SMG) CGT/SGT MOSFET. Moreover, the effect of technology parameters variations workfunction difference has also been presented in terms of gate bias, drain bias, transconductance and drain conductance. Results reveal that the DMG SGT/CGT devices offer superior characteristics as compared to single material gate CGT/SGT devices. A good agreement between modeled and simulated results has also been obtained thus providing the validity of proposed model.     

A non-local impact ionization/lattice temperature model for VLSIdouble-gate ultrathin SOI NMOS devices

This paper presents an analytical drain current model for VLSI double-gate ultrathin SOI NMOS devices considering both the nonlocal impact ionization effect and the lattice temperature effect. Supported by the experimental data, the analytical model predicts that the double-gate SOI NMOS device has a more obvious nonlocal impact ionization effect and a higher lattice thermal effect as compared to the single-gate device     

甚低频固态发射机功率器件分析

甚低频发射机用来给潜艇发信,功率达数百千瓦至数千千瓦,如今可以采用MOSFET和IGBT等固态器件作为大功率开关放大器,但选择MOSFET还是IGBT,设计人员需要做出选择。分析了这两类器件的开关特性及导通特性,比较了它们的工作特点,介绍了一种典型的大功率开关放大器应用电路,讨论了甚低频发射机在选择大功率放大器器件时应考虑的一些条件,如频率、电压、开关时间等。     

Reduction of off-current in self-aligned double-gate TFT with mask-free symmetric LDD

In this work, the lateral electric field distribution in the channel of a double-gate TFT is studied and compared with that of a conventional single-gate TFT. The double-gate TFT is predicted to suffer from a more severe anomalous off-current than the single-gate TFT. A smart double-gate TFT technology is proposed to decrease the off-current. The unique feature of the technology is the lithography independent formation of the self-aligned double-gate and the symmetric lightly doped drain (LDD) structures. With the LDD applied, the anomalous off-current of the fabricated double-gate TFT is reduced by three orders of magnitude from the range of 10/sup -9/ A//spl mu/m to 10/sup -12/ A//spl mu/m. The on/off current ratio is increased by three orders of magnitude accordingly from around 10/sup 4/ to 10/sup 7/.     

双栅双应变沟道全耗尽SOI CMOS的瞬态特性分析

在提出双栅双应变沟道全耗尽SOl MOSFET新结构的基础上,模拟了沟道长度为25nm时基于新结构的CMOS瞬态特性.结果表明,单栅工作模式下,传统应变SiGe(或应变Si)器件的CMOS电路只能实现上升(或下降)时间的改善,而基于新结构的CMOS电路能同时实现上升和下降时间的缩短;双栅模式下,CMOS电路的上升和下降时间较单栅模式有了更进一步的改善,电路性能得以显著提高.     

Self-aligned vertical double-gate MOSFET (VDGM) with the oblique rotating ion implantation (ORI) method

A process of making a symmetrical self-aligned n-type vertical double-gate MOSFET (n-VDGM) over a silicon pillar is revealed. This process utilizes the technique of oblique rotating ion implantation (ORI). The self-aligned region forms a sharp vertical channel profile and decreases the channel length L_g. A tremendous improvement in the drive-on current is noted. The electron concentration profile obtained demonstrates an increased number of electrons in the channel injected from the source end as the drain voltage increases. The enhanced carrier concentration results in significant reduction in the off-state leakage current and improves the drain-induced barrier-lowering (DIBL) effect. These simulated characteristics when compared to those in a fabricated device without the ORI method show the distinct advantage of the technique reported for suppression of short-channel effects (SCE) in nanoscale vertical MOSFET.     

基于固体开关器件的“过”驱动技术研究

为了提高功率MOSFET的开关速度,从功率MOSFET的开关机理加以分析,通过用仿真与电路实验相结合的方法,研究出了功率MOSFET栅极的“过”驱动技术,大大加快了功率MOSFET的开关速度。     

Implementation and characterization of the double-gate MOSFET using lateral solid-phase epitaxy

In this paper, a simple high performance double-gate metal oxide semiconductor field effect transistor (MOSFET) using lateral solid-phase epitaxy (LSPE) is experimentally demonstrated and characterized. The thin channel of the double-gate MOSFET was obtained using the high quality LSPE crystallized layer. The fabricated double-gate MOSFET provides good current drive capability and steep subthreshold slope, and they are approximately 350 /spl mu/A//spl mu/m (@ V/sub ds/ = 2.5 V and V/sub gs/ - V/sub T/ = 2.5 V) and 78 mV/dec for the devices with 0.5 /spl mu/m channel length. Compared to the conventional single-gate transistor, the double-gate NMOSFET fabricated on the LSPE layer has better V/sub T/ roll-off characteristics, DIBL effect, and 1.72 times higher current drive. The peak effective electron mobility of the LSPE crystallized layer is approximately 382 cm/sup -2//V.s.     

MOSFET器件并联实验研究

采用图腾柱的驱动方式,设计了应用于IXYS公司的功率MOSFET器件DE375-102N12的驱动电路。单个开关在多脉冲下具有良好的脉冲一致性。以该功率MOSFET器件进行的6个并联实验说明,影响并联的MOSFET的动态均流的主要参数是放电回路中的回路电感和寄生电感,电路板的布局与布线对并联的功率MOSFET有很大的影响,良好的布局可以大大提高电路的性能。     

基于GaAs STATZ模型的RF MOSFET DC建模技术

STATZ模型是表征GaAsMESFET特性的常用模型,具有表达式简洁、参数少的优点。通过尝试将STATZ模型用于表征射频MOSFET的直流特性,提取并在ADS软件中优化了STATZ直流模型的参数。为了提高仿真精度,模型必须考虑晶体管漏极与源极的寄生电阻,根据MOSFET处于强反型区且漏-源电压为零时的等效电路模型提取了晶体管的漏极和源极的寄生电阻。在ADS软件中利用STATZ模型对MOSFET的直流特性进行了仿真,测量的MOSFET直流曲线与仿真曲线一致性很好,验证了模型的良好的精确度,证明了GaAs STATZ模型可以用于表征射频MOSFET的直流特性。晶体管采用中芯国际的0.13μm RF CMOS工艺制作。     

A physical compact model of DG MOSFET for mixed-signal circuit applications - part II: Parameter extraction

For pt. see ibid., vol. 50, no. 10, p. 2135 (2003). Based on the physical double-gate MOSFET model described in Part I, we present a systematic parameter extraction methodology that avoids parameter interdependence between different physical effects whenever possible. Several extraction schemes are compared for precise modeling of small-signal and large-signal characteristics. The physical model and the extraction methodology are verified through the reproduction of the simulated drain current, incremental drain resistance, and transconductance per unit current, which are parameters of particular interest to mixed-signal circuit designs.     

MOSFET管并联应用时电流分配不均问题探究

并联应用时MOSFET管会产生电流分配不匀的现象,为减小此问题造成的不良影响,只能通过实验确定有关的电路参数。这里用数学方法详细分析MOSFET管的特性参数和电路参数对静态和动态漏极电流分配不匀的影响,推导出反映漏极电流分配不匀程度和对漏极电流上升速度影响程度的精确计算公式,为在实际工作中减小电流分配不匀的影响提供理论依据。     

A novel double gate MOSFET by symmetrical insulator packets with improved short channel effects

In this article, we study a novel double-gate SOI MOSFET structure incorporating insulator packets (IPs) at the junction between channel and source/drain (S/D) ends. The proposed MOSFET has great strength in inhibiting short channel effects and OFF-state current that are the main problems compared with conventional one due to the significant suppressed penetrations of both the lateral electric field and the carrier diffusion from the S/D into the channel. Improvement of the hot electron reliability, the ON to OFF drain current ratio, drain-induced barrier lowering, gate-induced drain leakage and threshold voltage over conventional double-gate SOI MOSFETs, i.e. without IPs, is displayed with the simulation results. This study is believed to improve the CMOS device reliability and is suitable for the low-power very-large-scale integration circuits.     

功率MOSFET并联驱动特性分析

并联MOSFET非常适合于在低电压、大电流下工作.基于IRFS4227PBF功率MOSFET,分析和测试了在一定散热环境下MOSFET结温的收敛特性与漏极电流的关系,说明了MOSFET的实际电流容量受散热条件制约,并以此确定在额定电流下需要并联的个数.用PSPICE电路仿真论述了外围电路Q值和功率管参数等因素对并联驱动的动态均流特性的影响.在此基础上搭建实验平台,成功实现了8个MOSFET并联在高频状态下的稳定工作.     

A new empirical nonlinear model for sub-250 nm channel MOSFET

An empirical nonlinear model for sub-250 nm channel length MOSFET is presented which is useful for large signal RF circuit simulation. Our model is made of both analytical drain current and gate charge formulations. The drain current expression is continuous and infinitely derivable, and charge conservation is taken into account, as the capacitances derive from a single charge expression. The model's parameters are first extracted, prior the model's implementation into a circuit simulator. It is validated through dc, ac, and RF large signal measurements compared to the simulation.     

Continuous analyticⅠ-Ⅴmodel for GS DG MOSFETs including hot-carrier degradation effects

正We have studied the influence of hot-carrier degradation effects on the drain current of a gate-stack double-gate(GS DG) MOSFET device.Our analysis is carried out by using an accurate continuous current-voltage (Ⅰ-Ⅴ) model,derived based on both Poisson's and continuity equations without the need of charge-sheet approximation. The developed model offers the possibility to describe the entire range of different regions(subthreshold, linear and saturation) through a unique continuous expression.Therefore,the proposed approach can bring considerable enhancement at the level of multi-gate compact modeling including hot-carrier degradation effects.     

Continuous analytic I–V model for GS DG MOSFETs including hot-carrier degradation effects

We have studied the influence of hot-carrier degradation effects on the drain current of a gate-stack double-gate (GS DG) MOSFET device. Our analysis is carried out by using an accurate continuous current-voltage (I-V) model, derived based on both Poisson's and continuity equations without the need of charge-sheet approximation. The developed model offers the possibility to describe the entire range of different regions (subthreshold, linear and saturation) through a unique continuous expression. Therefore, the proposed approach can bring considerable enhancement at the level of multi-gate compact modeling including hot-carrier degradation effects.     

FinFET design considerations based on 3-D simulation and analytical modeling

Design considerations of the FinFET have been investigated by three-dimensional (3-D) simulation and analytical modeling in this paper. Short-channel effects (SCE) of the FinFET can be reasonably controlled by reducing either silicon fin height or fin thickness. Analytical solution of 3-D Laplace's equation is employed to establish the design equations for the subthreshold behavior in the fully depleted silicon fins. Based on the 3-D analytical electrostatic potential in the subthreshold region, the threshold voltage (V/sub th/) roll-off and the subthreshold swing (S) are estimated by considering the source barrier changes in the most leaky channel path. V/sub th/ roll-off is an exponential function of the ratio of effective channel length to drain potential decay length, which can then be expressed as a function of the fin thickness, the fin height and the gate oxide thickness. The drain-potential decay lengths of single-gate fully depleted SOI MOSFET (FDFET), double-gate MOSFET (DGFET), rectangular surrounding-gate MOSFET (SGFET), and FinFET are compared. The drain potential scaling length and V/sub th/ roll-off can be included into a universal relation for convenient comparison.     

SiC JFET与SiC MOSFET失效模型及其短路特性对比

建立了两种碳化硅（SiC）器件JFET和MOSFET的失效模型.失效模型是在传统的电路模型的基础上引入了额外附加的泄漏电流,其中,SiC JFET是在漏源极引入了泄漏电流,SiC MOSFET是在漏源极和栅极引入了泄漏电流;同时,为了体现温度和电场强度与失效的关系,用与温度和电场强度相关的沟道载流子迁移率代替了传统电路模型所采用的常数迁移率.有关文献的实验结果和半导体器件的计算机模拟（Technology Computer Aided Design,TCAD）验证了两种SiC器件失效模型的准确性.所建立的失效模型能够对比SiC JFET和SiC MOSFET的短路特性.