A quasi-analytical SET model for few electron circuit simulation

A novel quasi-analytical model for single electron transistors (SETS) is proposed and validated by comparison with Monte-Carlo (MC) simulations in terms of drain current and transconductance. The new approach is based on the separate modeling of the tunneling and thermal components of the drain current, and verified over two decades of temperature. The model parameters are physical and an associated parameter extraction procedure is also reported. The model is shown to be accurate for SET logic circuit simulation in both static and dynamic regimes and is attractive for hybrid (SET-CMOS) circuit co-simulation     

A bidirectional NMOSFET current reduction model for simulation ofhot-carrier-induced circuit degradation

An approach for modeling hot-electron induced change in drain current that significantly improves the ease of parameter extraction and provides new capabilities for modeling the effect of bidirectional stressing and the asymmetrical I-V characteristics after stressing is presented. The change in the drain current, ΔI_D is implemented as an asymmetrical voltage-controlled current source and the new ΔI_D model is independent of the MOSFET model used for circuit simulation. The physical basis of the model, the analytical model equations, the implementation scheme in BERT (BErkeley Reliability Tools) simulator and simulation results for uni- and bidirectional circuit stressing are presented     

基于表面势的多晶硅晶体管漏电流物理模型

提出了一种基于薄层电荷模型、陷阱态密度和表面势的多晶硅薄膜晶体管漏电流物理模型。模型采用非迭代的运算方法, 简单且适用于所有大于平带电压的工作区域。 考虑了包括高斯分布的深能态和指数分布的带尾态在内的陷阱分布形式, 陷阱分布参数的提取通过光电子调制谱方法实现。通过模型与现有实验结果的比较, 得到一致的符合结果。     

Extraction technique for characterization of electric field distribution and drain current in VDMOS power transistor

This paper presents a methodology for modeling the electric field distribution in the vertical direction of VDMOS power transistors, considering the effects of cell spacing and drain voltage. An accurate and consistent extraction technique is developed to extract the values of various important parameters based on non-linear and multivariable regression techniques for the first time. The generalized form of electric field distribution enables the physical modeling of drain current at the onset of quasi-saturation considering the effect of non-uniform electron distribution in the n-epi region. Results so obtained are in good agreement with PISCES simulation over wide range of device parameters. The proposed model will be highly suitable for CAD (Computer Aided Design) tools in HVIC applications.     

MOSFET和Poly-Si TFTs参数提取策略的研究

随着半导体制造技术的不断改善和工艺的不断升级,精确的模型参数对于代工厂和设计者尤为重要.而参数提取策略的选择是整个参数提取过程中的关键步骤.该研究以伯克利大学开发的SPICE Level-3 MOSFET和多晶硅薄膜晶体管模型为研究对象,以包括了短沟效应、窄沟效应、漏致势垒降低效应的MOSFET阈值电压方程和多晶硅薄膜晶体管统一漏电流方程作为研究出发点,然后分别讨论了模型中几个主要参数的提取方法,最后给出了参数提取的流程图.     

基于自动微分技术的器件模型参数提取算法

自动微分 (AD)技术以非标准分析为理论基础 ,是计算机数值计算领域中的一种很有前途的方法。文中提出了基于 AD技术的器件模型参数提取算法 ,在 Visual C+ +平台编制了模型参数提取程序 ,对所建立的基于表面势的 MOSFET模型进行了有约束条件的参数提取。结果表明 ,算法收敛快、稳定性好、提取准确     

Physical modeling of the power VDMOST for computer-aided design ofintegrated circuit

This paper presents a methodology for physical modeling of the vertical double-diffused MOS transistor (VDMOST) for power-integrated-circuit (PIC) design. The circuit model comprises the regional models derived from basic semiconductor equations. The unique features of the VDMOST such as quasi-saturation, nonlinear inter-electrode capacitances, reverse-recovery current, and temperature dependencies are accurately modeled based on device simulations. The composite model is implemented in Saber and SPICE2G.6 source code. It is verified against steady-state and capacitance-voltage measurements on test devices. A parameter extraction routine is developed, and a system that links ICCAP and Saber is set up that performs measurement, simulation, and parameter extraction. The application of the described model in computer-aided design (CAD) is demonstrated for several power-electronic circuits     

A methodology to extract the channel current of permeable gate oxide MOSFETs

A methodology to extract the channel current of MOS transistors in the presence of high gate leakage current is presented. The methodology is based on the partitioning of the gate current among the source and drain terminals and it is well suited for devices featuring ultrathin gate oxide and long channels, as those typically employed for mobility measurements. The proposed procedure is compared with the existing method based on a 50%-50% source/drain partition of the gate current, and the dependence of the extraction error associated with these two methods on channel length and bias conditions is studied in detail. It is found that the extraction error is weakly dependent on gate-source and drain-source voltages.     

Unified electrical model for the contact regions of staggered Thin Film Transistors

In this work, we propose an unified compact model, which includes the effects of both source and drain contact regions, to describe the electrical characteristics of staggered thin film transistors (TFTs). The model is based on a generic drift analytical expression that describes the intrinsic channel of the transistor. Despite the distributed two-dimensional nature of the contacts in staggered configurations, two-terminal components are usually preferred to model the source and drain contact regions. In this regard, a model based on versatile simple expressions that describe the current–voltage relations of both contact regions are proposed in this work. These expressions are based on the physics underlying a metal–organic-metal structure. They can be adapted to different transport conditions, such as Ohmic, space-charge-limited transport or Schottky-like contacts. This adaptation is controlled with the value of a single parameter that modifies the concavity or convexity of these expressions. The model works together with an evolutionary parameter extraction procedure, presented in a previous work for TFTs with negligible drain contact effects, and adapted here to this proposed model for staggered transistors. The results of the model and the evolutionary procedure have been validated with published experimental data of different TFTs, mostly organic thin film transistors (OTFTs). The model and evolutionary procedure agrees with other procedures tested successfully in the literature which were defined to cope with specific kinds of contacts in the TFTs. In this regard, our model and evolutionary parameter extraction procedure unify these previous procedures.     

Analysis of floating body induced transient behaviors in partiallydepleted thin film SOI devices

Emphasis toward manufacturability of thin film SOI devices has prompted more attention on partially depleted devices. In this paper, drain current transients in partially depleted SOI devices due to floating-body effects are investigated quantitatively. A one-dimensional analytical model is developed to predict the transient effect and MEDICI simulation is performed to confirm the model. With the model, the amount of the turn-on current enhancement and the turn-off current suppression are calculated. The transient characteristics can be used in investigating the quality of the SOI materials by determining the carrier lifetime. The impact of the transient effect on the device parameter extraction is described     

A theoretical model for the current-voltage characteristics of afloating-gate EEPROM cell

A model for current-voltage characteristics of an EEPROM cell has been developed and used in the simulation of an EEPROM test structure. It provides an explanation for the observed strong drain-induced barrier lowering effect and the role of trapped charge in the floating gate. In this model, the surface potential is related to the terminal voltages through an equivalent electrical circuit. Charge sheet and depletion approximation are used to describe the charge distribution in the semiconductor. Gradual approximation is assumed in deriving the drain current equation. A simplified drain current equation under a strong inversion condition is derived. An expression defining the extrapolated threshold voltage is obtained. It is useful in parameter extraction. A new method for extracting the drain coupling ratio and the channel coupling ratio is proposed. Finally, it is shown that extrapolated threshold voltage is a convenient quantity for classifying the threshold voltage of an EEPROM cell     

A new empirical large-signal model for enhancement-mode AlGaAs/InGaAs pHEMTs

We propose a new large-signal model for AlGaAs/InGaAs pHEMTs, which can simulate the device microwave output power, non-linear characteristics at arbitrary bias points. This model includes a new drain current equation, which is extracted from its derivatives. In addition, gate-to-source and gate-to-drain capacitances are also characterized versus the function of gate and drain biases. The parameter extraction procedure is addressed for the enhancement-mode pHEMTs, which offers an attractive solution for handset power amplifier application because of its positive bias characteristics. Finally, measured and model-predicted dc I–V, S-parameters, and power performance have been compared.     

Characterization and modeling of hot carrier injection in LDMOS for L-band radar application

This paper reports a methodology to correlate Hot Carrier Injection (HCI) degradation mechanism and electrical figures of merit on Lateral-Diffused Metal-Oxide-Semiconductor (LDMOS) transistor. This method is based on RF life test in radar operating conditions coupled to a high drain voltage in order to make visible HCI degradation. We propose drain current modeling vs. time based on a simple extraction procedure. The electron density trapped in the oxide is extracted from hot carrier induced series resistance enhancement model (HISREM - i.e. ΔR_d model). From this methodology, the degradation of RF-LDMOS due to HCI is quantified and could be simulated with EDA.     

A unified look at the use of successive differentiation and integration in MOSFET model parameter extraction

This article provides a unified look at MOSFET model parameter extraction methods that rely on the application of successive differential and integral operators, their ratios, and various other combinations thereof. Some of the most representative extraction procedures are assessed by comparatively examining their ability to extract basic model parameters from synthetic MOSFET transfer characteristics, generated by an ad hoc minimalist four-parameter model. The model used, comprised of a single polylogarithm function of gate voltage, approximately describes in a very concise manner the essential features of MOSFET drain current continuously from depletion to strong inversion. The exponential-like low voltage and monomial-like high voltage asymptotes of this simple model are conveniently used to analyze and compare the different extraction schemes that are founded on successive differentiation or integration. In addition to providing a combined view useful for comparative methodological appraisal, the present unified analysis facilitates visualizing and exploring other potentially promising extraction strategies beyond the straightforward use of successive differential and integral operators and their ratios. We include examples of parameter extraction from measured transfer characteristics of real experimental MOSFETs to comparatively illustrate the actual numerical implementation of typical successive differential and integral operator-based procedures.     

On the transient response of organic electrochemical transistors

We present a universal model for the transient drain current response in organic electrochemical transistors (OECTs). Using equivalent circuits and charge injection physics, we are able to predict the drain current in OECT devices upon application of a gate voltage input. The model is applicable to both plain and membrane-functionalized devices, and allows us to extract useful physical quantities such as resistances and capacitances, which are related to functional properties of the system. We are also able to use the model to reconstruct the magnitude and shape in time of an applied voltage source based on the observed drain current response. This was experimentally demonstrated for drain current measurements under an applied action potential.     

一种用于非线性分析的新型4H-SiC MESFET大信号经验模型

提出了一种简洁的新型4H-SiCMESFET经验大信号模型.在Materka漏电流模型基础上,改进了沟道调制因子和饱和电压系数的建模方式,电容模型采用了改进的电荷守恒模型.参数的提取和优化采用了Levenberg-Marquardt优化方法.在偏置点VDS=20V,IDS=80mA和工作频率1.8GHz下,模型直流电流-电压扫描曲线、输出功率、功率附加效率和增益的模拟结果与实验数据符合良好.     

一种用于非线性分析的新型4H-SiC MESFET大信号经验模型

提出了一种简洁的新型4H-SiCMESFET经验大信号模型.在Materka漏电流模型基础上,改进了沟道调制因子和饱和电压系数的建模方式,电容模型采用了改进的电荷守恒模型.参数的提取和优化采用了Levenberg-Marquardt优化方法.在偏置点VDS=20V,IDS=80mA和工作频率1.8GHz下,模型直流电流-电压扫描曲线、输出功率、功率附加效率和增益的模拟结果与实验数据符合良好.     

Accounting for quantum effects and polysilicon depletion from weak to strong inversion in a charge-based design-oriented MOSFET model

This paper presents a simple, physics-based, and continuous model for the quantum effects and polydepletion in deep-submicrometer MOSFETs with very thin gate oxide thicknesses. This analytical design-oriented MOSFET model correctly predicts inversion and depletion charges, transcapacitances, and drain current, from weak to strong inversion and from nonsaturation to saturation. One single additional parameter is used for polysilicon doping concentration, while the quantum correction does not introduce any new parameter. Comparison to experimental data of deep-submicrometer technologies is provided, showing accurate fits both for I-V and C-V data. The model offers simple relationships among effective electrical parameters and physical device parameters, providing insight into the physical phenomena. This new model thereby supports device engineering, analog circuit design practice, as well as efficient circuit simulation.     

A new approach to determine the drain-and-source series resistanceof LDD MOSFET's

A method for determining the intrinsic drain-and-source series resistance and the effective channel length of LDD MOSFET's is proposed. The method is based on the experimentally measured device I-V characteristics and a new parameter extraction procedure. A consistent set of the effective channel length and the gate-voltage-dependent drain-and-source series resistance was thus determined. The comparison between the measured and experimental drain current characteristics shows excellent agreement using the present model values