一种全集成CMOS数字电视调谐器射频前端

设计了一种全集成CMOS数字电视调谐器(DTV tuner)射频前端电路.该电路采用二次变频低中频结构,集成了低噪声放大器、上变频混频器、下变频混频器等模块.芯片采用0.18μm CMOS工艺实现,测试结果表明,在50～860MHz频率范围内,射频前端能够实现很好的输入阻抗匹配,并且总的增益变化范围达到20dB.其中,在最大增益模式下,电压增益为 33dB,单边带噪声系数(SSB NF)为9.6dB,输入参考三阶交调点(ⅡP3)为-11Bm;在最小增益模式下,电压增益为 14dB,单边带噪声系数为28dB,输入参考三阶交调点为 8dBm.射频前端电路面积为1.04mm×0.98mm,工作电压为1.8V,消耗电流为30mA.     

一种全集成CMOS数字电视调谐器射频前端

设计了一种全集成CMOS数字电视调谐器(DTV tuner)射频前端电路.该电路采用二次变频低中频结构,集成了低噪声放大器、上变频混频器、下变频混频器等模块.芯片采用0.18μm CMOS工艺实现,测试结果表明,在50～860MHz频率范围内,射频前端能够实现很好的输入阻抗匹配,并且总的增益变化范围达到20dB.其中,在最大增益模式下,电压增益为+33dB,单边带噪声系数(SSB NF)为9.6dB,输入参考三阶交调点(ⅡP3)为-11Bm;在最小增益模式下,电压增益为+14dB,单边带噪声系数为28dB,输入参考三阶交调点为+8dBm.射频前端电路面积为1.04mm×0.98mm,工作电压为1.8V,消耗电流为30mA.     

用于UHF RFID读写器的射频前端CMOS混频电路北大核心CSCD

提出了900 MHz频段下射频识别(RFID)读写器芯片射频前端接收器混频器模块,给出了读写器芯片的前端混频电路结构。采用单平衡无源混频器的特殊结构,降低了载波泄漏的干扰,后级接跨阻放大器,抑制了后级电路的噪声。通过电路内部复数反馈可以控制接收机等效输入阻抗实部与虚部的变化,进行阻抗匹配,省去了片外匹配网络。在SMIC 0.13μm CMOS混和信号工艺下进行流片。测试结果表明,核心模块的电源电压为3 V,电流为7.3 mA,混频器的转换增益为21.8 dB,输入1 dB压缩点为-5.11 dBm,IP3为4.6 dBm,芯片核心面积为0.83 mm×0.56 mm。     

用于UHF RFID读写器的射频前端CMOS混频电路

提出了900 MHz频段下射频识别(RFID)读写器芯片射频前端接收器混频器模块,给出了读写器芯片的前端混频电路结构。采用单平衡无源混频器的特殊结构,降低了载波泄漏的干扰,后级接跨阻放大器,抑制了后级电路的噪声。通过电路内部复数反馈可以控制接收机等效输入阻抗实部与虚部的变化,进行阻抗匹配,省去了片外匹配网络。在SMIC 0.13μm CMOS混和信号工艺下进行流片。测试结果表明,核心模块的电源电压为3 V,电流为7.3 mA,混频器的转换增益为21.8 dB,输入1 dB压缩点为-5.11 dBm,IP3为4.6 dBm,芯片核心面积为0.83 mm×0.56 mm。     

0.18μm CMOS X波段接收机射频前端设计

本文给出了一个采用TSMC 0.18 m CMOS工艺应用于X波段SAR(合成孔径雷达)的单片接收机射频前端的设计。接收机前端由低噪声放大器和混频器组成,低噪声放大器工作在9 GHz~11GHz,混频器将10GHz的射频信号转换到2GHz中频,本振信号由片外提供。在X波段频率下,尽管CMOS 0.18μm工艺特征频率比较低,工作仍然实现了低噪声系数,提高了集成度。测试结果表明,本设计在300MHz的带宽上实现了20dB的转换增益,噪声系数达到2.7Db,输入1dB压缩点达到-19.2dBm,在1.8V的电源电压下前端消耗26.6mA电流,芯片面积为1.3×0.97mm2。     

应用于TD-SCDMA/LTE/LTE-Advanced收发机的多频多模CMOS射频接收前端电路设计

设计了应用于TD-SCDMA/LTE/LTE-Advanced收发机中的多频段、多模式射频接收前端电路. 该前端电路采用直接变频结构,包含两个可调谐差分低噪声放大器、一个正交混频器和两个中频放大器。其中,两个独立的可调谐低噪声放大器覆盖了4个射频频段,在较低的功耗下实现足够的增益和噪声性能. 并且利用开关电容阵列来调节低噪声放大器的谐振频率点. 低噪声放大器通过混频器的驱动级跨导晶体管实现结合。正交混频器采用折叠式双平衡吉尔伯特结构,利用PMOS晶体管作为本振信号的开关对,从而降低1/f噪声. 前端电路具有3种增益模式以获得更大的动态范围. 模式配置和频段选择功能都由片上的SPI模块控制. 该射频前端电路采用TSMC0.18um RF CMOS工艺实现,芯片面积为1.3 mm2. 全部频段上测量的转换增益高于43dB,双边带噪声系数低于3.5dB. 整个电路在1.8V供电电压下,消耗电流约31mA。     

一款低噪声卫星导航接收机射频前端的设计

基于0.18tm RF CMOS工艺,采用低中频系统结构,设计了一款可应用于全球定位导航系统(GPS) L1频段和北斗二代(BD2) B1频段的低噪声卫星导航接收机的射频模拟前端芯片.该前端包括低噪声放大器、无源混频器、中频放大器、复数带通滤波器和数控可变增益放大器.其中低噪声放大器采用电流舵技术,与无源混频器一起,提高了射频前端的1 dB压缩点输入功率(Pi(1dB)),有效地改善了系统的线性度.测试结果显示,在GPS L1频点,系统的最大增益107.2 dB,噪声系数达到1.8 dB,动态增益66 dB,镜像抑制比约为39.54 dB,Pi(1dB)为-41 dBm,电源为1.8V时,消耗电流16 mA,芯片面积1.7 mm×0.8 mm.     

一种应用于多模多标准接收机的CMOS宽带电流换向无源混频器的设计

本文报告了一种应用于直接变频多模多标准接收机的宽带无源混频器的设计。本文首先比较了电流换向无源混频器和传统有源混频器的优缺点,然后分析了无源混频器开关级的源阻抗和负载阻抗对其线性度的影响。特别的,本文分析了电流跨阻放大器的输入阻抗对混频器线性度的影响。我们基于CMOS 0.18 μm 工艺设计了一个电流换向无源混频器来验证我们的分析。该电路无电感,并可以宽带工作。在芯片测试结果表明,当射频端输入频率为700 MHz 到2.3 GHz时,混频器可以实现21 dB的变频增益,输出中频带宽为10 MHz。测量的输入三阶截点为9dBm, 输出中频为10MHz处的双边带噪声系数为10.6 dB.芯片面积为0.19 mm2。芯片从1.8V电源上抽取电流5.5 mA.     

医疗内窥检查超低功耗电感复用射频前端芯片设计

本文阐述了一种应用于医疗探测的工作在407～425MHz频段的电感复用射频前端芯片。本射频前端芯片由超低功耗电流复用LNA、Mixer和高发射效率PA构成。本文提出了一种新型的电感复用射频前端结构,通过接收机和发射机输入输出共用电感,不仅有效避免了双工器的使用降低了芯片成本,而且节省了片外元件的数量,满足了高集成度的应用要求。该射频前端芯片在0.18μm标准CMOS工艺下进行了流片,芯片面积0.43mm2。作为接收机和发射机使用时,射频前端功耗分别为0.45mA和1.53mA,是一款超低功耗、高集成度的射频前端芯片。     

应用于SC-UWB收发机的CMOS射频接收前端电路设计

设计了应用于单载波超宽带（SC-UWB）无线收发机中的CMOS射频接收前端电路. 该前端电路采用直接变频结构,包含一个差分低噪声放大器（LNA）、一个正交混频器和两个中频放大器。其中,LNA采用源级电感负反馈结构.首先给出了该类型LNA中输入匹配带宽关于栅源电容、工作频率及匹配目标值的表达式 然后考虑到栅极片上电感、键合电感及其精度,提出了在增益和功耗约束下的噪声因子优化策略。该LNA利用两级放大级的不同谐振点实现了7.1~8.1GHz频段上的平坦增益,并具有两种增益模式来改善接收机动态范围. 正交混频器采用折叠式双平衡吉尔伯特结构. 该射频前端电路采用TSMC0.18um RF CMOS工艺设计,芯片面积为1.43 mm2. 在高、低增益模式下,测得的最大转换增益分别为42dB和22dB,输入1dB压缩点为-40dBm和-20dBm,S11低于-18dB和-14.5dB,中频3dB带宽大于500MHz. 高增益模式下双边带噪声因子为4.7dB. 整个电路在1.8V供电电压下功耗为65mW。     

A 1.5-V multi-mode quad-band RF receiver for GSM/EDGE/CDMA2K in 90-nm digital CMOS process

A single chip quad-band multi-mode (GSM900/ DCS1800/PCS1900/CDMA2K) direct-conversion RF receiver with integrated baseband ADCs is presented. The fully integrated RF receiver is implemented in a 90-nm single poly, six level metal, standard digital CMOS process with no additional analog and RF components. The highly digital multi-mode receiver uses minimum analog filtering and AGC stages, digitizing useful signal, dynamic DC offsets and blockers at the mixer output. The direct-conversion GSM front-end utilizes resistive loaded LNAs with only two coupled inductors per LNA. The GSM front-end achieves a 31.5 dB gain and a 2.1 dB integrated noise figure with a 5 dB noise figure under blocking conditions. The CDMA2K front-end utilizes a self-biased common-gate input amplifier followed by passive mixers, achieving wideband input matching from 900 MHz up to 2.1 GHz with an IIP3 of +8 dBm. The GSM receiver consumes 38 mA from a power supply of 1.5 V and CDMA2K receiver consumes 16 mA in the low band and 21 mA in the high band. The multi-mode receiver, including LO buffers and frequency dividers, ADCs, and reference buffers, occupies 2.5 mm/sup 2/.     

A fully integrated direct-conversion digital satellite tuner in 0.18μm CMOS

A fully integrated direct-conversion digital satellite tuner for DVB-S/S2 and ABS-S applications is presented.A broadband noise-canceling Balun-LNA and passive quadrature mixers provided a high-linearity low noise RF front-end,while the synthesizer integrated the loop filter to reduce the solution cost and system debug time.Fabricated in 0.18μm CMOS,the chip achieves a less than 7.6 dB noise figure over a 900-2150 MHz L-band, while the measured sensitivity for 4.42 MS/s QPSK-3/4 mode is -91 dBm at the PCB connector.The fully integrated integer-N synthesizer operating from 2150 to 4350 MHz achieves less than 1℃integrated phase error. The chip consumes about 145 mA at a 3.3 V supply with internal integrated LDOs.     

A low voltage CMOS RF front-end for IEEE 802.11b WLAN transceiver

A low voltage CMOS RF front-end for IEEE 802.11b WLAN transceiver is presented. The problems to implement the low voltage design and the on-chip input/output impedance matching are considered, and some improved circuits are presented to overcome the problems. Especially, a single-end input, differential output double balanced mixer with an on-chip bias loop is analyzed in detail to show its advantages over other mixers. The transceiver RF front-end has been implemented in 0.18 um CMOS process, the measured results show that the Rx front-end achieves 5.23 dB noise figure, 12.7 dB power gain (50 ohm load), −18 dBm input 1 dB compression point (ICP) and −7 dBm IIP3, and the Tx front-end could output +2.1 dBm power into 50 ohm load with 23.8 dB power gain. The transceiver RF front-end draws 13.6 mA current from a supply voltage of 1.8 V in receive mode and 27.6 mA current in transmit mode. The transceiver RF front-end could satisfy the performance requirements of IEEE802.11b WLAN standard. Supported by the National Natural Science Foundation of China, No. 90407006 and No. 60475018.     

A 0.25-/spl mu/m CMOS quad-band GSM RF transceiver using an efficient LO frequency plan

This paper describes a single-chip CMOS quad-band (850/900/1800/1900 MHz) RF transceiver for GSM/GPRS applications. It is the most important design issue to maximize resource sharing and reuse in designing the multiband transceivers. In particular, reducing the number of voltage-controlled oscillators (VCOs) required for local oscillator (LO) frequency generation is very important because the VCO and phase-locked loop (PLL) circuits occupy a relatively large area. We propose a quad-band GSM transceiver architecture that employs a direct conversion receiver and an offset PLL transmitter, which requires only one VCO/PLL to generate LO signals by using an efficient LO frequency plan. In the receive path, four separate LNAs are used for each band, and two down-conversion mixers are used, one for the low bands (850/900 MHz) and the other for the high bands (1800/1900 MHz). A receiver baseband circuit is shared for all four bands because all of their channel spaces are the same. In the transmit path, most of the building blocks of the offset PLL, including a TX VCO and IF filters, are integrated. The quad-band GSM transceiver that was implemented in 0.25-/spl mu/m CMOS technology has a size of 3.3/spl times/3.2 mm/sup 2/, including its pad area. From the experimental results, we found that the receiver provides a maximum noise figure of 2.9 dB and a minimum IIP3 of -13.2dBm for the EGSM 900 band. The transmitter shows an rms phase error of 1.4/spl deg/ and meets the GSM spectral mask specification. The prototype chip consumes 56 and 58 mA at 2.8 V in the RX and TX modes, respectively.     

A fractional-N frequency synthesizer for single-chip UHF RFID reader

A novel fractional-N frequency synthesizer which is based on delta sigma modulator (DSM) and specialized for single-chip UHF 860-to-960 MHz band radio frequency identification (RFID) reader is proposed in this paper. The fractional-N synthesizer is implemented in 0.18 μm CMOS process. The phase noise of the fractional-N synthesizer is approximately ?109 and ?129 dBc/Hz at 200 kHz and 1 MHz offset from 900 MHz operating frequency while drawing 9.6 mA from 1.8 V power supply. The synthesizer is evaluated by implementing it in a direct conversion RF front-end. The front-end features a noise figure of 3.5 dB and an input-referred third-order intercept point of 5 dBm.     

433MHz ASK接收机射频前端电路设计

设计了一款应用在433MHz ASK接收机中的射频前端电路。在考虑了封装以及ESD保护电路的寄生效应的同时,从噪声、匹配、增益和线性度等方面详细讨论了低噪声放大器和下混频器的电路设计。采用0.18μm CMOS工艺,在1.8V的电源电压下射频前端电路消耗电流10.09 mA。主要的测试结果如下:低噪声放大器的噪声系数、增益、输入P1dB压缩点分别为1.35 dB、17.43 dB、-8.90dBm;下混频器的噪声系数、电压增益、输入P1dB压缩点分别为7.57dB、10.35dB、-4.83dBm。     

A Wideband CMOS RF Front-End Using AC-Coupled Current Mirrored Technique for Multiband Multistandard Mobile TV Tuners

In this paper, a wideband CMOS radio frequency (RF) front-end for various terrestrial mobile digital TV applications such as digital video broadcasting-handheld, terrestrial digital multimedia broadcasting, and integrated services digital broadcasting-terrestrial is proposed. To cover VHF III, UHF, and L bands and reduce the silicon area simultaneously, it employs three low-noise amplifiers and single-to-differential transconductors and shares the rest of the RF front-end. By applying ac-coupled current mirrored technique, the proposed RF front-end has good wideband performance, high linearity, and precise gain control. It is fabricated in 0.18 mum CMOS process and draws 15 mA~20 mA from a 1.8 V supply voltage for each band. It shows a gain of more than 29 dB, noise figure of lower than 2.5 dB, IIP2 of more than 30 dBm, IIP3 of more than -10 dBm for entire bands.     

A 5–6 GHz 1-V CMOS Direct-Conversion Receiver With an Integrated Quadrature Coupler

This paper describes a novel monolithic low voltage (1-V) CMOS RF front-end architecture with an integrated quadrature coupler (QC) and two subharmonic mixers for direct-down conversion. The LC-folded-cascode technique is adopted to achieve low-voltage operation while the subharmonic mixers in conjunction with the QC are used to eliminate LO self-mixing. In addition, the inherent bandpass characteristic of the LC tanks helps suppression of LO leakage at RF port. The circuit was fabricated in a standard 0.18-mum CMOS process for 5-6 GHz applications. At 5.4 GHz, the RF front-end exhibits a voltage gain of 26.2 dB and a noise figure of 5.2 dB while dissipating 45.5 mW from a 1.0-V supply. The achieved input-referred DC-offset due to LO self-mixing is below -110.7 dBm.     

3 V, 28 mW Si-bipolar front-end IC for 900 MHz homodyne wirelessreceivers

A 900 MHz homodyne receiver front-end bipolar chip is presented. The circuit consists of a low-noise amplifier and two double-balanced mixers for in-phase and quadrature channels. The power supply voltage is 3 V and power dissipation is 28 mW. The measured performance includes 33.5 dB voltage gain, a 3.1 dB noise figure, -13 dBm input referred IP3, -95 dB LO leakage into the RF port on wafer probing, and less than 0.1 dB I/Q magnitude imbalance     

A low power 3-5 GHz CMOS UWB receiver front-end

A novel low power RF receiver front-end for 3-5 GHz UWB is presented. Designed in the 0.13μm CMOS process, the direct conversion receiver features a wideband balun-coupled noise cancelling transconductance input stage, followed by quadrature passive mixers and transimpedance loading amplifiers. Measurement results show that the receiver achieves an input return loss below-8.5 dB across the 3.1-4.7 GHz frequency range, max-imum voltage conversion gain of 27 dB, minimum noise figure of 4 dB, IIP3 of-11.5 dBm, and IIP2 of 33 dBm. Working under 1.2 V supply voltage, the receiver consumes total current of 18 mA including 10 mA by on-chip quadrature LO signal generation and buffer circuits. The chip area with pads is 1.1 × 1.5 mm2.