一种高性能共模反馈CMOS运算放大器

介绍了一种具有高增益,高电源抑制比(CMRR)和大带宽的两级共源共栅运算放大器。此电路在两级共源共栅运算放大器的基础上增加共模反馈电路,以提高共模抑制比和增加电路的稳定性。电路采用0.35μm标准CMOS工艺库,在Cadence环境下进行仿真。结果显示,该放大器增益可达到101 dB,负载电容为10 pF时,单位增益带宽大约为163 MHz,共模抑制比可达101dB,电路功耗仅为0.5 mW。     

一种高增益三级运算放大器

提出了一种高增益三级运算放大器。采用五管全差分、套筒式共源共栅、典型共源级结构作为运算放大器的放大级,采用共模抑制电路、频率补偿电路、高摆幅偏置电路,提高了运算放大器的性能。结果表明,在3 V电源电压、4 pF负载电容的条件下,该运算放大器的开环直流增益为155 dB,单位增益带宽为112 MHz,相位裕度为84.1°,电源抑制比为151 dB,共模抑制比为-168 dB。该运算放大器的补偿电容较小,节省了面积。     

一种高CMRR和PSRR的共源共栅放大器

针对传统运算放大器共模抑制比和电源抑制比低的问题,设计了一种差分输入结构的折叠式共源共栅放大器。本设计采用两级结构,第一级为差分结构的折叠式共源共栅放大器,并采用MOS管作为电阻,进一步提高增益、共模抑制比和电源电压抑制比;第二级采用以NMOS为负载的共源放大器结构,提高增益和输出摆幅。基于LITE—ON40V1．0μm工艺,采用Spectre对电路进行仿真。仿真结果表明,电路交流增益为125．8dB,相位裕度为62.8°,共模抑制比140．9dB,电源电压抑制比125．5dB。     

一种采用增益增强技术的全差分运放设计和实现

设计了一种采用增益增强技术并带有共模反馈的全差分运算放大器.该运算放大器主要由三个折叠式共源共栅结构的运放、一个偏置电路和一个共模反馈电路组成.运算放大器采用chartered 0.35 μm CMOS工艺实现,仿真结果表明运放开环增益为106.8 dB,单位增益带宽为58 MHz,相位裕度为79°(负载Cload=1 pF).对流片运放进行测试和分析,运算放大器测试指标和仿真指标基本接近,较好达到预先的设计要求.     

一种用于采保电路的宽带高增益放大器的设计

分析了跨导运算放大器的电路结构,采用两级放大电路,考虑到全差分结构中要使用共模反馈,用共源共基和共源共栅电路来实现电路的设计.同时对部分性能指标进行了优化,其中包括增益非线性引入的误差和不完全建立误差.设计了一种宽带高增益跨导放大器,利用0.35 μm Bi CMOS工艺条件下,Spectre仿真得到运算放大器的开环增益大于60 dB,单位增益带宽可达2.1 GHz,输出摆幅能达到1.5 V.     

一种高共模抑制比轨到轨全差分运算放大器

针对传统全差分运算放大器电路存在输入输出摆幅小和共模抑制比低的问题,提出了一种高共模抑制比轨到轨全差分运算放大器电路。电路的输入级采用基于电流补偿技术的互补差分输入对,实现较大的输入信号摆幅;中间级采用折叠式共源共栅结构,获得较大的增益和输出摆幅;输出级采用共模反馈环路控制的A类输出结构,同时对共模反馈环路进行密勒补偿,提高电路的共模抑制比和环路稳定性。提出的全差分运算放大器电路基于中芯国际(SMIC) 0.13μm CMOS工艺设计,结果表明,该电路在3.3 V供电电压下,负载电容为5 pF时,可实现轨到轨的输入输出信号摆幅;当输入共模电平为1.65 V时,直流增益为108.9 dB,相位裕度为77.5°,单位增益带宽为12.71 MHz;共模反馈环路增益为97.7 dB,相位裕度为71.3°;共模抑制比为237.7 dB,电源抑制比为209.6 dB,等效输入参考噪声为37.9 nV/Hz^1/2@100 kHz。     

一种高单位增益带宽CMOS全差分运算放大器

设计并讨论了一种高单位增益带宽CMOS全差分运算放大器。由于折叠共源共栅结构电路具有相对高的单位增益带宽以及开关电容共模反馈电路稳定性好、对运放频率特性影响小等优点,故设计的放大器采用了折叠共源共栅结构以及开关电容共模反馈电路技术,并达到了高单位增益带宽的设计目的。基于TSMC0·25μmCMOS工艺,仿真结果表明,在2·5V的单电源电压下,运算放大器的直流开环增益为70dB,单位增益带宽为500MHz。     

一种高增益带宽CMOS全差分运算放大器的设计

介绍了一种采用折叠式共源共栅结构的高增益带宽全差分运算放大器的设计和实现,详细讨论了折叠式共源共栅放大器的电路结构、共源共栅偏置电路,以及开关电容共模反馈电路(SCCMFB).电路的设计基于CSMC 0.5μm DPTM 5V混合信号工艺.仿真结果表明,该电路在5V电源电压下具有64 dB直流开环增益、155 MHz单位增益带宽.通过在一款ADC电路中流片验证,该放大器达到设计指标要求.     

高性能折叠式共源共栅运算放大器的设计

折叠式共源共栅结构能够提供足够高的增益,并且能够增大带宽、提高共模抑制比和电源电压抑制比.基于Chartered 0.35 μm工艺,设计了一种折叠式共源共栅结构的差分输入运算放大器,给出了整个电路结构.Spectre仿真结果表明,该电路在3.3V电源电压下直流开环增益为121.5dB、单位增益带宽为12 MHz、相位裕度为61.4°、共模抑制比为130.1dB、电源电压抑制比为105 dB,达到了预期的设计目标.     

一种高速CMOS全差分运算放大器

设计并讨论了一种高速CMOS全差分运算放大器.设计中采用了折叠共源共栅结构、连续时间共模反馈以及独特的偏置电路,以期达到高速及良好的稳定性.基于TSMC 0.25 μ m CMOS工艺,仿真结果表明,在2.5V的单电源电压下,运算放大器的直流开环增益为71.9dB,单位增益带宽为495MHz(CL=0.5pF),建立时间为24ns,功耗为3.9mW.     

High-performance current-mode instrumentation amplifier circuit

A high-performance current-mode instrumentation amplifier circuit is described in this paper. It has a high common mode rejection ratio, high gain, high accuracy, wide bandwidth and bandwidth gain-independence. It utilizes commercially available integrated circuits and is easily implemented. Experimental results show that at low frequencies a common mode rejection ratio of 120 dB is attainable.     

电荷泵型LED驱动器的CMOS误差放大器设计

结合电荷泵型LED驱动器的工作要求,从减小输出电压纹波、稳定输出电压出发,设计了一款误差放大器。该误差放大器具有较大的工作电压范围,使电荷泵型LED驱动器高效率低噪声工作。基于CHRT0．35μm CMOS MIXED SIGNAL TECHNOLOGY进行仿真,结果表明,在2．7～5V工作电压范围内,开环电压增益约等于72dB,相位裕度约等于65°,单位增益带宽约等于4．6MHz,共模抑制比CMRR约等于113dB,电源抑制比PSRR约等于100dB。     

A MOS switched-capacitor instrumentation amplifier

Describes a precision switched-capacitor sampled-data instrumentation amplifier using NMOS polysilicon gate technology. It is intended for use as a sample-and-hold amplifier for low level signals in data acquisition systems. The use of double correlated sampling technique achieves high power supply rejection, low DC offset, and low 1/f noise voltage. Matched circuit components in a differential configuration minimize errors from switch channel charge injection. Very high common mode rejection (120 dB) is obtained by a new sampling technique which prevents the common mode signal from entering the amplifier. This amplifier achieves 1 mV typical input offset voltage, greater than 95 dB PSRR, 0.15 percent gain accuracy, 0.01 percent gain linearity, and an RMS input referred noise voltage of 30 /spl mu/V/input sample.     

A design for high noise rejection in a pseudodifferentialpreamplifier for hard disk drives

A study of supply and system noise rejection for a pseudodifferential amplifier is presented in this paper. This pseudodifferential amplifier is aimed at high data-rate disk drive signal sensing and preamplification applications. This high rejection was achieved by improving the rejection of the pseudodifferential amplifier and also by carefully designing the interconnect flex circuit where the preamplifier is mounted. The measured rejection to power supply, ground and system noise is above 50 dB over a 300 MHz bandwidth. This is significant for a pseudodifferential amplification system. The gain of the preamplifier is 47 dB and write mode to read mode switching time is 210 ns. This preamplifier currently supports disk drive data rates over 270 Mb/s     

The Matrix Balun—A Transistor-Based Module for Broadband Applications

In this paper the analysis and design of a new active balun with very broadband performance, the matrix balun, are reported. Measured results show a common mode rejection ratio, CMRR, larger than 15 dB between 4 and 42 GHz while exhibiting 2 dB single-ended gain with a ripple of 1 dB. The balun was realized in a 0.15 mum GaAs mHEMT process. It occupies a chip area of 0.63 mm² and consumes a dc power of 20 mW. The same matrix balun circuit may also be biased for amplification and used as a matrix amplifier. The circuit then exhibits 10.5 dB gain up to 63 GHz with 1 dB ripple above 5.5 GHz and a power consumption of 67 mW.     

An image-reject down-converter for 802.11a and HIPERLAN2 wireless LANs

An image-reject down-converter for IEEE 802.11a and ETSI HIPERLAN2 wireless local area networks was implemented in a low-cost 46-GHz-f _T silicon bipolar process. The circuit integrates a variable-gain low noise amplifier and a double-balanced mixer along with passive image rejection filters. It exhibits a 4-dB noise figure and a power gain of 23 dB. By reducing the low noise amplifier gain by 9 dB (thanks to a 1-bit gain control), the down-converter achieves an input 1-dB compression point of –14 dBm, while drawing only 23 mA from a 3-V supply voltage. The adopted filtering approach provides an image rejection ratio higher than 60 dB.     

新型差分三通带滤波器设计

基于T型支节加载均匀阻抗谐振器,设计了一款新型小型化差分三通带滤波器,并对该滤波器进行了改进设计。所设计滤波器的三个通带中心频率分别为2,6.4,9.2 GHz。-3 dB相对带宽分别为20%(1.85~2.25 GHz)、7%(6.21~6.71 GHz)、5%(8.98~9.44 GHz),通带内插入损耗小于1.5 dB。为了实现良好的共模抑制,在该滤波器中心对称处增加了开路支节,高频处的共模抑制得到显著提高。该滤波器结构简单,能够实现良好的性能,仿真结果与理论分析一致。     

220GHz低噪声放大器研究

基于IHP锗硅BiCMOS工艺,研究和实现了两种220 GHz低噪声放大器电路,并将其应用于220 GHz太赫兹无线高速通信收发机电路。一种是220 GHz四级单端共基极低噪声放大电路,每级电路采用了共基极（Common Base, CB）电路结构,利用传输线和金属-绝缘体-金属(Metal-Insulator-Metal, MIM)电容等无源电路元器件构成输入、输出和级间匹配网络。该低噪放电源的电压为1.8 V,功耗为25 mW,在220 GHz频点处实现了16 dB的增益,3 dB带宽达到了27 GHz。另一种是220 GHz四级共射共基差分低噪声放大电路,每级都采用共射共基的电路结构,放大器利用微带传输线和MIM电容构成每级的负载、Marchand-Balun、输入、输出和级间匹配网络等。该低噪放电源的电压为3 V,功耗为234 mW,在224 GHz频点实现了22 dB的增益,3 dB带宽超过6 GHz。这两个低噪声放大器可应用于220 GHz太赫兹无线高速通信收发机电路。     

A pseudodifferential amplifier for bioelectric events with DC-offset compensation using two-wired amplifying electrodes

Most wired active electrodes reported so far have a gain of one and require at least three wires. This leads to stiff cables, large connectors and additional noise for the amplifier. The theoretical advantages of amplifying the signal on the electrodes right from the source has often been described, however, rarely implemented. This is because a difference in the gain of the electrodes due to component tolerances strongly limits the achievable common mode rejection ratio (CMRR). In this paper, we introduce an amplifier for bioelectric events where the major part of the amplification (40 dB) is achieved on the electrodes to minimize pick-up noise. The electrodes require only two wires of which one can be used for shielding, thus enabling smaller connecters and smoother cables. Saturation of the electrodes is prevented by a dc-offset cancelation scheme with an active range of +/- 250 mV. This error feedback simultaneously allows to measure the low frequency components down to dc. This enables the measurement of slow varying signals, e.g., the change of alertness or the depolarization before an epileptic seizure normally not visible in a standard electroencephalogram (EEG). The amplifier stage provides the necessary supply current for the electrodes and generates the error signal for the feedback loop. The amplifier generates a pseudodifferential signal where the amplified bioelectric event is present on one lead, but the common mode signal is present on both leads. Based on the pseudodifferential signal we were able to develop a new method to compensate for a difference in the gain of the active electrodes which is purely software based. The amplifier system is then characterized and the input referred noise as well as the CMRR are measured. For the prototype circuit the CMRR evaluated to 78 dB (without the driven-right-leg circuit). The applicability of the system is further demonstrated by the recording of an ECG.