硅低温双极晶体管的数值模拟

本文讨论了有关低温双极器件模拟物理的数的低温模型和各种低温物理效应，确立了适用于低温双极器件模拟的数值分析方法，建立了适用于７７－３００Ｋ温度范围内硅双极器件模拟程序，最后模拟分析了一典型结构晶体管的常温和低温时的工作特性。     

与CMOS工艺兼容的横向双极晶体管直流特性的新算法

本文提出了一种适用于CMOS工艺中横向双极型晶体管直流特性计算的新方法。新方法采用解析形式计算电流I_c,所需模型参数均保留明确的物理意义,不用数值和曲线拟合参数的方法就能得到处于任何注入水平的本征收集极电流I_c和跨导g_(??)。该方法为在设计高精度的CMOS模拟IC中利用横向双极器件提供了良好的CAD器件模型。模型值和实验值呈现良好的一致性。     

基于Matlab的基极电流理想因子提取方法研究

采用Matlab数字分析方法,结合多晶硅发射极双极器件基极电流的构成情况,阐述了不同理想因子电流成分分离的基本原理和数学方法。利用该方法分析了多晶硅发射极双极器件在正向大电流激励下的电参数退化过程中不同理想因子基极电流的变化情况,分析了导致各电流分量变化的物理机制。该理想因子提取方法普遍适用于各类双极型器件。     

小尺寸超高频双极晶体管工艺及特性模拟

基于通信系统中射频电路设计的特殊要求,对小尺寸(基区宽度低于100nm)、超高频(特征频率高于15GHz)双极晶体管工艺制程和器件的物理特性进行了模拟,为工艺线流片进行可行性研究。该器件采用BiCMOS制程结构实现,在对小尺寸、超高频双极性器件物理模型进行详尽分析的基础上,实现了该器件工艺级(Sentaurus Process)及器件物理特性级(Sentaurus Device)的仿真,提出TCAD工艺及器件的一体化设计方案。模拟结果表明,在高频指标参数17GHz下,所得β值接近于80,满足设计要求。     

77K MOSFET计算机模拟增量限制方法

对低温器件计算机模拟方法作了具体的考虑。从求解变量和半导体物理意义出发，数值计算结果事先有一个定性范围，如果每一次循环的迭代初值都修正到这个数值范围内，那么选代过程将以更快的速度接近真解。提出了适用于低温半导体器件计算机模拟的增量限制方法，并且将该方法插入ＭＩＮＩＭＯＳ４．０进行了数值实验。结果表明，设置增量限制能保证低温半导体器件模拟的数值收敛性，并巨有较快的收敛速度。     

低温半导体器件模拟中若干问题与对策

低温半导体器件以其优异的性能,可以满足军用和民用等领域中常规器件无法满足的特殊要求.低温微电子学日益成为微电子技术的重要的发展方向,而低温器件计算机模拟则是低温器件分析与设计的重要手段.本文着重讨论了常温下半导体器件的计算机模拟方法在低温下的蜕变及相应的对策,分析了导致常温下方法失效的主要物理参数的低温模型,并提出了低温器件模拟加速收敛的几种数值技术.     

半导体器件

Y2002-63209 02173252001年 IEEE 双极/双极互补 MOS 电路与技术会议录=2001 IEEE proceedings of the 2001 bipolar/BiCMOSOrcuits and technology meeting[会,英]/IEEE ElectronDevices Society.—2001.—199P.(E)本会议录收集了于2001年9月30～10月2日在明尼苏达州 Minneapolis 召开的双极互补 MOS 集成电路及技术会议上发表的40篇论文,内容涉及双极技术进展,硅与锗硅晶体管建模0.25μm与0.18μm 双极互补 MOS 技术,双极器件与器件物理,射频系统与元件,信息时代的模拟设计,高速电路设计。     

LDO中过温保护电路的设计

LDO是一个微型的片上系统,他包括调整管、采样网络、精密基准源、差分放大器、过流保护、过温保护等电路。分析了LDO中过温保护电路的设计,主要介绍了LDO中双极型过温保护电路和CMOS过温保护电路。由于双极器件开发早、工艺相对成熟、稳定,而且用双极工艺可以制造出速度高、驱动能力强、模拟精度高的器件,适用于高精度的模拟集成电路。因此,双极型集成稳压器应用广泛,其设计技术和制造工艺比较成熟和完善。但双极型过温保护电路本身存在热振荡的问题。给出一种新型的CMOS过温保护电路,他具有温度迟滞功能,有效地避免了芯片出现热振荡。     

双极晶体管发射极电阻的提取方法及应用研究

以双多晶自对准互补双极器件中NPN双极晶体管为例,阐述了发射极电阻提取的基本原理和数学方法。在大电流情况下,NPN管的基极电流偏离理想电流是发射极串联电阻效应引起的。该提取方法综合考虑了辐照过程中NPN管的电流增益退化特性,分析了总剂量辐照效应对NPN管的损伤机理和模式。该提取方法适用于多晶硅发射极器件,也适用于SiGe HBT器件。     

高性能硅双极器件的发展

以ECL电路为主,讨论了硅双极器件近期的发展。简述了VLSI中ECL电路结构和性能之后,着重讨论双极器件的按比例缩小、结构的改进以及相关的工艺技术的发展,最后分析了双极器件的低温工作性能。     

BILOW-simulation of low-temperature bipolar device behavior

The BILOW simulation program for investigating bipolar transistor behavior in the temperature range 77-300 K is discussed. Differences between the numerical approaches required for simulation of low-temperature behavior compared to room-temperature simulation are presented. Efficient numerical models for the physical parameters in the carrier transport equations and Poisson's equation for the temperature range of 77-300 K, including a new highly accurate numerical model for the temperature and doping concentration dependence of carrier mobility, are discussed. A temperature- and doping-concentration-dependent model for apparent bandgap narrowing is also discussed. The internal characteristics of a typical bipolar transistor are simulated over the 300-77 K range. The behavior of current gain β and the unity gain frequency f_T versus collector current density for different temperatures are calculated and discussed     

Two-dimensional analysis of a BiNMOS transistor operating at 77 Kusing a modified PISCES program

The authors present a detailed two-dimensional numerical simulation study on the steady-state and turn-on transient behavior of a BiNMOS device operating at 77 K using PISCES-2B with modified low-temperature models. It is shown that the switching speed of the BiNMOS device, which is designed for operation at room temperature, is degraded for low-temperature operation. The BiNMOS device structure and the low-temperature device models for the two-dimensional (2D) device simulator are described, following by the steady-state and the transient analysis of the BiNMOS device. The turn-on transient performance of the BiNMOS device shows that, at 77 K, the switching time, which is determined by the load-related delay and the intrinsic delay of the bipolar device, increases about 45% from its 300 K value for an output load of 0.1 pF/μm     

A closed-form analytical forward transit time model consideringspecific models for bandgap-narrowing effects andconcentration-dependent diffusion coefficients for BJT devices operatingat 77 K

The authors report a closed-form analytical low-temperature forward transit time model considering bandgap-narrowing effects and concentration-dependent diffusion coefficients based on the entire shape of the emitter and base doping profiles for bipolar junction transistor (BJT) devices operating at 77 K. As verified by the PISCES simulation results, the new closed-form analytical model provides a better low-temperature forward transit time model compared to the model in which bandgap-narrowing effects and concentration-dependent diffusion coefficients are not considered     

工作在液氮温度下的低频低噪声双极晶体管的研究

对双极晶体管的低温物理模型和低频噪声模型进行了研究，认为低温下硅双极晶体管电流增益下降的主要原因是低温下非理想基极电流的增加。同时指出，低温下硅双极晶体管１／ｆ噪声的增大，是由于低温下电流增益的减小和载流子在体内和表面的复合增加。通过优化设计，做出了一种低温、低频、低噪声硅双极晶体管。测试表明，在室温（３００Ｋ）下，电流增益、低频转折频率、１ｋＨｚ点的噪声电压分别为β≥８００，ｆ＿Ｌ≤３０Ｈｚ，Ｅｎ（１ｋＨｚ）≤１．５ｎＶ／　　；低温（７７Ｋ）下，电流增益、低频转折频率、１ｋＨｚ点的噪声电压分别为β≥３０，ｆ＿Ｌ≤３００Ｈｚ，Ｅｎ（１ｋＨｚ）≤１．２ｎＶ／。     

低温基区轻掺杂硅双极晶体管的温度比例因子设计规则

通过对电流增益温度模型的分析，表明发射区重掺杂引起的禁带变窄效应是低温下双极晶体管电流增益衰变的主要原因，提出了用温度比例因子设计低温基区轻掺杂双极晶体管的新设计方法，计算机模拟表明结果良好。     

Analyzing hot-carrier effects on cold CMOS devices

The operation of discrete and integrated CMOS ring oscillators was evaluated over the temperature range 77-300 K. Gate delays typically decreased by a factor of two at 77 K. Hot-carrier effects were enhanced by low-temperature operation, and transistor transconductance degradation occurred at low temperatures, which did not occur at room temperature as measured in the forward and inverse transistor curves. In marked contrast to dc stressing, ac stressing caused very little circuit degradation at low temperatures. By modeling the low-temperature phenomena at the MOSFET source junction, both hot-electron and hot-hole carrier effects were analyzed.     

双极器件中硅基区和锗硅基区的禁带变窄量

采用一种新的方法计算双极器件中离子注B硅基区和原位掺B的锗硅基区禁带变窄量．在器件基区的少子迁移率、多子迁移率和方块电阻已知的情况下,应用这种方法只需测量室温和液氮温度下的电学特性就可以获得禁带变窄量．这种方法从双极晶体管的集电极电流公式出发,利用VBE做自变量,在室温和液氮温度下测量器件的Gummel图,选取lnIC随VBE变化最为线性的一部分读出VBE及相应的IC数值,获得两条VBE-lnIC直线,通过求解两条直线的交点可以计算出基区的禁带变窄量ΔEG．利用这种方法测试了硅双极器件和锗硅基区双极器件,其基区禁带变窄量分别为41meV和125meV,这个测量结果与文献中的数值符合较好．     

GaAs inversion-base bipolar transistor (GaAs IBT)

A completely new type of GaAs bipolar transistor with a base formed by a two-dimensional hole gas has been fabricated. The transistor has no metallurgical base layer but has an extremely thin inversion hole layer working as a base layer. The current gain β = 5.6 at 77 K and β = 17.1 at 300 K was obtained for the common emitter mode.     

MOS device modeling at 77 K

The state of the art in self-consistent numerical low-temperature MOS modeling is reviewed. The physical assumptions that are required to describe carrier transport at low ambient temperatures are discussed. Particular emphasis is placed on the models for space charge (impurity freeze-out), carrier mobility (temperature dependence of scattering mechanisms at a semiconductor-insulator interface), and carrier generation-recombination (impact ionization). The differences with regard to the numerical methods required for the solution of low-temperature models compared to room-temperature models are explained. Typical results obtained with the simulator MINIMOS 4 are presented. These include comparisons of short-channel effects and hot-electron phenomena such as energy relaxation and avalanche breakdown at 77 K and 300 K ambient temperatures     

Low-temperature (77 K) BJT model with temperature dependences onthe injected condition and base resistance

A low-temperature (77-K) bipolar transistor model based on physical analysis by considering the temperature dependences of the injection condition and base resistance modulation is described. A charge-based injection factor which describes the temperature dependence of the ideality factor n is introduced by taking into account the electron and hole concentration ratios at the edges of the emitter-base depletion layer. The temperature dependence of base resistance modulation is explained by using the temperature dependences of the conductivity modulation effect, the base pushout effect, and the emitter current-crowding effect. Calculations using the model are compared with measurements, revealing excellent agreement over a wide temperature range from 50 to 298 K