共查询到20条相似文献,搜索用时 26 毫秒
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描述了采用直接数字式频率合成器加谐波发生器来进行频率合成的方法,提供了基于这种方法的10~18 GHz频率合成器设计方案,并就这种频率合成方法在雷达信号模拟系统中的使用进行了说明.该技术所产生的频率合成器具有电路简单、低杂散、低相噪、置频时间短等特点. 相似文献
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Taavi Viilukas Anton Karputkin Jaan Raik Maksim Jenihhin Raimund Ubar Hideo Fujiwara 《Journal of Electronic Testing》2012,28(4):511-521
The paper proposes a hierarchical untestable stuck-at fault identification method for non-scan synchronous sequential circuits. The method is based on deriving, minimizing and solving test path constraints for modules embedded into Register-Transfer Level (RTL) designs. First, an RTL test pattern generator is applied in order to extract the set of all possible test path constraints for a module under test. Then, the constraints are minimized using an SMT solver Z3 and a logic minimization tool ESPRESSO. Finally, a constraint-driven deterministic test pattern generator is run providing hierarchical test generation and untestability proof in sequential circuits. We show by experiments that the method is capable of quickly proving a large number of untestable faults obtaining higher fault efficiency than achievable by a state-of-the-art commercial ATPG. As a side effect, our study shows that traditional bottom-up test generation based on symbolic test environment generation at RTL is too optimistic due to the fact that propagation constraints are ignored. 相似文献
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This paper presents a new effective Built-In Self Test (BIST) scheme that achieves 100% fault coverage with low area overhead, and without any modification of the circuit under test (CUT), i.e., no test point insertion. The set of patterns generated by a pseudo-random pattern generator, e.g. a Linear Feedback Shift Register (LFSR), is transformed into a new set of patterns that provides the desired fault coverage. To transform these patterns, a ring architecture composed by a set of masks is used. During on-chip test pattern generation, each mask is successively selected to map the original pattern sequence into a new test sequence. We describe an efficient algorithm that constructs a ring of masks from the test cubes provided by an automatic test pattern generator (ATPG) tool. Moreover, we show that rings of masks are implemented very easily at low silicon area cost, without requiring any logic synthesis tool; a combinational mapping logic corresponding to the masks is placed between the LFSR and the CUT, together with a looped shift register that acts as a mask selecting circuit. Experimental results are given at the end of the paper, demonstrating the effectiveness of the proposed approach in terms of area overhead, fault coverage and test sequence length. Note that this paper is an extended version of [1]. 相似文献
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LFSR-Based Deterministic TPG for Two-Pattern Testing 总被引:1,自引:0,他引:1
This paper proposes an approach to designing a cost-effective deterministic test pattern generator (TPG) for two-pattern testing. Given a set of pre-generated test-pair set (obtained by an ATPG tool) with a pre-determined (path delay) fault coverage, a simple TPG is synthesized to apply the given test-pair set in a minimal test time. To achieve this objective, a configurable linear feedback shift register (CLFSR) structure is used. Techniques are developed to synthesize such a TPG, which is used to generate an unordered deterministic test-pair set. The resulting TPG is efficient in terms of hardware size and speed performance. Experiments on benchmark circuits indicate that TPG designed using the proposed procedure obtain high path delay fault coverage in short test length. 相似文献
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本文提出了一种基于折叠集的test-Der-clock结构的混合模式BIST设计方案,并且进行了低功耗的整体优化设计.该设计方案在电路结构上利用双模式LFSR将两部分测试生成器有机的进行了结合,针对伪随机测试序列与折叠测试序列两部分采用了不同的措施来优化测试生成器的设计,从而达到降低被测电路功耗的目的. 相似文献
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This work presents built-in self-test (BIST) techniques for the production testing of mixed signal circuits. The special test strategy for the typical mixed-signal component analog-to-digital converter (ADC) is discussed. The traditional test for such mixed-signal components can be completed through a DSP-based mixed-signal tester with an arbitrary waveform generator and a signal digitizer, but such a test is very costly and time consuming. Hence, a BIST strategy based on an on chip ramp generator (OCRG) is proposed in this work for testing ADC. This BIST method has an advantage testing ADC without DAC to overcome area overhead. This BIST method realizes the test controller, test pattern generation and output response analyser at the aspect of the on-chip circuitry. The demonstration of the proposed BIST is given through various simulation results in the last parts of this work. 相似文献
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There are usually many different ways to make a digital circuit testable using the BILBO methodology. Each solution can have different values of test time and area overhead. A design system based on the BILBO methodology has been developed that can efficiently explore the testable design space to generate a family of designs ranging from the minimal test time design to the minimal area overhead design. A designer can select an appropriate design based on trade-offs between test time and area overhead. The branch and bound technique is employed during the exploring process to prune the design space. This significantly reduces the execution time of this process. To effectively bound the exploring process, a very efficient test scheduler has been developed. Unlike previous approaches, this new test scheduler can process a partially testable design as well as a complete testable design. A test schedule for a design is constructed incrementally. The test scheduling procedures are presented along with experimental results that show that this test scheduler usually outperforms existing schedulers. In many cases, it generates an optimal test schedule. Experiments have been performed on several circuits generated by MABAL, a CAD synthesis tool, to demonstrate the performance and practicality of this system.This work was supported by the Defense Advanced Research Projects Agency and monitored by the Federal Bureau of Investigation under Contract No. JFBI90092. The views and conclusions considered in this document are those of the authors and should not be interpreted as necessarily representing the official policies, either expressed or implied, of the Defense Advanced Research Projects Agency or the U.S. Government. 相似文献
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分析了DDS技术的基本原理和基本结构,介绍了一种基于FPGA的DDS信号发生器设计方法。以FPGA芯片EP2C35F672C8为核心器件,辅以必要的模拟电路,在Quartus II9.0平台下实现系统设计的综合与仿真。实验测试表明该信号发生器输出的波形具有平滑、稳定度高和相位连续等优点,具有一定的工程实践意义。 相似文献
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Chakrabarty K. Murray B.T. Iyengar V. 《Very Large Scale Integration (VLSI) Systems, IEEE Transactions on》2000,8(5):633-636
We present a new approach for built-in test pattern generation based on the reseeding of twisted-ring counters (TRCs). The proposed technique embeds a precomputed deterministic test set for the circuit under test (CUT) in a short test sequence produced by a TRC. The TRC is designed using existing circuit flip-flops and does not add to hardware overhead beyond what is required for basic scan design. The test control logic is simple, uniform for all circuits, and can be shared among multiple CUTs. Furthermore, the proposed method requires no mapping logic between the test generator circuit and the CUT; hence it imposes no additional performance penalty. Experimental results for the ISCAS benchmark circuits show that it is indeed possible to embed the entire precomputed test set in a TRC sequence using only a small number of seeds 相似文献
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Toral Shah Anzhela Matrosova Masahiro Fujita Virendra Singh 《Journal of Electronic Testing》2018,34(1):53-65
Automatic test pattern generation (ATPG) is the next step after synthesis in the process of chip manufacturing. The ATPG may not be successful in generating tests for all multiple stuck-at faults since the number of fault combinations is large. Hence a need arises for highly testable designs which have 100% fault efficiency under the multiple stuck-at fault(MSAF) model. In this paper we investigate the testability of ROBDD based 2×1 mux implemented combinational circuit design. We show that the ROBDD based 2×1 mux implemented circuit is fully testable under multiple stuck-at fault model. Principles of pseudoexhaustive testing and multiple stuck-at fault testing of two level AND-OR gates are applied to one sub-circuit(2×1 mux). We show that the composite test vector set derived for all 2×1 muxes is capable of detecting multiple stuck-at faults of the circuit as a whole. Algorithms to derive test set for multiple stuck-at faults are demonstrated. The multiple stuck-at fault test set is larger than the single stuck-at fault test set. We show that the multiple stuck-at fault test set can be derived from the Disjoint Sum of Product expression which allows test pattern generation at design time, eliminating the need of an ATPG after the synthesis stage. 相似文献
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Miaris G.S. Goudos S.K. Iakovidis C. Vafiadis E. Sahalos J.N. 《Antennas and Propagation Magazine, IEEE》2002,44(5):62-74
A computer tool (ORAMA) for the synthesis of linear antenna arrays is presented. The orthogonal method (OM) and the orthogonal perturbation (OP) method are used. The orthogonal method derives the excitation of the elements of the array, while the orthogonal perturbation method quantizes the excitation and determines the position of the elements. The user has the options to select the array geometry, the case study for a specific desired pattern, the method to be used, and the element type. Several design cases with various constraints are presented. ORAMA (a demo of the software is available at http://rcl.physics.auth.gr) has been designed as a Windows MDI application for the academic classroom, as well as for professional antenna engineers. A set of examples for different array patterns shows the usefulness of the tool. 相似文献
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针对某型导弹测试设备电路板检测仪激励信号源具体要求,采用了基于直接数字频率合成技术(DDS)的信号发生器设计方法,介绍了DDS的工作原理,详细阐述了基于FPGA设计DDS信号发生器的主要环节和实现的方法。采用了硬件描述语言Verilog HDL,完成了信号发生器的电路设计和功能仿真,并通过DE2—70开发板结合嵌入式逻辑分析仪Signal—Tap Ⅱ进行了分析验证。实验结果表明,该信号发生器能较好地产生所需激励信号,具有较高的实用价值。 相似文献
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结合船用发电机保护的功能需求。介绍一种基于单片机的船用发电机实时保护装置。讨论如何实时监测多路信号并做出准确延时,描述一种友好的树形菜单结构。该装置硬件结构简单,精度高,程序扩展性好,易于维护。 相似文献