一种与标准CMOS工艺兼容的光电集成接收机设计与实现

设计了一种与标准CMOS工艺完全兼容的高速光电探测器和宽带光电集成接收机,并采用0.6μm标准CMOS工艺流片. 测试结果表明,该光电集成接收机的性能已接近实用要求. 探测器的频率响应带宽为1.11GHz,光电集成接收机的3dB带宽为733MHz;在误码率为10-12条件下,对波长为850nm的输入光信号,灵敏度达到-9dBm.     

与CMOS工艺兼容的硅高速光电探测器模拟与设计

用器件模拟的方法,设计了一种与常规CMOS 工艺兼容的硅高速光电探测器,该探测器可与CMOS接收机电路单片集成,对该探测器进行了器件模拟研究,给出了该探测器的电路模型.通过MOSIS(MOS implementation support project) 0.35μm COMS工艺制做了该探测器,实际测试了该器件的频率响应和波长响应,探测器频率响应在1GHz以上,峰值波长响应在0.69μm.     

与CMOS工艺兼容的硅高速光电探测器模拟与设计

用器件模拟的方法,设计了一种与常规CMOS 工艺兼容的硅高速光电探测器,该探测器可与CMOS接收机电路单片集成,对该探测器进行了器件模拟研究,给出了该探测器的电路模型.通过MOSIS(MOS implementation support project) 0.35μm COMS工艺制做了该探测器,实际测试了该器件的频率响应和波长响应,探测器频率响应在1GHz以上,峰值波长响应在0.69μm.     

高灵敏度CMOS光电集成接收机设计

设计了一个由调节型级联跨阻抗放大器(TIA)和双光电二极管(DPD)构成的CMOS光电集成(OEIC)接收机.具体分析了这个光电集成接收机的噪声和灵敏度及其相互关系.接收机中的噪声主要是电路中电阻的热噪声和MOS器件的闪烁噪声.提出了优化接收机灵敏度的方法.通过低成本的CSMC 0.6μm CMOS工艺流片并对芯片进行了测试.从测试眼图可知,该CMOS光电集成接收机可工作在1.25GB/s的传输速率下,灵敏度为-12dBm.     

前均衡CMOS光电集成接收机概念的提出和模拟

提出了一种解决CMOS光电集成接收机灵敏度和速度问题的新方法--前均衡法,即在接收放大电路的前端对传输信号进行频率补偿,并分别采用并联谐振回路、三次阶梯网络和高通滤波器峰化技术设计了三种前均衡0.35μm CMOS光电集成接收机.其中,光电探测器选用面积为40μm×40μm的叉指型双光电二极管结构,实验测得该二极管的频率响应带宽为1.1GHz,结电容为0.95pF.对接收机的模拟结果表明:采用三次阶梯网络峰化技术的前均衡方案可有效提高光接收机的灵敏度和速度,并可实现灵敏度为-14dBm,3dB带宽为2GHz,BER为10-12的0.35μm CMOS光电集成接收机.     

高速12路并行CMOS单片光电集成接收机设计与实现

设计并实现了一个高速12路并行CMOS单片光电集成接收机.其每一路都包括一个光探测器、一个跨阻放大器以及后续放大电路.双光电二极管(DPD)结构可以提高接收机速度,但同时降低了响应度.在跨阻放大器电路中采用有源电感来展宽-3dB带宽.通过无锡上华(CSMC)0.6μm CMOS工艺流片并对芯片进行了测试.测试结果显示该接收机单路传输比特率可达0.8～1.4 Gb/s,总的12路可传输15Gb/s数据.     

前均衡CMOS光电集成接收机概念的提出和模拟

提出了一种解决CMOS光电集成接收机灵敏度和速度问题的新方法--前均衡法,即在接收放大电路的前端对传输信号进行频率补偿,并分别采用并联谐振回路、三次阶梯网络和高通滤波器峰化技术设计了三种前均衡0.35μm CMOS光电集成接收机.其中,光电探测器选用面积为40μm×40μm的叉指型双光电二极管结构,实验测得该二极管的频率响应带宽为1.1GHz,结电容为0.95pF.对接收机的模拟结果表明:采用三次阶梯网络峰化技术的前均衡方案可有效提高光接收机的灵敏度和速度,并可实现灵敏度为-14dBm,3dB带宽为2GHz,BER为10-12的0.35μm CMOS光电集成接收机.     

CMOS兼容光电单片接收机的模拟与设计

设计了与CMOS工艺兼容的光电单片接收机电路,其中包括光电探测器、前置放大器和主放大器.它采用0.6μm CMOS工艺,可在自备的高阻外延片上使用MPW(multi-project wafer)进行流水.其中光电探测器的工作波长为850nm,响应度为0.2A/W,接收灵敏度为-16dBm,带宽为800MHz,因此适用于VSR(very short reach)系统.前置放大器采用电流模反馈放大器,主放大器输出为LVDS(low voltage differential signals)电平.通过器件模拟与电路模拟统一的方法将光电探测器与接收机放大电路进行统一模拟,分析了电路的限制因素,并提出了相应的改进方法.     

MS/RF CMOS工艺兼容的光电探测器

为实现光纤通信系统中的单片光电集成,采用工业标准工艺设计了硅基光电探测器,讨论了光电探测器的机理,提出了五种新的探测器结构,并采用TSMC 0.18μm MS/RF CMOS工艺进行了流片.利用半导体测试仪对芯片进行了测试,包括探测器的暗电流、响应度和结电容,并分析了深n阱、浅沟槽隔离等工艺步骤对探测器参数的影响.结果表明,利用标准MS/RF CMOS工艺实现的光电探测器具有良好的特性.     

高灵敏度CMOS光电集成接收机设计

设计了一个由调节型级联跨阻抗放大器(TIA)和双光电二极管(DPD)构成的CMOS光电集成(OEIC)接收机.具体分析了这个光电集成接收机的噪声和灵敏度及其相互关系.接收机中的噪声主要是电路中电阻的热噪声和MOS器件的闪烁噪声.提出了优化接收机灵敏度的方法.通过低成本的CSMC 0.6μm CMOS工艺流片并对芯片进行了测试.从测试眼图可知,该CMOS光电集成接收机可工作在1.25GB/s的传输速率下,灵敏度为-12dBm.     

A monolithic, standard CMOS, fully differential optical receiver with an integrated MSM photodetector

This paper presents a realization of a silicon-based standard CMOS, fully differential optoelectronic inte grated receiver based on a metal-semiconductor-metal light detector (MSM photodetector). In the optical receiver, two MSM photodetectors are integrated to convert the incident light signal into a pair of fully differential photo generated currents. The optoelectronic integrated receiver was designed and implemented in a chartered 0.35 μm, 3.3 V standard CMOS process. For 850 nm wavelength, it achieves a 1 GHz 3 dB bandwidth due to the MSM pho todetector's low capacitance and high intrinsic bandwidth. In addition, it has a transimpedance gain of 98.75 dBΩ, and an equivalent input integrated referred noise current of 283 nA from 1 Hz up to -3 dB frequency.     

A fully integrated 900-MHz CMOS wireless receiver with on-chip RF and IF filters and 79-dB image rejection

A monolithic 900-MHz CMOS wireless receiver with on-chip RF and IF filters and a fully integrated fractional-N synthesizer is presented. Implemented in a standard 0.5-/spl mu/m CMOS process and without any off-chip component, the complete receiver has a measured image rejection of 79 dB, a sensitivity of -90 dBm, an IIP3 of -24 dBm, and a noise figure of 22 dB with a power of 227 mW and a chip area of 5.7 mm/sup 2/. The synthesizer achieves a phase noise of -118 dBc/Hz at 600 kHz offset and a settling time of less than 150 /spl mu/s.     

A 3.1 GHz–8.0 GHz Single-Chip Transceiver for MB-OFDM UWB in 0.18-$mu$ m CMOS Process

This paper presents the design and integration of a fully-integrated dual-conversion zero-IF2 CMOS transceiver for 9-band MB-OFDM UWB systems from 3.1 GHz to 8.0 GHz. The transceiver integrates all building blocks including a variable-gain wideband LNA, a single combined mixer for both RF down-conversion in RX and up-conversion in TX, a fast-settling frequency synthesizer, and IQ ADCs and DACs. Fabricated in a standard 0.18- mum CMOS process, the receiver measures maximum S11 of - 13 dB, maximum NF of 8.25 dB, in-band IIP3 of better than -13.7 dBm, and variable gain from 25.3 to 84.0 dB. IQ path gain and phase mismatches of the receiver chain are measured to be 0.8 dB and 4 ^deg, respectively. The transmitter achieves a minimum output P-1 dB of -8.2 dBm, sideband rejection of better than -42.2 dBc, and LO leakage of smaller than - 46.5 dBc.     

一种用于卫星导航接收机的低噪声放大器设计

设计了一种可用于多模式卫星导航接收机的射频前端低噪声放大器,设计电路可在1.13～1.95 GHz工作,兼容了GPS,北斗及GLONOSS导航系统的工作频段。电路采用0.18 μm CMOS工艺实现。仿真结果表明,频带内S11和S22均在-10 dB以下,功率增益＞10 dB,带内最小噪声系数可达到2.2 dB,输出1 dB压缩点为-5.585 dBm,在1.8 V电源电压下,主体电路消耗12 mA电流。因此,该低频噪声放大器模块可满足当前各种导航系统的工作要求。     

用于IEEE802．11b／g WLAN直接下变频接收机的射频前端设计

介绍了一种应用于IEEE802．11b／g无线局域网接收机射频前端的设计。基于直接下变频的系统架构。接收机集成了低噪声放大器、I／Q下变频器、去直流偏移滤波器、基带放大器和信道选择滤波器。电路采用TSMC0．18μm CMOS工艺设计,工作在2．4GHz ISM（工业、科学和医疗）频段,实现的低噪声放大器噪声系数为0．84dB,增益为16dB,S11低于-15dB,功耗为13mW;I／Q下变频器电压增益为2dB,输入1dB压缩点为-1 dBm,噪声系数为13dB,功耗低于10mw。整个接收机射频前端仿真得到的噪声系数为3．5dB,IIP3为-8dBm,IP2大于30dBm,电压增益为31dB,功耗为32mW。     

A CMOS passive mixer with low flicker noise for low-power direct-conversion receiver

A CMOS passive mixer is designed to mitigate the critical flicker noise problem that is frequently encountered in constituting direct-conversion receivers. With a unique single-balanced passive mixer design, the resulted direct-conversion receiver achieves an ultralow flicker-noise corner of 45 kHz, with 6 dB more gain and much lower power and area consumption than the double-balanced counterpart. CMOS switches with a unique bias-shifting network to track the LO DC offset are devised to reduce the second-order intermodulation. Consequently, the mixer's IIP2 has been greatly enhanced by almost 21 dB from a traditional single-balanced passive mixer. An insertion compensation method is also implemented for effective dc offset cancellation. Fabricated in 0.18 /spl mu/m CMOS and measured at 5 GHz, this passive mixer obtains 3 dB conversion gain, 39 dBm IIP2, and 5 dBm IIP3 with LO driving at 0 dBm. When the proposed mixer is integrated in a direct-conversion receiver, the receiver achieves 29 dB overall gain and 5.3 dB noise figure.     

A 5.2-GHz CMOS receiver with 62-dB image rejection

A 5.2-GHz CMOS receiver employs a double downconversion heterodyne architecture with a local oscillator frequency of 2.6 GHz and applies offset cancellation to the baseband amplifiers. Placing the image around the zero frequency, the receiver achieves an image rejection of 62 dB with no external components while minimizing the flicker noise upconversion in the first mixing operation. Realized in a 0.25-μm digital CMOS technology, the circuit exhibits a noise figure of 6.4 dB, an IP₃ of -15 dBm, and a voltage conversion gain of 43 dB, while draining 29 mW from a 2.5-V supply     

A 3.1-4.8 GHz CMOS receiver for MB-OFDM UWB

An integrated fully differential ultra-wideband CMOS receiver for 3.1-4.8 GHz MB-OFDM systems is presented. A gain controllable low noise amplifier and a merged quadrature mixer are integrated as the RF front-end. Five order Gm-C type low pass filters and VGAs are also integrated for both I and Q IF paths in the receiver. The ESD protected chip is fabricated in a Jazz 0.18 μm RF CMOS process and achieves a maximum total voltage gain of 65 dB, an AGC range of 45 dB with about 6 dB/step, an averaged total noise figure of 6.4 to 8.8 dB over 3 bands and an in-band lIP3 of-5.1 dBm. The receiver occupies 2.3 mm2 and consumes 110 mA from a 1.8 V supply including test buffers and a digital module.     

Millimeter-wave CMOS design

This paper describes the design and modeling of CMOS transistors, integrated passives, and circuit blocks at millimeter-wave (mm-wave) frequencies. The effects of parasitics on the high-frequency performance of 130-nm CMOS transistors are investigated, and a peak f/sub max/ of 135 GHz has been achieved with optimal device layout. The inductive quality factor (Q/sub L/) is proposed as a more representative metric for transmission lines, and for a standard CMOS back-end process, coplanar waveguide (CPW) lines are determined to possess a higher Q/sub L/ than microstrip lines. Techniques for accurate modeling of active and passive components at mm-wave frequencies are presented. The proposed methodology was used to design two wideband mm-wave CMOS amplifiers operating at 40 GHz and 60 GHz. The 40-GHz amplifier achieves a peak |S/sub 21/| = 19 dB, output P/sub 1dB/ = -0.9 dBm, IIP3 = -7.4 dBm, and consumes 24 mA from a 1.5-V supply. The 60-GHz amplifier achieves a peak |S/sub 21/| = 12 dB, output P/sub 1dB/ = +2.0 dBm, NF = 8.8 dB, and consumes 36 mA from a 1.5-V supply. The amplifiers were fabricated in a standard 130-nm 6-metal layer bulk-CMOS process, demonstrating that complex mm-wave circuits are possible in today's mainstream CMOS technologies.     

A CMOS RF front-end for a multistandard WLAN receiver

This letter describes the design and performance of a dual band tri-mode receiver front-end compliant with the IEEE 802.11a, b, and g standards. The receiver front-end was built in a 0.18-/spl mu/m CMOS process and achieves a noise figure of 4.7 dB/5.1 dB for the 2.4-GHz/5-GHz bands, respectively. The receiver front-end provides a dual gain mode of 5 dB/30 dB with an IIP3 of -1dBm for the low gain mode. The front-end draws 25 mA/27 mA from a 1.8-V supply for the 2.4-GHz/5-GHz bands, respectively.