一种全数字半速率鉴相器的设计

鉴相器是高速时钟数据恢复环路的关键电路,其性能的优劣直接影响了整个系统的工作。通过系统分析,提出了一种全数字半速率鉴相器设计方案,按照全定制设计流程采用SMIC 0.18μm CMOS混合信号工艺完成了电路的设计、仿真。结果表明该电路在2.5 Gb/s收发器电路中可以稳定可靠地工作。     

OKI(900)型手机信号发射电路中鉴相器的噪声仿真

采用全能OrCAD混合电路仿真Pspice A/D V9软件,对OKI（900）型手机信号发射电路中的鉴相器进行了噪声仿真。     

2.5 Gbps收发器中1∶2解复用电路的设计

在2.5 Gbps高速串行收发系统接收端中1到2解复用电路位对于降低内核工作速度,减轻设计压力,提高电路稳定性起着关键作用.本文描述了基于电流模式逻辑的解复用电路工作原理,按照全定制设计流程采用SMIC0.18um混合信号工艺完成了高速差分数据的1到2解复用,并采用SpectreVerilog进行了数模混合仿真,结果表明该电路在2.5 Gbps收发器电路中可以稳定可靠地工作.     

采用MCML的高速低功耗复接器的设计

复接器是现代光纤通信系统中将多路低速信号合并成一路高速信号从而实现高速数据传输的关键器件.考虑到低功耗和高速度的要求,可以将MOS电流模逻辑(MCML)电路结构用到复接器电路中.文中给出了利用MCML电路设计串行、并行和树型三种常用结构的4:1复接器(MUX)的设计和仿真方法.通过SMIC 0.25μm CMOS工艺对其进行的仿真结果表明,该设计可以在毫瓦级功耗下实现最高为4Gb/s的数据速率.     

2.488 Gbit/s时钟数据恢复电路的设计

利用Cadence集成电路设计软件,基于SMIC 0.18 μm 1P6M CMOS工艺,设计了一款2.488 Gbit/s三阶电荷泵锁相环型时钟数据恢复(CDR)电路.该CDR电路采用双环路结构实现,为了增加整个环路的捕获范围及减少锁定时间,在锁相环(PLL)的基础上增加了一个带参考时钟的辅助锁频环,由锁定检测环路实时监控频率误差实现双环路的切换.整个电路由鉴相器、鉴频鉴相器、电荷泵、环路滤波器和压控振荡器组成.后仿真结果表明,系统电源电压为1.8V,在2.488 Gbit/s速率的非归零(NRZ)码输入数据下,恢复数据的抖动峰值为14.6 ps,锁定时间为1.5μs,功耗为60 mW,核心版图面积为566 μm×448μm.     

2.5Gbps收发器中1:2解复用电路的设计

在2.5 Gbps高速串行收发系统接收端中1到2解复用电路位对于降低内核工作速度,减轻设计压力,提高电路稳定性起着关键作用。本文描述了基于电流模式逻辑的解复用电路工作原理,按照全定制设计流程采用SMIC0.18um混合信号工艺完成了高速差分数据的1到2解复用,并采用SpectreVerilog进行了数模混合仿真,结果表明该电路在2.5 Gbps收发器电路中可以稳定可靠地工作。     

基于差分编码技术的12.5 Gbit/s高速SerDes发射机

研究并设计了一种基于差分编码技术的12.5 Gbit/s高速SerDes发射机。该电路由并串转换模块、去加重控制模块和驱动模块组成。驱动模块采用电流模逻辑异或门结构,动态负载的加入可以在降低功耗的同时实现与传输线的阻抗匹配。首次提出在并串转换模块中加入差分编码电路的解决方案,以保证原码输出,从而使数据在发射机内完成差分编解码的过程。后仿真结果表明,发射机数据传输速度达到12.5 Gbit/s。此时发射机整体功耗为39 mW,输出总抖动为0.05 UI,远小于JESD204B标准所要求的0.3 UI。     

一种新型的高速时钟数据恢复电路的设计和验证

针对高速(Gbit/s)串行数据通信应用,提出了一种混合结构的高速时钟数据恢复电路。该电路结构结合鉴频器和半速率二进制鉴相器,实现了频率锁定环路和相位恢复环路的同时工作。和传统的双环路结构相比,在功耗和面积可比拟的前提下,该结构系统的复杂度低、响应速度快。电路采用1.8 V,0.18μm CMOS工艺流片验证,测试结果显示在2 Gbit/s伪随机数序列输入情况下,电路能正确恢复出时钟和数据。芯片面积约0.5 mm~2,时钟数据恢复部分功耗为53.6 mW,输出驱动电路功耗约64.5 mW,恢复出的时钟抖动峰峰值为45 ps,均方根抖动为9.636 ps。     

一种基于SCL结构的高精度差分型PFD的设计

介绍一种基于场效应管源级耦合逻辑(SCL)结构的高精度差分型鉴频鉴相器(PFD)的设计,包括构成PFD的SCL结构基本单元--SCL结构D触发器、与非门、倒相器和缓冲单元.仿真实验结果表明,该PFD不仅能够减小死区范围,提高鉴相精度到50 ps,而且具有速度快、功耗低(仅47 mW)的特点,在低抖动锁相环路设计中有着广泛的应用.     

一种新型高精度DLL鉴相器设计

 本文从研究静态相位误差对DLL(Delay-Locked Loop)环路的影响入手,基于Hogge和Alexander结构鉴相器,设计了一款用于30相500MHz DLL的新型高精度鉴相器.与传统的线性鉴相器和二进制鉴相器相比,文中提出的新型鉴相器电路既具有理想线性鉴相器的特点,又解决了电荷泵开启死区的问题,消除了电流舵结构的电荷泵因电流失配带来的静态相位误差.对该鉴相器电路进行0.13μm CMOS工艺下的版图实现,版图之后的仿真结果显示:该鉴相器能正确鉴别1ps以上的相位延迟差,鉴相的精度高达0.18°,完全满足设计要求.     

一种适用于NRZ数据的时钟数据恢复电路

提出了一种基于传统电荷泵锁相环结构的时钟数据恢复电路.采用一种适用于NRZ数据的新型鉴频鉴相器电路,以克服传统鉴频鉴相器在恢复NRZ信号时出现错误脉冲的问题,从而准确地恢复出NRZ数据.同时,对其他电路也采用优化的结构,以提高时钟数据恢复电路的性能.设计的电路可在1.1 V超低电压下工作,适合RF ID等需要低电压、低功耗的系统使用.     

A 200-Mbps/spl sim/2-Gbps continuous-rate clock-and-data-recovery circuit

A 200-Mbps/spl sim/2-Gbps continuous-rate clock-and-data-recovery (CDR) circuit using half-rate clocking is presented. To detect the data with wide-range bit rates, a frequency tracing circuit (FTC) is used to aid the frequency acquisition. A wide-range and low gain voltage-controlled oscillator (VCO) is also presented by using analog and digital controlled mechanisms. A two-level bang-bang phase detector is utilized to improve the jitter performance and speed up the locking process. This CDR circuit has been realized in a 2P4M 0.35-/spl mu/m CMOS process. The experimental results show that this CDR circuit with the proposed FTC can receive 2/sup 31/-1 pseudorandom bit stream when the bit rate ranges from 200 Mbps to 2 Gbps without the harmonic-locking issue. All measured bit error rates are below 10/sup -12/. The measured root-mean-square and peak-to-peak jitters are 5.86 ps and 41.8 ps, respectively, at 2 Gbps.     

A 1.7 Gbps DLL‐Based Clock Data Recovery for a Serial Display Interface in 0.35‐μm CMOS

This paper presents a delay‐locked‐loop–based clock and data recovery (CDR) circuit design with a nB(n+2)B data formatting scheme for a high‐speed serial display interface. The nB(n+2)B data is formatted by inserting a ‘01’ clock information pattern in every piece of N‐bit data. The proposed CDR recovers clock and data in 1:10 demultiplexed form without an external reference clock. To validate the feasibility of the scheme, a 1.7‐Gbps CDR based on the proposed scheme is designed, simulated, and fabricated. Input data patterns were formatted as 10B12B for a high‐performance display interface. The proposed CDR consumes approximately 8 mA under a 3.3‐V power supply using a 0.35‐μm CMOS process and the measured peak‐to‐peak jitter of the recovered clock is 44 ps.     

InP DHBT-Based Monolithically Integrated CDR/DEMUX IC Operating at 80 Gbit/s

In this paper, a monolithically integrated clock and data recovery (CDR) circuit with 1:2 demultiplexer (DEMUX), which is intended for use in 80 Gbit/s optical fiber links, is presented. The integrated circuit (IC) is manufactured using an in-house InP double heterostructure bipolar transistor (DHBT) technology, exhibiting cut-off frequency values of more than 220 GHz for both$f_T$and$f_max $. The CDR circuit in the topology of a phase-locked loop (PLL) is mainly composed of a half-rate linear phase detector including a 1:2 demultiplexer (DEMUX), a loop filter, and a voltage-controlled oscillator (VCO). Hence, the corresponding architecture of each of these components as well as the applied circuit design technique are extensively addressed. Concerning the performance achieved by the CDR/DEMUX IC, the recovered and demultiplexed 40 Gbit/s data from an 80 Gbit/s input signal feature clear eye opening with a signal swing as high as 600$hboxmV_ pp$. The extracted 40 GHz clock signal shows a phase noise as low as$- hbox98~dBc/hboxHz$at 100 kHz offset frequency. The corresponding rms jitter amounts to 0.37 ps while the peak-to-peak jitter is as low as 1.66 ps. At a single supply voltage of$-hbox4.8~V$, the power consumption of the full CDR/DEMUX IC amounts to 1.65 W. To the authors' best knowledge, this work demonstrates the first CDR circuit at the achieved data rate, regardless of all the competing semiconductor technologies.     

Reduction of mutual coupling and cross-polarization of a MIMO/diversity antenna using a string of H-shaped DGS

In this article, a simple string of H-shaped defected ground structure (DGS) is used to reduce the mutual coupling and cross-polarization of a MIMO antenna. A MIMO antenna has been designed using two identical square patches to operate at the frequency of 2.4 GHz. The proposed DGS decreases the direct coupling path among the closely spaced (edge to edge gap 0.038 λ₀) patches and thereby reduces the mutual coupling and cross-polarization by 46 dB and 11 dB respectively. To study the amount of mutual coupling is decoupled; a new term namely, coupling to decoupling ratio (CDR) has been defined. A mathematical model is developed using multiple polynomial regression analysis techniques to observe the dependency of CDR as a function of frequency and inter-element spacing. Also, an equivalent circuit of the DGS is constructed and validated. Diversity performance of this MIMO antenna is presented through Envelope Correlation Coefficient (ECC) and Mean Effective Gain (MEG) ratio and well acceptable values of 0.0002 and 0.03 dB are obtained respectively. A prototype is fabricated and measured. The experimental results show good agreement with that of the simulated results. Maximum peak gain of 2dBi and radiation efficiency of 74% also proves the practicality of this design.     

A multibitrate burst-mode CDR circuit with bit-rate discriminationfunction from 52 to 1244 Mb/s

We fabricate and assess a clock and data recovery (CDR) circuit with a bit-rate discrimination (BRD) function that can receive burst-mode signals containing packets of different bit rates. The clock recovery circuit in the CDR circuit consists of gated oscillators (GOs) for handling the burst-mode signals, whose bit rates vary with each packet. Moreover, we improve the performance of the clock recovery circuit based on GOs against the bit rate unevenness around each bit rate. By combining an agile clock recovery circuit and a digital BRD circuit, the CDR circuit can handle multiplexed bit rates. Tests show that the circuit offers excellent performance for the multiplexed bit rates of nonreturn-to-zero 52, 155, 622, and 1244 Mb/s     

A 10-Gb/s data-pattern independent clock and data recovery circuit with a two-mode phase comparator

A clock and data recovery (CDR) circuit with a novel two-mode phase comparator is proposed. The 10-Gb/s CDR integrated circuit (IC) operates both for consecutive identical digits (CID) and data transition density variations. This advance is achieved through the use of our novel two-mode phase comparator, which enables us to determine an optimal phase-locked loop parameter for various data patterns. Experimental results show that the jitter generation of the CDR IC is less than 7 pspp for a 2/sup 7/-1 pseudorandom bit sequence with up to 1024 CIDs. The results also show that the jitter transfer and jitter tolerance are unaffected by data transition density factors of between 1/8 and 1/2.     

A 39-to-45-Gbit/s multi-data-rate clock and data recovery circuit with a robust lock detector

We describe a 40-Gbit/s-class clock and data recovery (CDR) circuit with an extremely wide pull-in range. A Darlington-type voltage-controlled oscillator (VCO) is newly designed to cover the STM-256/OC-768 full-rate-clock frequencies with a wide frequency margin. We also describe a new lock detector using an exclusive-NOR gate. The CDR IC was fabricated using InP/InGaAs HBTs. Error-free operation and wide eye opening were confirmed for 40-, 43-, and 45-Gbit/s PRBS with a word length of 2/sup 31/ - 1. We attached a frequency search and phase control (FSPC) circuit to the chip as a new frequency acquisition aid, and this allows the CDR circuit to pull in throughout a 39-45-Gbit/s range. The peak-to-peak and rms jitter of the recovered clock were 3.6 and 0.48 ps, respectively.