用光学制版设备制作1μm光掩模版

本文研究了用常规光学制版设备制作微细线条光掩模的加工技术,分析了精缩机,初缩版(原版)、化学处理、工艺环境在1μm光掩模版制作中的作用和要求。研制结果表明,采用反差大、过渡区小的初缩版,在严格聚焦的情况下进行分步精缩制版,精确控制显影和腐蚀时间,就能够制作出1μm条宽的光掩模版。     

对一台光栅扫描电子束曝光机制作掩模版质量的分析

本文在成熟使用电子束曝光机制作各种掩模版的基础上,针对评价掩模版质量的三大因素:图形尺寸精度、图形套准精度、芯片合格率逐一详细分析,以研究探讨如何应用电子束曝光机制作高质量的掩模版。     

国外电子束曝光设备的新进展

<正> 一、前言从六十年代末以来,电子束曝光设备在技术上的进展是十分显著的。由于电子束曝光设备具有高分辨率、高精度和使用灵活的特点,在集成电路的制造工艺中,主要用于制版(1×掩模版、10×和5×中间版)和在硅片上直接扫描制作电路图形。目前,电子束曝光设备已经成为大规模集成电路和超大规模集成电路     

掩模版复印工艺图形畸变分析与改进

批量化、低成本的掩模版复印工艺常被用于LED领域。在微米级图形的掩模版复印工艺中,受玻璃基板平面度的影响,光学衍射效应会导致图形发生畸变。为消弭复印工艺中的图形畸变,从光学衍射理论展开分析,提出通过调整光刻曝光剂量和光刻胶层厚度来提升掩模版复印工艺水平的方法。实验实现了4μm圆形图形掩模版的复印制作,结果表明该方法可以显著提升微米级图形的掩模版复印工艺水平,降低掩模版的制作成本。     

TFT阵列工艺简化

三星电子成功开发了3套掩模版TFT阵列工艺技术。一般TFT阵列工艺采用5或4套掩模版技术制作TFT阵列，3套掩模版工艺与4套掩模版工艺相比较，缩短工序，降低生产成本，生产能力提高20％，将增强企业的竞争力。     

一种掩模版制版用夹具装置的研制

介绍了一种掩模版制版用夹具装置,该装置具有准确的定位功能,能够自动补偿片厚误差,可进行真空复印使母掩模版与子掩模版紧密贴附,操作方便等特点。     

电子束曝光机制作分离掩模版的套准精度

一、前言电子束曝光机制作的高精度分离掩模版,精度高。要检查一套版之间的相对套准精度,往往比较困难。若用掩模版比较仪测量,只能测量相对精度,且精度较低,要测到±0.5μm的相对误差,已属不易。采用光刻工艺来检验掩模版的相对套准精度,尽管和器件生产工艺相容好,但测试周期长;而且由于光刻、腐蚀等工艺过程要带来相当可观的精度损失。因此作为一种工艺考核是可以的,而作为掩模版的套准精度就不合适了。     

国外图形发生器发展概况

一、前言随着半导体集成电路由大规模集成向超大规模集成化方向的飞速发展,电路图形日趋复杂,线条已进入亚微米领域,对掩模版的精度要求亦越来越高。因此,制作高质量的掩模版是发展现代集成电路工业的关键步骤之一。作为主要制版设备的图形发生器,其所处的重要地位是不言而喻的。     

亚半微米铬掩模版制作技术研究

介绍了用LeicaVB5电子束曝光系统在涂敷有PMMA电子束抗蚀剂的4英寸铬板上,通过扫描曝光、湿法显影、干法刻蚀等手段制作亚微米、亚半微米铬掩模版的工艺技术。     

采用PMMA LB膜作为电子束抗蚀层进行100mm高分辨率铬掩模版的制作研究

在发展流动亚相法制备高粘度聚合物分子单层膜装置的基础上，研究制备大面积，高质量的ＰＭＭＡ ＬＢ膜抗蚀层，并用于１００ｍｍ Ｃｒ掩模版的电子束光刻制造技术中，采用现行标准的湿法工艺获得了分辨率为０．５μｍ，特征线宽为０．３８μｍ的高分辨率１００ｍｍ铬掩模版，为深亚微米掩模版制造的研究探索了一条新路。     

用于纳米器件的电子束与光学混合光刻技术

成功开发出了一种可用于纳米结构及器件制作的电子束与光学光刻的混合光刻工艺。通过两步光刻工艺,在栅结构层上采用大小图形数据分离的方法,使用光学光刻形成大尺寸栅引出电极结构,利用电子束直写形成纳米尺寸栅结构,并通过图形转移工艺解决两次光刻定义的栅结构的叠加问题。此混合光刻工艺技术可以解决纳米电子束直写光刻技术效率较低的问题,同时避免了电子束进行大面积、高密度图形曝光时产生严重邻近效应影响的问题。这项工艺技术已经应用于先进MOS器件的研发,并且成功制备出具有良好电学特性、最小栅长为26 nm的器件。     

光学和电子束曝光系统之间的匹配与混合光刻技术

介绍如何实现光学和电子束曝光系统之间的匹配和混合光刻的技术，包括：(1）光学曝光系统与电子束曝光系统的匹配技术；(2）投影光刻和JBX-5000LS混合曝光技术；(3）接触式光刻机和JBX-5000LS混合曝光技术；(4）大小束流混合曝光技术或大小光阑混合曝光技术；(5）电子束与光学曝光系统混合光刻对准标记制作技术. 该技术已成功地应用于纳米器件和集成电路的研制工作，实现了20nm线条曝光，研制成功了27nm CMOS器件；进行了50nm单电子器件的演试；并广泛地用于100nm化合物器件和其他微/纳米结构的制造.     

第二代接近式X射线光刻技术

介绍了第二代PXL的原理和影响光刻分辨率的关键因素,当第二代PXL工艺因子为0.8时,对于50 nm及35 nm节点分辨率,掩模与硅片的间距可以分别达到10μm和5μm,表明第二代PXL具有很大的工艺宽容度;分析了纳米X射线掩模的具体结构、制作工艺和成本,相对于其竞争对手,在100 nm节点及其以下,X射线掩模的制造难度和成本是比较低的,而且随着电子束直写X射线掩模能力的进一步提高,X射线掩模更具优势;对几种常用的X射线光刻胶性能进行了分析,高性能的X射线光刻胶的研发不会成为PXL发展的障碍;对步进光刻机和X射线光源进行了论述,X射线点光源的研究进展对于第二代PXL的发展至关重要;最后介绍了第二代接近式X射线光刻的研究现状,尽管PXL的工业基础比起其它下一代光刻来说要好得多,但是比起光学光刻还差得很远,第二代PXL是否真正为硅基超大规模集成电路生产所接受目前还不得而知。     

Optical proximity correction: Mask pattern-generation challenges

The requirements imposed by optical proximity correction (OPC) on mask making, i.e. pattern generation, are addressed. Dry etching of MoSi is proposed to deal with the need for improved resolution. E-beam proximity correction (EPC) is used for more accurate linewidth control. An appropriate pre-correction fracturing technique is presented. A MoSi based embedded phase shift mask (5X) has been produced with a critical dimension of 0.3 μm using OPC corrected data. Highly accurate linewidth control was achieved by the reduction of the e-beam proximity effect and linearity errors to less than 3%. The effect of OPC and EPC on mask making throughput are discussed. An alternative OPC strategy is suggested that is more compatible with exposure grid requirements.     

Evolution of T-shaped gate lithography for compound semiconductors field-effect transistors

T-shaped gate formation is a major processing step in the fabrication of high-performance FET-based III-V devices. Traditional bilayer or trilayer E-beam lithography methods using PMMA/(PMMA&PMAA) copolymers are high-cost options which also lack the required critical dimension control for manufacturing. Lithography methods that use only a single layer of PMMA for the formation of T-shaped gate stem, and routine I-line resist lithography for the tee-top, i.e., hybrid T-shaped gates, have been developed and extensively used in manufacturing. This approach has also been extended to the fabrication of deep submicron T-shaped gates using all I-line optical lithography. Both chemical shrinks and chromeless phase-shift resolution enhancement techniques have been investigated.     

Does short wavelength lithography process degrade the integrity of thin gate oxide?

This paper presents the results of investigation on integrity of X-ray/E-beam irradiated thin gate oxides. A large increase of gate oxide leakage current is observed after irradiation on thin gate oxide under X-ray/E-beam lithography conditions. This radiation-induced leakage current (RILL) can be removed by a thermal annealing at 400°C and above, without adverse effect to the oxide integrity. In addition, it is found that ionizing exposures do not significantly affect the breakdown and quasi-breakdown characteristics in ultra-thin oxide.     

Fabrication of 0.15-μm Γ-Shaped Gate In0.52Al0.48As/In0.6Ga0.4As Metamorphic HEMTs Using DUV Lithography and Tilt Dry-Etching Technique

An In_0.52Al_0.48As/In_0.6Ga_0.4 As metamorphic high-electron mobility transistor (MHEMT) with 0.15-mum Gamma-shaped gate using deep ultraviolet lithography and tilt dry-etching technique is demonstrated. The developed submicrometer gate technology is simple and of low cost as compared to the conventional E-beam lithography or other hybrid techniques. The gate length is controllable by adjusting the tilt angle during the dry-etching process. The fabricated 0.15-mum In_0.52Al_0.48As/In_0.6Ga_0.4As MHEMT using this novel technique shows a saturated drain-source current of 680 mA/mm and a transconductance of 728 mS/mm. The f_T and f_max of the MHEMT are 130 and 180 GHz, respectively. The developed technique is a promising low-cost alternative to the conventional submicrometer E-beam gate technology used for the fabrication for GaAs MHEMTs and monolithic microwave integrated circuits     

A simplified fully implanted bipolar VLSI technology

An implanted n-p-n bipolar transistor structure named Isoplanar Z II (currently, being marketed as FAST-Z technology) with reduced process and masking steps is described. The simplification is achieved by employing self-aligned-transistor (SAT) masking, ion-implantation techniques to provide impurity doping, and using one common annealing cycle for collector, base, and emitter implantations. The device structure reduces design constraints through use of self-aligned field implantation and SAT mask for contact window definition. Submicrometer emitter widths are obtained by step and repeat optical photolithographic tool and two-dimensional effect on current gain due to sidewall injection is also studied. This technology is used to demonstrate 13-15 ns TAA, 4K static RAM and minimum delay of 250 ps per gate, gate array products.     

光学偏振器的量子逻辑功能

光子的水平偏振态和竖直偏振态作为两种基本量子状态。利用光学偏振器实现量子操作、最子异或操作的逻辑功能,分析偏振器在构造量子Ｔｏｆｆｏｌｉ门和量子Ｆｒｅｄｋｉｎ门中的作用。