基于泰勒级数展开的蜂窝TDOA定位新算法

在蜂窝移动通信系统中，TDOA（到达时间差）是目前最有发展潜力的无线定位技术。其中的泰勒级数展开算法因为具有精度高和顽健性强等特点在求解非线性定位方程组中得到了广泛的应用，但它对初始值有很强的依赖性。在此基础上，提出一种混合优化算法（HOA，hybrid optimizing algorithm）将泰勒级数展开算法和最速下降法有机结合，扬长避短，既继承了泰勒级数展开算法的精确性和顽健性，又具备最速下降法迭代前期收敛速率快，计算量小的优点。仿真结果表明HOA算法能显著提高传统的泰勒级数展开算法的定位精度和定位效率。     

基于最小二乘和泰勒级数展开的蜂窝定位新算法

蜂窝网络用户定位是蜂窝移动通信领域研究的热点技术之一.泰勒级数展开算法在求解非线性定位方程组中得到了广泛的应用,但是它对初始值具有很强的依赖性.本文提出了一种确定泰勒级数展开初始值的最小二乘估计算法,并对算法进行了仿真分析.仿真结果表明,本算法具有近似于基于真实值的泰勒级数展开算法的性能.     

基于泰勒级数下的均匀分布的空间相关性分析

通过对泰勒级数的展开,推导了均匀角能量分布的线性阵列和圆形阵列空间相关性的泰勒近似表达式。在对空间相关性的精确表达式的基础上,通过泰勒级数的展开,得到近似的相关性的表达式,在Matlab环境下进行仿真,对泰勒级数展开的近似算法与以往的近似算法进行了比较,并将基于泰勒级数展开的近似算法与精确算法进行比较,结果表明在一定条件下,泰勒近似算法与精确算法在很大范围内有很好的一致性。通过近似算法的分析可以得出,在一定范围内,增大天线间的距离以及角能量分布标准差可以减小天线阵列的空间相关性。     

基于泰勒级数展开的蜂窝TDOA定位算法

基于用户位置的应用已经成为移动数据业务的重要组成部分,使得蜂窝系统用户定位技术成为蜂窝移动通信领域的研究热点。泰勒级数展开算法因为具有精度高和顽健性强等特点而在求解非线性定位方程组中得到了广泛的应用,但它对初始值有很强的依赖性。本文使用最小二乘方法估计用户位置的初始值并使用泰勒级数展开算法确定用户坐标。通过对算法的仿真分析,结果表明本算法具有近似于基于真实值的泰勒级数展开算法的性能。     

双基合成孔径雷达二维频谱微增量算法研究

针对双基合成孔径雷达二维频谱难以精确获取的问题,提出基于斜距历程泰勒级数展开的双基二维频谱微增量算法.该算法在获取斜距历程低阶泰勒展开驻相点的基础上,通过求解此驻相点与斜距历程高阶泰勒展开驻相点之间的微增量来获取高阶展开驻相点的近似解,并以此为基础得到二维频谱.数学推导表明:级数反演(MSR)算法是微增量算法的一种低阶近似.微增量算法避免了求解高阶驻相点方程,运算量小.在仿真实验中,通过对比分析微增量算法与精确传递函数(ETF)算法、MSR算法得到的驻相点和二维参考频谱的聚焦效果,验证了微增量算法的有效性.     

基于FPGA的2底指数函数算法优化与实现

针对指数函数的常见硬件实现方法中存在的计算范围小、误差较大等问题，文中提出一种改进的多项式和查找表相结合的2底指数函数y=2^x的浮点硬件实现方法。优化算法采用区间划分的预处理方法将输入x压缩至(-1/512,1/512)后进行指数函数的泰勒级数展开，确保双精度浮点数格式下泰勒级数展开至x⁴项时精度达到10^-16,并通过优化中间数据存储策略，减少存储资源消耗。使用Verilog HDL在Xilinx公司的XC7K325T FPGA(Field Programmable Gate Array)上完成优化算法的硬件设计实现与性能测试。结果表明，在双精度浮点数所能表示的值域范围内，文中所设计的电路能够以较少的存储开销支持全定义域指数函数计算，计算精度不低于10^-16。     

基于APIT和TSE算法的混合定位方法

讨论了距离无关的近似三角形内点测试（APIT）算法和基于信号到达时间差（TDOA）的泰勒级数展开算法（TSE）的优缺点，并在此基础上提出了利用两者进行混合定位。仿真的结果表明该混合定位方法能有效提高定位精度。     

基于ADSP-21262的数字压限器设计

对数字压限器压限过程中计算音频信号有效值的加窗宽度进行了分析,提出了用分段法和泰勒级数展开相结合的算法计算压限系数,从而将压限误差控制在0.6 dB之内.基于压限算法的理论分析,利用通用DSP处理器ADSP-21262设计数字压限器,给出了硬件设计框图及其设计原理,测试表明样机性能与理论设计一致.     

LTE中PUSCH发射功率的一种优化方法

本文从LTE PUSCH的功率计算公式出发,研究指数运算和对数运算的泰勒级数展开算法,并研究在保持较高精度的情况下,最大限度地降低运算时间开销的算法实现方案,给出算法仿真性能,并对结果进行分析。     

LTE中PUSCH发射功率的一种优化方法

本文从LTE PUSCH的功率计算公式出发.研究指数运算和对数运算的泰勒级数展开算法,并研究在保持较高精度的情况下,最大限度地降低运算时间开销的算法实现方案,给出算法仿真性能,并对结果进行分析.     

固定延迟的流水线双精度浮点除法电路

除运算采用泰勒级数展开,用5级流水线结构,查找表大小缩小为2.5kB,并获得固定延迟.FPGA综合结果表明,与其他设计电路相比,面积减小了33%.     

Determining elements of lossy ladder networks

An algorithm for determining the Stieltjes continued-fraction expansion of driving-point function from its Taylor-series expansion has been suggested. This algorithm can be used to determine the elements of lossy ladder networks with advantage when the driving point function is represented in time domain by state variables.     

可配置非幂方分频器的全新设计方法

本文采用基于计数空间完全划分和周期插入控制计数过程方法设计了非幂方分频器,采用这种全新思路设计的非幂方分频器分频范围很宽,分频输出对后续分频支持好,非常适用于通讯接口中的波特率时钟设计.此外,这种设计思路对系统定时电路和节拍控制电路设计也有一定的借鉴意义.     

A New Multi-tanh-Based Non-linear Function Synthesiser

A new complementary metal-oxide-semiconductor transadmittance-mode with input voltage and output current, analogue non-linear odd-function synthesiser is presented. The proposed circuit is based on the assumption that a non-linear odd- function can be approximated by the summation of hyperbolic tangent (tanh) functions with different arguments. Each term of the tanh function expansion is realised by exploiting to advantage the inherent non-linearity of a current-controlled current-conveyor (CCCCII) (or an operational transconductance amplifier (OTA)) with a different bias current. The output currents of these CCCCIIs (OTAs) are weighted using the gains of current amplifiers. These weighted currents are algebraically added to form the required non-linear function. The proposed circuit is suitable for integration, can be easily extended to include higher order terms of the tanh-odd-function expansion and can be programmed to realise arbitrary hard non-linear odd-functions that cannot be easily realised using already existing techniques, based on the Taylor-series expansion, for synthesising non-linear functions. PSPICE simulation results, obtained from CCCCII-based realisations of selected hard non-linearities, demonstrating the functionality of the proposed circuit are included.     

幅度固定唯相位实现波束控制的功分器设计

针对传统阵列天线设计流程中功分器繁琐的设计过程, 基于满足-3 dB范围为0°~12°, -10 dB波束宽度为65°, 波束覆盖为65°, 中心频率为9.05 GHz的余割平方扩展波束赋形要求, 设计了一种幅度固定唯相位实现波束控制的新型串馈结构Gysel功分器.该功分器幅度为固定值, 此幅度分布满足余割平方赋形阵列天线幅度的分布特征, 在遗传算法计算出理想赋形激励后只需调整该功分器的输出相位值就能实现高拟合度的余割平方扩展波束赋形, 大为减少了传统设计中功分器所需的设计时间.     

Performance analysis of an FFH/BFSK linear-combining receiveragainst multitone jamming

A computationally efficient bit-error rate (BER) expression for a fast frequency-hopping binary frequency-shift-keying (FFH/BFSK) spread-spectrum system is derived based on Taylor-series expansion of the central differences. The FFH system employs a soft-decision linear-combining receiver against the worst-case band multitone jamming (MTJ) and additive white Gaussian noise. The analytical results are shown to match closely with the BER results based on simulation. This approach allows us to efficiently analyze the performance of the linear-combining receiver with higher diversity levels, which is otherwise mathematically intractable     

基于FPGA的任意数值分频器的设计

介绍了基于FPGA的任意分频系数的分频器的设计,该分频器能实现分频系数和占空比均可以调节的3类分频：整数分频、小数分频和分数分频。所有分频均通过VHDL语言进行了编译并且给出了仿真图。本设计中的分频器没有竞争冒险,可移植性强,占用的FPGA资源少。本设计在Altera公司的CycloneⅡ系列EP2C35型FPGA芯片中完全可实现,结果表明设计是正确和可行的。由于分频器应用非常广泛,故本设计具有很强的实用价值。     

A Radix-4 New Svobota-Tung Divider with Constant Timing Complexity for Prescaling

A new floating-point division architecture that complies with the IEEE 754-1985 standard is proposed in this paper. This architecture is based on the New Svoboda-Tung (NST) division algorithm and the radix-4 MROR (maximally redundant maximally recoded) signed digit number system. In NST division, the divisor and dividend must be prescaled. We summarize a general systematic method to accomplish the prescaling, and we also propose a hardware scheme such that the timing complexity is constant regardless of the bit length of the divisor. For the divider implementation, a new MROR signed digit adder with carry free characteristic is proposed for addition and subtraction, and this adder can improve the cycle time significantly. A 32-b/32-b radix-4 divider is thus designed in Verilog HDL; the simulation results show that this architecture is implementable using currently available libraries. The hardware complexity and performance of this divider is competitive with conventional SRT dividers.     

Robust Least Squares Constant Modulus Algorithm to Signal Steering Vector Mismatches

The linearly constrained least squares constant modulus algorithm (LSCMA) may suffer significant performance degradation and lack robustness in the presence of the slight mismatches between the actual and assumed signal steering vectors, which can cause the serious problem of desired signal cancellation. To account for the mismatches, we propose a doubly constrained robust LSCMA based on explicit modeling of uncertainty in the desired signal array response and data covariance matrix, which provides robustness against pointing errors and random perturbations in detector parameters. Our algorithm optimizes the worst-case performance by minimizing the output SINR while maintaining a distortionless response for the worst-case signal steering vector. The weight vector can be optimized by the partial Taylor-series expansion and Lagrange multiplier method, and the optimal value of the Lagrange multiplier is iteratively derived based on the known level of uncertainty in the signal DOA. The proposed implementation based on iterative minimization eliminates the covariance matrix inversion estimation at a comparable cost with that of the existing LSCMA. We present a theoretical analysis of our proposed algorithm in terms of convergence, SINR performance, array beampattern gain, and complexity cost in the presence of random steering vector mismatches. In contrast to the linearly constrained LSCMA, the proposed algorithm provides excellent robustness against the signal steering vector mismatches, yields improved signal capture performance, has superior performance on SINR improvement, and enhances the array system performance under random perturbations in sensor parameters. The on-line implementation and significant SINR enhancement support the practicability of the proposed algorithm. The numerical experiments have been carried out to demonstrate the superiority of the proposed algorithm on beampattern control and output SINR enhancement compared with linearly constrained LSCMA.     

A new SPICE subcircuit model of power p-i-n diode

A new modeling approach for the power p-i-n diode is proposed. The base region is represented with a two-port network, obtained by solving the ambipolar diffusion equation with the Laplace transform method, and by approximating the resulting transcendental functions in the s-domain with rational approximations. Two different networks have been obtained. The first one, based on Taylor-series approximation is shown to be a generalization of a two-port model already proposed in the literature for the nonquasi-static modeling of bipolar transistors. The second network representation is based on Pade' approximation and is shown to be more accurate than the Taylor-series approach, The obtained RLC networks are easily implemented in a PSPICE subcircuit which also takes into account the emitter recombination effects and the dynamic of the space-charge voltage build-up. Good agreement has been obtained by comparing the results of the proposed model with numerical device simulations