Semi-Analytical Modeling of Short-Channel Effects in Si and Ge Symmetrical Double-Gate MOSFETs

A simple analytical expression of the 2-D potential distribution along the channel of silicon symmetrical double-gate (DG) MOSFETs in weak inversion is derived. The analytical solution of the potential distribution is compared with the numerical solution of the 2-D Poisson's equation in terms of the channel length L, the silicon thickness t _Si, and the gate oxide thickness t _OX. The obtained results show that the analytical solution describes, with good accuracy, the potential distribution along the channel at different positions from the gate interfaces for well-designed devices when the ratio of L/t _Si is ges 2-3. Based on the 2-D extra potential induced in the silicon film due to short-channel effects (SCEs), a semi-analytical expression for the subthreshold drain current of short-channel devices is derived. From the obtained subthreshold characteristics, the extracted device parameters of the subthreshold slope, drain-induced barrier lowering, and threshold voltage are discussed. Application of the proposed model to devices with silicon replaced by germanium demonstrates that the germanium DG MOSFETs are more prone to SCEs.     

Semianalytical Modeling of Short-Channel Effects in Lightly Doped Silicon Trigate MOSFETs

A simple analytical expression of the 3-D potential distribution along the channel of lightly doped silicon trigate MOSFETs in weak inversion is derived, based on a perimeter-weighted approach of symmetric and asymmetric double-gate MOSFETs. The analytical solution is compared with the numerical solution of the 3-D Poisson's equation in the cases where the ratios of channel length/silicon thickness and channel length/channel width are ges 2. Good agreement is achieved at different positions within the channel. The perimeter-weighted approach fails at the corner regions of the silicon body; however, by using corner rounding and undoped channel to avoid corner effects in simulations, the agreement between model and simulation results is improved. By using the extra potential induced in the silicon film due to short-channel effects, the subthreshold drain current is determined in a semianalytical way, from which the subthreshold slope, the drain-induced barrier lowering, and the threshold voltage are extracted.     

Analytical modelling for the current-voltage characteristics of undoped or lightly-doped symmetric double-gate MOSFETs

An analytical drain current model for undoped (or lightly-doped) symmetric double-gate (DG) MOSFETs is presented. This model is based on the subthreshold leakage current in weak inversion due to diffusion of carriers from source to drain and an analytical expression for the drain current in strong inversion of long-channel DG MOSFETs, both including the short-channel effects. In the saturation region, the series resistance, the channel length modulation, the surface-roughness scattering and the saturation velocity effects were also considered. The proposed model has been validated by comparing the transfer and output characteristics with simulation and experimental results.     

全耗尽SOI MOSFETs阈值电压解析模型

提出了一种新的全耗尽SOI MOSFETs阈值电压二维解析模型.通过求解二维泊松方程得到器件有源层的二维电势分布函数,氧化层-硅界面处的电势最小值用于监测SOI MOSFETs的阈值电压.通过对不同栅长、栅氧厚度、硅膜厚度和沟道掺杂浓度的SOI MOSFETs的MEDICI模拟结果的比较,验证了该模型,并取得了很好的一致性.     

非掺杂对称双栅的基于完整表面电势的核心模型

通过求解Poisson方程自洽地得到了表面电势随沟道电压的变化关系,从而推出了非掺杂对称双栅MOSFET的一个基于表面势的模型.通过Pao-Sah积分得到了漏电流的表达式.该模型由一组表面势方程组成,解析形式的漏电流可以通过源端和漏端的电势得到.结果标明该模型在双栅MOSFET的所有工作区域都成立,而且不需要任何简化(如应用薄层电荷近似)和辅助拟合函数.对不同工作条件和不同尺寸器件的二维数值模拟与模型的比较进一步验证了提出模型的精度.     

Numerical and charge sheet models for thin-film SOI MOSFETs

Numerical charge sheet models applicable for all bias conditions are presented for the channel currents of long-channel SOI MOSFETs. From a comparison of the two models it is shown that the charge sheet analytic model accurately predicts the channel currents from weak to strong inversion regions. The results include analytic expressions for the drift and diffusion current components of individual channel currents, the front-gate and back-gate interaction parameter, and an analytic correlation between the surface potentials of the front and back channels when there is coupling between the two gates under nonthermal equilibrium conditions. The effect of SOI (silicon on insulator) film thickness on the drain current was investigated under different bias conditions for the back gate, and it was found that thin films are beneficial from the point of increased drain currents if the back channel is in depletion or inversion. It is also shown that, in addition to the charge coupling effects, dynamic interaction between the channels exists if the static current in one of the channels saturates     

考虑源漏隧穿的DG MOSFET弹道输运及其模拟

在经典弹道输运模型中引入源漏隧穿 (S/ D tunneling) ,采用 WKB方法计算载流子源漏隧穿几率 ,对薄硅层(硅层厚度为 1nm) DG(dual gate) MOSFETs的器件特性进行了模拟 .模拟结果表明当沟道长度为 10 nm时 ,源漏隧穿电流在关态电流中占 2 5 % ,在开态电流中占 5 % .随着沟道长度进一步减小 ,源漏隧穿比例进一步增大 .因此 ,模拟必须包括源漏隧穿 .     

A 2D compact model for lightly doped DG MOSFETs (P-DGFETs) including negative bias temperature instability (NBTI) and short channel effects (SCEs)

In this paper, a 2D compact model for potential and threshold voltage for lightly doped symmetrical double gate (DG) p-channel MOSFETs (PMOS) including negative bias temperature instability (NBTI) and short channel effects (SCEs) is presented. The model is dedicated to nano scale MOSFETs below 30 nm. In this model, both effects of interface state generation and hole-trapping are considered. Moreover, the effects of scaling down the oxide thickness and the channel thickness on NBTI are discussed. Our model is matched very well with numerical simulations obtained from COMSOL multi-physics at different drain voltages (V_d). A 4% shift in threshold voltage roll-off and 47% shift in drain induced barrier lowering (DIBL) is achieved at a gate length of 10 nm after 10 years of operation at a frequency of 1 GHz.     

Continuous analytic I-V model for surrounding-gate MOSFETs

We present a continuous analytic current-voltage (I-V) model for cylindrical undoped (lightly doped) surrounding gate (SGT) MOSFETs. It is based on the exact solution of the Poisson's equation, and the current continuity equation without the charge-sheet approximation, allowing the inversion charge distribution in the silicon film to be adequately described. It is valid for all the operation regions (linear, saturation, subthreshold) and traces the transition between them without fitting parameters, being ideal for the kernel of SGT MOSFETs compact models. We have demonstrated that the I-V characteristics obtained by this model agree with three-dimensional numerical simulations for all ranges of gate and drain voltages.     

The behavior of narrow-width SOI MOSFETs with MESA isolation

Narrow-width effects in thin-film silicon on insulator (SOI) MOSFETs with MESA isolation technology have been studied theoretically and experimentally. As the channel width of the MOSFET is scaled down, the gate control of the channel potential is enhanced. It leads to the suppression of drain current dependence on substrate bias and punchthrough effect in narrow-width devices. The variation of threshold voltage with the channel width is also studied and is found to have a strong dependence on thickness of silicon film, interface charges in the buried oxide and channel type of SOI MOSFETs     

Charge-based model for symmetric double-gate MOSFETs with inclusion of channel doping effect

This paper presents a unified charge-based model for symmetric double-gate (DG) MOSFETs with a wide range of channel doping concentrations. From one dimensional (1D) Poisson–Boltzmann equation in the DG MOSFET structure, an accurate inversion charge model is proposed, which predicts the inversion charge density precisely from weak inversion, through moderate inversion and finally to strong inversion region for both heavily doped and lightly doped condition. Based on that, the unified drain current model is developed from Pao-Sah’s dual integral. The unified terminal charge and trans-capacitance models are derived out from Ward and Dutton’s linear-charge-partition scheme. Extensive numerical simulations are performed on DG MOSFETs to verify the unified charge-based models and good agreements between them are obtained, proving the validity of the proposed model for further circuit simulation.     

Two-dimensional analytical modeling of fully depleted DMG SOI MOSFET and evidence for diminished SCEs

A two-dimensional (2-D) analytical model for the surface potential variation along the channel in fully depleted dual-material gate silicon-on-insulator MOSFETs is developed to investigate the short-channel effects (SCEs). Our model includes the effects of the source/drain and body doping concentrations, the lengths of the gate metals and their work functions, applied drain and substrate biases, the thickness of the gate and buried oxide and also the silicon thin film. We demonstrate that the surface potential in the channel region exhibits a step function that ensures the screening of the drain potential variation by the gate near the drain resulting in suppressed SCEs like the hot-carrier effect and drain-induced barrier-lowering (DIBL). The model is extended to find an expression for the threshold voltage in the submicrometer regime, which predicts a desirable "rollup" in the threshold voltage with decreasing channel lengths. The accuracy of the results obtained using our analytical model is verified using 2-D numerical simulations.     

Performance analysis of long Ge channel double gate (DG) p MOSFETs with high-k gate dielectrics based on carrier concentration formulation

In this paper, electrical behavior of symmetric double gate Ge channel MOSFETs with high-k dielectrics is reported on the basis of carrier concentration formalism. The model relies on the solution of Poisson-Boltzmann equations subject to suitable boundary conditions taking into account the effect of interface trap charge density (D_it) and the Pao-Sah’s current formulation considering field dependent hole mobility. It is continuous as it holds good for sub-threshold, weak and strong inversion regions of device operation. The proposed model has been employed to calculate the drain current of DG MOSFETs for different values of gate voltage and drain voltage along with various important device parameters such as transconductance, output conductance, and transconductance per unit drain current for a wide range of interface trap charge density, equivalent oxide thickness (EOT) and bias conditions. Moreover, most of the important device parameters are compared with their corresponding Si counter parts. Accuracy of the model has been verified by comparing analytical results with the numerical simulation data. A notable improvement of the drive current and transconductance for Ge devices is observed with reference to Si devices, particularly when D_it is small.     

An analytical compact model for Schottky-barrier double gate MOSFETs

An analytical and explicit compact model for undoped symmetrical silicon double gate MOSFETs (DGMOSFETs) with Schottky barrier (SB) source and drain is presented. The SB MOSFET can be studied as a traditional MOSFET where the doped source/drain regions have been replaced by a metal contact. Due to particular features of this new structure, the main transport mechanisms of these devices differ from those found in traditional MOSFETs. The model developed in this paper is based on a previously published DGMOSFET model which has been extended to include the characteristic tunneling transport mechanisms of SB MOSFET.The proposed model reproduces the well known ambipolar behavior found in SB MOSFET for a wide range of metal source and drain contacts specified through different values of their work function. The model has been validated with numerical data obtained by means of the 2D ATLAS simulator, where a SB DGMOSFET structure has been defined and characterized in order to obtain the transfer and output characteristics for several bias configurations. Devices with two channel lengths (2 μm and 3 μm) has been simulated and modeled.     

Threshold voltage model for deep-submicron fully depleted SOI MOSFETs with back gate substrate induced surface potential effects

A simple analytical threshold voltage model for short-channel fully depleted SOI MOSFETs has been derived. The model is based on the analytical solution of the two-dimensional potential distribution in the silicon film (front silicon), which is taken as the sum of the long-channel solution to the Poisson's equation and the short-channel solution to the Laplace equation, and the solution of the Poisson's equation in the silicon substrate (back silicon). The proposed model accounts for the effects of the back gate substrate induced surface potential at the buried oxide-substrate interface which contributed an additional 15–30% reduction in the threshold voltage for the devices used in this work. Conditions on the back gate supply voltage range are determined upon which the surface potential at the buried oxide-substrate interface is accumulated, depleted, or inverted. The short-channel associated drain induced barrier lowering effects are also included in the model. The model predications are in close agreement with PISCES simulation results. The equivalence between the present model and previously reported models is proven. The proposed model is suitable for use in circuit simulation tools such as Spice.     

A fuzzy-logic-based approach to accurate modeling of a double gate MOSFET for nanoelectronic circuit design

正The double gate(DG) silicon MOSFET with an extremely short-channel length has the appropriate features to constitute the devices for nanoscale circuit design.To develop a physical model for extremely scaled DG MOSFETs,the drain current in the channel must be accurately determined under the application of drain and gate voltages.However,modeling the transport mechanism forthe nanoscale structures requires the use of overkill methods and models in terms of their complexity and computation time(self-consistent,quantum computations,...). Therefore,new methods and techniques are required to overcome these constraints.In this paper,a new approach based on the fuzzy logic computation is proposed to investigate nanoscale DG MOSFETs.The proposed approach has been implemented in a device simulator to show the impact of the proposed approach on the nanoelectronic circuit design.The approach is general and thus is suitable for any type of nanoscale structure investigation problems in the nanotechnology industry.     

A 2-D Semi-Analytical Model of Double-Gate Tunnel Field-Effect Transistor Xu Huifang (许会芳), Dai Yuehua*(代月花), Li Ning(李宁), Xu JianBin(徐建斌)

文中提出了一种双栅隧穿场效应晶体管(DG TFET)的二维半解析模型。通过在栅绝缘层和沟道区引入两个矩形源,运用半解析法和特征函数展开法求解二维泊松方程,得到电势的二维半解析解。解的结果是一个特殊函数,为无穷级数表达式。基于电势模型,求出最短隧穿长度( )和平均电场( ),运用Kane模型得到漏极电流。新模型考虑了移动电荷对电势的影响以及漏源电压对隧穿参数 和 的影响。文中计算了不同漏源电压,不同硅膜厚度,栅介质层厚度和栅介质层常数下的表面势和漏极电流。结果表明,新模型与仿真结果吻合。这将有助于DG TFET的优化设计,同时,也加深了DG TFET器件对电路结构设计的规划。     

双栅和环栅MOSFET中短沟效应引起的阈值电压下降

基于电荷分享原理 ,推导了双栅和环栅 MOSFET短沟效应引起的阈值电压下降 ,分析了衬底掺杂浓度、栅氧化层厚度及硅膜厚度等因素对阈值电压下降的影响 ,并用数值模拟验证了理论结果 .这些研究结果对进一步开展纳米 CMOS新器件的研究有很好的参考价值和实际意义     

Partially depleted SOI MOSFETs under uniaxial tensile strain

The effects of tensile uniaxial strain on the DC performance of partially-depleted silicon-on-insulator n and p-channel MOSFETs as a function of orientation and gate length are reported. The drain current of the n-MOSFETs increases for both longitudinal and transverse strain orientations with respect to the current flow direction. In the n-MOSFET, longitudinal strain provides greater enhancement than transverse strain. In contrast, for p-MOSFETs, longitudinal strain decreases the current while transverse strain increases the drain current. The magnitude of the fractional change in drain current decreases as gate length is reduced from 20 to 0.35 /spl mu/m. These phenomena are consistent with those of bulk silicon MOSFETs and are shown to be qualitatively correlated with the piezoresistance coefficients of the Si inversion layer. Analysis of the linear drain current versus gate voltage characteristics shows that the threshold voltage is independent of strain while the change in drain current tracks with the change in effective electron and hole mobility. Closer examination shows that as the gate length is reduced from 20 to 0.35 /spl mu/m, the relative increase in low-field electron and hole mobility is constant for transverse strain and generally decreases with gate length for longitudinal strain.     

A charge sheet model for MOSFETs with an abrupt retrograde channel Part I. Drain current and body charge

Analytical solutions to drain current, depletion and inversion charges for MOSFETs with an ideally abrupt retrograde doping profile in the channel are derived based on the charge sheet model. The validity of the analytical solutions is confirmed by comparing the modeling results with simulation data obtained using numerical calculations; the modeling and simulation results are in excellent agreement. It is shown that the inclusion of an intrinsic surface layer in the channel causes a voltage shift in the drain current, in accordance with experimental observations. For the depletion charge, an analytical expression principally identical to that for the uniformly doped body case is found with a simple replacement of the surface potential, ψ_s, by the potential at the interface between the intrinsic surface layer and the doped substrate, ψ_ξ.