共查询到18条相似文献,搜索用时 78 毫秒
1.
提出了一种新的全耗尽SOI MOSFETs阈值电压二维解析模型.通过求解二维泊松方程得到器件有源层的二维电势分布函数,氧化层-硅界面处的电势最小值用于监测SOI MOSFETs的阈值电压.通过对不同栅长、栅氧厚度、硅膜厚度和沟道掺杂浓度的SOI MOSFETs的MEDICI模拟结果的比较,验证了该模型,并取得了很好的一致性. 相似文献
2.
通过准二维的方法,求出了全耗尽SOILDMOS晶体管沟道耗尽区电势分布的表达式,并建立了相应的阈值电压模型。将计算结果与二维半导体器件模拟软件MEDICI的模拟结果相比较,两者误差较小,证明了本模型的正确性。从模型中可以容易地分析阈值电压与沟道浓度、长度、SOI硅膜层厚度以及栅氧化层厚度的关系,并且发现ΔVth与背栅压的大小无关。 相似文献
3.
4.
5.
6.
7.
8.
异质栅非对称Halo SOI MOSFET 总被引:2,自引:1,他引:2
为了抑制异质栅SOI MOSFET的漏致势垒降低效应,在沟道源端一侧引入了高掺杂Halo结构.通过求解二维电势Poisson方程,为新结构器件建立了全耗尽条件下表面势和阈值电压解析模型,并对其性能改进情况进行了研究.结果表明,新结构器件比传统的异质栅SOI MOSFETs能更有效地抑制漏致势垒降低效应,并进一步提高载流子输运效率.新结构器件的漏致势垒降低效应随着Halo区掺杂浓度的增加而减弱,但随Halo区长度非单调变化.解析模型与数值模拟软件MEDICI所得结果高度吻合. 相似文献
9.
采用分解电势的方法求解二维泊松方程,建立了考虑电子准费米势的短沟道双栅MOSFET的二维表面势模型,并在其基础上导出了阈值电压、短沟道致阈值电压下降效应和漏极感应势垒降低效应的解析模型。研究了不同沟道长度、栅压和漏压情况下的沟道表面势,分析了沟道长度和硅膜厚度对短沟道效应的影响。研究结果表明,电子准费米势对开启后的器件漏端附近表面势有显著影响,新模型可弥补现有模型中漏端附近表面势误差较大的缺点;对于短沟道双栅MOSFET,适当减小硅膜厚度可抑制短沟道效应。 相似文献
10.
11.
Kajiwara K. Nakajima Y. Hanajiri T. Toyabe T. Sugano T. 《Electron Devices, IEEE Transactions on》2008,55(7):1702-1707
We characterized the distribution of trap states in silicon-on-insulator (SOI) layers in epitaxial layer transfer (ELTRAN) wafers and in low-dose separation by implanted oxygen (SIMOX) wafers. We measured the front- and back-gate characteristics of MOSFETs with SOI layers of different thicknesses. We used the current-Terman method to estimate the trap states at the gate oxide (GOX)/SOI interface and at the SOI/buried oxide (BOX) interface separately. As a result, we concluded that the high-density trap states in the SOI layers in SIMOX wafers cause a gate-voltage shift, which is attributed to the charged trap states only in the inversion layer. We also found that the trap states are distributed within about 30 nm from the SOI/BOX interface in the SOI layer in SIMOX wafers, which indicates that the distribution of trap states originates from the oxygen implantation that is peculiar to the SIMOX process. 相似文献
12.
A 2D model for the potential distribution in silicon film is derived for a symmetrical double gate MOSFET in weak inversion. This 2D potential distribution model is used to analytically derive an expression for the subthreshold slope and threshold voltage. A drain current model for lightly doped symmetrical DG MOSFETs is then presented by considering weak and strong inversion regions including short channel effects, series source to drain resistance and channel length modulation parameters. These derived models are compared with the simulation results of the SILVACO (Atlas) tool for different channel lengths and silicon film thicknesses. Lastly, the effect of the fixed oxide charge on the drain current model has been studied through simulation. It is observed that the obtained analytical models of symmetrical double gate MOSFETs are in good agreement with the simulated results for a channel length to silicon film thickness ratio greater than or equal to 2. 相似文献
13.
Noguchi M. Numata T. Mitani Y. Shino T. Kawanaka S. Oowaki Y. Toriumi A. 《Electron Device Letters, IEEE》2001,22(1):32-34
The dependence of threshold voltage on silicon-on-insulator (SOI) thickness is studied on fully-depleted SOI MOSFETs, and, for this purpose, back-gate oxide thickness and back gate voltage are varied. When the back gate oxide is thinner than the critical thickness dependent on the back gate voltage, the threshold voltage has a minimum in cases where the SOI film thickness is decreased, because of capacitive coupling between the SOI layer and the back gate. This fact suggests that threshold voltage fluctuations due to SOI thickness variations are reduced by controlling the back gate voltage and thinning the back gate oxide 相似文献
14.
An analytical model is proposed for calculating the potential drop in the silicon substrate for thin-film SOI MOSFETs. The model is verified by numerical simulation, and indicates that the substrate potential causes a nonlinear shift of the threshold voltage for varying back gate voltages. Although this shift is shown to be rather limited for SOI fabrication parameters, it will increase if thinner buried oxides are used in the future.<> 相似文献
15.
A physical model and a computer simulation program for nanoscale ballistic SOI MOSFETs are developed. The model includes transistor parameters such as the type and level of doping in the source and drain regions, gate length, Si and gate-oxide thicknesses, spacer length, gate-material work function, etc. Transistor performance is characterized in terms of transconductance, subthreshold slope, on- and off-state drain currents, gate–source overlap capacitance, etc. The software enables one to optimize the transistor parameters. 相似文献
16.
Classical modeling of fully inverted SOI MOSFET (FI MOSFET) has been performed. In FI MOSFETs, the top Si layer is thinner than the thickness of the inversion layer at the conducting state and so the depleted region in the top Si layer is completely eliminated. It was found that the gate electric field induces carriers in the channel more effectively in FI MOSFET than in the fully depleted SOI MOSFETs (FD MOSFET), so that the short channel effects can be suppressed significantly. 相似文献
17.
Xinnan Lin Chuguang Feng Shengdong Zhang Wai-Hung Ho Mansun Chan 《Solid-state electronics》2004,48(12):2315-2319
A simple process to fabricate double gate SOI MOSFET is proposed. The new device structure utilizes the bulk diffusion layer as the bottom gate. The active silicon film is formed by recrystallized amorphous silicon film using metal-induced-lateral-crystallization (MILC). While the active silicon film is not truly single crystal, the material and device characteristics show that the film is equivalent to single crystal SOI film with high defect density, like SOI wafers produced in early days. The fabricated double gate MOSFETs are characterized, which demonstrate excellent device characteristics with higher current drive and stronger immunity to short channel effects compared to the single gate devices. 相似文献
18.
A new 2D analytical drain current model is presented for symmetric double-gate fully depleted nanoscale SOI MOSFETs. Investigation of device parameters like transconductance for double-gate fully depleted nanoscale SOI MOSFETs is also carried out. Finally this work is concluded by modeling the cut-off frequency, which is one of the main figures of merit for analog/RF performance for double-gate fully depleted nanoscale SOI MOSFETs. The results of the modeling are compared with those obtained by a 2D ATLAS device simulator to verify the accuracy of the proposed model. 相似文献